Laurent Pinchart [Fri, 10 May 2013 14:48:36 +0000 (16:48 +0200)]
gpio-rcar: Make the platform data gpio_base field signed
The gpio_base field is used to specify the desired GPIO base for the
GPIO controller. The GPIO core can automatically allocate a GPIO number
range when the base is set to -1. To make this possible, make the field
signed.
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Maxime Ripard [Tue, 14 May 2013 15:38:43 +0000 (17:38 +0200)]
ARM: shmobile: r8a7790: Remove init_irq declaration in machine description
Commit ebafed7a ("ARM: irq: Call irqchip_init if no init_irq function is
specified") removed the need to explictly setup the init_irq field in
the machine description when using only irqchip_init. Remove that
declaration for shmobile as well.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Maxime Ripard [Tue, 14 May 2013 15:38:42 +0000 (17:38 +0200)]
ARM: shmobile: r8a73a4: Remove init_irq declaration in machine description
Commit ebafed7a ("ARM: irq: Call irqchip_init if no init_irq function is
specified") removed the need to explictly setup the init_irq field in
the machine description when using only irqchip_init. Remove that
declaration for shmobile as well.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Maxime Ripard [Tue, 14 May 2013 15:38:41 +0000 (17:38 +0200)]
ARM: shmobile: emev2: Remove init_irq declaration in machine description
Commit ebafed7a ("ARM: irq: Call irqchip_init if no init_irq function is
specified") removed the need to explictly setup the init_irq field in
the machine description when using only irqchip_init. Remove that
declaration for shmobile as well.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Maxime Ripard [Tue, 14 May 2013 15:38:40 +0000 (17:38 +0200)]
ARM: shmobile: lager: Remove init_irq declaration in machine description
Commit ebafed7a ("ARM: irq: Call irqchip_init if no init_irq function is
specified") removed the need to explictly setup the init_irq field in
the machine description when using only irqchip_init. Remove that
declaration for shmobile as well.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Maxime Ripard [Tue, 14 May 2013 15:38:39 +0000 (17:38 +0200)]
ARM: shmobile: kzm9g: Remove init_irq declaration in machine description
Commit ebafed7a ("ARM: irq: Call irqchip_init if no init_irq function is
specified") removed the need to explictly setup the init_irq field in
the machine description when using only irqchip_init. Remove that
declaration for shmobile as well.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Maxime Ripard [Tue, 14 May 2013 15:38:38 +0000 (17:38 +0200)]
ARM: shmobile: ape6evm: Remove init_irq declaration in machine description
Commit ebafed7a ("ARM: irq: Call irqchip_init if no init_irq function is
specified") removed the need to explictly setup the init_irq field in
the machine description when using only irqchip_init. Remove that
declaration for shmobile as well.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add VIN DATA[0:8]/CLK/HSYNC/VSYNC pin groups to R8A7778 PFC driver.
While at it, add SH_PFC_MUX8() macro for 8-bit data busses.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
[Sergei: updated the copyrights, added SH_PFC_MUX8() macro for 8-bit data bus,
made use of SH_PFC_*() macros to define the pin groups.] Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Laurent Pinchart [Fri, 26 Oct 2012 13:38:48 +0000 (15:38 +0200)]
pwm: Add Renesas TPU PWM driver
The Timer Pulse Unit (TPU is a 4-channels 16-bit timer used to generate
waveforms. This driver exposes PWM functions through the PWM API for
other drivers to use.
The code is loosely based on the leds-renesas-tpu driver by Magnus Damm
and the TPU PWM driver shipped in the Armadillo EVA 800 kernel sources.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Tested-by: Simon Horman <horms@verge.net.au> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The sh73a0 has an internal power gate on the VCCQ power supply for the
SDHI0 device that is controlled (for some strange reason) by a bit in a
PFC register. This feature should be exposed as a regulator.
As the same register is also used for pin control purposes there is no
way to achieve atomic read/write sequences with a separate regulator
driver. We thus need to implement the regulator here.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Bastian Hecht [Wed, 8 May 2013 13:20:04 +0000 (15:20 +0200)]
irqchip: Add irqchip_init dummy function
We add an empty irqchip_init dummy function for cases in which
CONFIG_IRQCHIP is not used. In these cases irqchip.c is not compiled,
but a funtion call may still be present in architecture code, that in
runtime doesn't get hit.
E.g. this is needed in the arch/arm/mach-shmobile/intc-r8a7740.c
interrupt setup code where OF use and non OF us is both handled in one
file.
Signed-off-by: Bastian Hecht <hechtb+renesas@gmail.com>
[horms+renesas@verge.net.au: Make non-CONFIG_IRQCHIP version static inline
and remove trailing ';'.] Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Provide alternate board code for the Armadillo800EVA to demonstrate how
DT may be used given the current state of driver device tree support.
This is intended to act as a reference for mach-shmobile developers.
This a rather bare bone version with the following devices supported:
- GIC
- irqpins
- i2c0/1
- touchscreen
Signed-off-by: Bastian Hecht <hechtb+renesas@gmail.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
ARM: shmobile: bockw: add dummy regulators for SMSC
SMSC driver will try to get regulator if .config had CONFIG_REGULATOR,
and, shmobile_defconfig has it.
SMSC driver on Bock-W board will be failed if it doens't have
dummy regulator settings.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Debug serial (= SCIF0) is connected to CN9 upper side,
and it is shared by RCAN.
This patch adds SCIF/RCAN dipswitch explanation on
comment area for developers.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Bock-W SMSC needs FPGA settings which enables interrupt.
This patch does it on bockw_init() function.
As notes for future, this FPGA settings should be updated,
since this FPGA is using cascaded interrupt.
Current code is assuming that this FPGA interrupt user is only SMSC.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Acked-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Simon Horman [Thu, 18 Apr 2013 12:21:09 +0000 (21:21 +0900)]
ARM: shmobile: marzen: Use INTC External IRQ pin driver for SMSC
Update the marzen board to use the INTC External IRQ pin driver for SMSC.
This code was originally posted by Magnus Damm as part of
"ARM: shmobile: INTC External IRQ pin driver on r8a7779"
but somehow omitted when I applied that patch.
Cc: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
ARM: shmobile: ape6evm: MP clock parent become EXTAL2
The orignal commit 3263e09d287fbaa8a9424b5e69396599a3bbd518
(ARM: shmobile: Initial r8a73a4 SoC support V3)
put MP clock parent as EXTAL2, but its code was removed
on DIV6 clock support commit.
This patch makes it consistent.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
We add 2 Suspend to RAM modes:
- A3SM PLL0 on/off: Power domain A3SM that contains the ARM core
and the 2nd level cache with either PLL0 on
or off
As the suspend to memory mechanism we use A3SM PLL off. A3SM PLL on
is included here too, so CPUIdle can use both power down modes (not
included in this patch).
The setup of the SYSC regarding the external IRQs is taken from
pm-sh7372.c from Magnus Damm.
Sergei Shtylyov [Tue, 9 Apr 2013 17:48:59 +0000 (21:48 +0400)]
ARM: shmobile: R8A7779: fix Ether device name
While recasting the commit "ARM: shmobile: R8A7779: add Ether support", I made a
typo in the platform device's name: used underscore instead of hyphen.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
sh-pfc: r8a7740: Replace GPIO_PORTx enum with GPIO port numbers
The PFC GPIO API implementation moved to using port numbers. Replace all
GPIO_PORTx enum usage with the corresponding port number. The GPIO_PORTx
enum values are identical to the port number on this platform.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
ARM: shmobile: armadillo800eva: Replace GPIO_PORTx with GPIO port numbers
The PFC GPIO API implementation moved to using port numbers. Replace all
GPIO_PORTx enum usage with the corresponding port number. The GPIO_PORTx
enum values are identical to the port number on this platform.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The r8a7740 has two LCDC units and two sets of LCDC output signals. By
default LCDC0 is routed to the LCD0 signals, and LCDC1 to the LCD1
signals. However, LCDC1 can be routed to the LCD0 signals by setting bit
MSEL6 in MSEL3CR (the LCD0 signals are further pinmuxed the usual way).
This could be configured by duplicating the LCD0 pin groups for LCDC1.
However, this would unnecessarily complicate the LCD pin groups, as no
r8a7740 board supported in mainline use such a configuration. Hardcode
the MSEL3CR MSEL6 bit to 0 for now.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
projects / karo-tx-linux.git / log