Shawn Guo [Tue, 21 Mar 2017 08:38:21 +0000 (16:38 +0800)]
clk: zte: set CLK_SET_RATE_PARENT for a few zx296718 clocks
To support VOU VGA display driver with different modes, we need to set
flag for a few clocks, so that clk_set_rate() call in VOU driver can get
VGA device desired pixel rate.
While at it, the divider between pll_vga and clk_vga gets corrected, as
it's 1:1 instead of 1:2.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Reviewed-by: Jun Nie <jun.nie@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
clk: imx: clk-imx6ul: The i.mx6ul has no aips_tz3 clock
The clock was mapped on CG15 (gpio2_clocks) in the CCRG0 register.
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Robin van der Gracht <robin@protonic.nl> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Ray Jui [Wed, 5 Apr 2017 19:53:37 +0000 (12:53 -0700)]
clk: iproc: Remove redundant check
Remove the redundant check of 'rate' in the if statement of the
'pll_set_rate' function
Reported-by: David Binderman <dcb314@hotmail.com> Signed-off-by: Ray Jui <ray.jui@broadcom.com> Fixes: 5fe225c105fd ("clk: iproc: add initial common clock support") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Merge tag 'v4.12-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next
Pull rockchip clk driver updates from Heiko Stuebner:
General rockchip clock changes for 4.12. Contains some new clock-ids
as well as fixups of the clock-ids on rk3368 timers, which were unused
and completely wrong (more and differently named timers).
Also there is one new clock on rk3328 using the muxgrf type, a fix for
pll enablement which should wait for the pll to lock before continuing,
some more critical clocks and the rename of the rk1108 to rv1108, as the
soc seems to have been using a preliminary name before its actual release.
The plan is to have the driver changes (pinctrl, clk) go through the
respective maintainer trees and once everything landed in mainline do
the rename of the devicetree files. With the dts-include change in the
clock rename, we also keep everything compiling and thus bisectability.
* tag 'v4.12-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
clk: rockchip: add pll_wait_lock for pll_enable
clk: rockchip: rename RK1108 to RV1108
dt-bindings: rk1108-cru: rename RK1108 to RV1108
clk: rockchip: mark some rk3368 core-clks as critical
clk: rockchip: export SCLK_TIMERXX id for timers on rk3368
clk: rockchip: describe clk_gmac using the new muxgrf type on rk3328
clk: rockchip: add clock ids for timer10-15 of RK3368 SoCs
clk: rockchip: fix up rk3368 timer-ids
clk: rockchip: add rk3328 clk_mac2io_ext ID
clk: rockchip: Set "ignore unused" for PMU M0 clocks on rk3399
Merge tag 'clk-renesas-for-v4.12-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next
Pull Renesas clk driver updates from Geert Uytterhoeven:
- Add support for the Clock Pulse Generator / Module Standby and
Software Reset module on revision ES2.0 of the R-Car H3 SoC, which
differs from ES1.x in some areas.
- Add IMR clocks for R-Car H3 and M3-W,
- Add workaround for PLL0/2/4 errata on R-Car H3 ES1.0,
- Small fixes and cleanups.
* tag 'clk-renesas-for-v4.12-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
clk: renesas: rcar-gen3-cpg: Add support for RCLK on R-Car H3 ES2.0
clk: renesas: r8a7795: Add support for R-Car H3 ES2.0
clk: renesas: Add r8a7795 ES2.0 CPG Core Clock Definitions
clk: renesas: cpg-mssr: Add support for fixing up clock tables
clk: renesas: rcar-gen3: Add workaround for PLL0/2/4 errata on H3 ES1.0
clk: renesas: rcar-gen3-cpg: Pass mode pins to rcar_gen3_cpg_init()
clk: renesas: r8a7796: Reformat core clock table
clk: renesas: r8a7795: Reformat core clock table
clk: renesas: r8a7796: Correct name of watchdog clock
clk: renesas: r8a7795: Correct name of watchdog clock
clk: renesas: r8a7795: Correct parent clock and sort order for Audio DMACs
clk: renesas: r8a7796: Add IMR clocks
clk: renesas: r8a7795: Add IMR clocks
Stephen Boyd [Tue, 4 Apr 2017 22:33:18 +0000 (15:33 -0700)]
Merge branch 'for-4.12-ti-clk-cleanups' of https://github.com/t-kristo/linux-pm into clk-next
* 'for-4.12-ti-clk-cleanups' of https://github.com/t-kristo/linux-pm:
clk: ti: convert to use proper register definition for all accesses
clk: ti: dpll44xx: fix clksel register initialization
clk: ti: gate: export gate_clk_ops locally
clk: ti: divider: add driver internal API for parsing divider data
clk: ti: divider: convert TI divider clock to use its own data representation
clk: ti: mux: convert TI mux clock to use its internal data representation
clk: ti: drop unnecessary MEMMAP_ADDRESSING flag
clk: ti: omap4: cleanup unnecessary clock aliases
clk: ti: enforce const types on string arrays
clk: ti: move omap2_init_clk_clkdm under TI clock driver
clk: ti: add clkdm_lookup to the exported functions
clk: ti: use automatic clock alias generation framework
clk: ti: add API for creating aliases automatically for simple clock types
clk: ti: add support for automatic clock alias generation
clk: ti: remove un-used definitions from public clk_hw_omap struct
Leo Yan [Sat, 25 Mar 2017 18:23:15 +0000 (02:23 +0800)]
clk: hi6220: add debug APB clock
The debug APB clock is absent in hi6220 driver, so this patch is to add
support for it.
Signed-off-by: Leo Yan <leo.yan@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Jon Hunter [Mon, 27 Mar 2017 11:01:05 +0000 (12:01 +0100)]
clk: tegra: Don't reset PLL-CX if it is already enabled
Commit 8dce89a1c2cf ("clk: tegra: Don't warn for PLL defaults
unnecessarily") changed the tegra210_pllcx_set_defaults() function
causing the PLL to always be reset regardless of whether it is in-use.
This function was changed so that resetting of the PLL will only be
skipped if the PLL is enabled AND 'pllcx->params->defaults_set' is not
true. However, the 'pllcx->params->defaults_set' is always true and
hence, the PLL is now always reset. This causes the boot to fail on the
Tegra210 Smaug where the PLL is already enabled and in-use. Fix this by
only resetting the PLL if not in-use and only printing the warning that
the defaults are not set after we have checked the default settings.
Fixes: 8dce89a1c2cf ("clk: tegra: Don't warn for PLL defaults unnecessarily") Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
Alex Frid [Wed, 22 Mar 2017 13:38:19 +0000 (15:38 +0200)]
clk: tegra: Propagate clk_out_x rate to parent
Given that externx can only be used as a parent for clk_out_x, it makes
sense to propagate requests to make clk_out_x easier to handle.
Signed-off-by: Alex Frid <afrid@nvidia.com> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
clk: renesas: r8a7795: Add support for R-Car H3 ES2.0
The Clock Pulse Generator / Module Standby and Software Reset module in
R-Car H3 ES2.0 differs from ES1.x in the following areas:
- More core clocks (S0D2, S0D3, S0D6, S0D8, S0D12),
- Different parent clocks for AUDMAC, EtherAVB, FCP, FDP, IMR,
SYS-DMAC, VIN, VSPB, VSPI,
- Removal of modules CSI21, FCPCI, FCPF2, FCPVD3, FCPVI2, FDP1-2,
USB3-IF1, VSPD3, VSPI2,
- Addition of modules EHCI3, HS-USB-IF3, USB-DMAC3-0, USB-DMAC3-1.
The goal is twofold:
1. Support both the ES1.x and ES2.0 SoC revisions in a single binary
for now,
2. Make it clear which code supports ES1.x, so it can easily be
identified and removed later, when production SoCs are deemed
ubiquitous.
This is achieved by:
- Updating the clock tables for the latest revision (ES2.0), but not
removing clocks that only exist on earlier revisions (ES1.x),
- Detecting the SoC revision at runtime using the new soc_device_match()
API, and fixing up the clocks tables to match the actual SoC
revision, by:
- NULLifying core and module clocks of modules that do not exist,
- Reparenting module clocks that have a different parent on ES1.x.
Based on R-Car Gen3 Hardware User's Manual rev. 0.53E.
Add all R-Car H3 ES2.0 Clock Pulse Generator Core Clock Outputs, as
listed in Table 8.2a ("List of Clocks [R-Car H3]") of the R-Car Gen3
Hardware User's Manual rev. 0.53E.
clk: renesas: cpg-mssr: Add support for fixing up clock tables
The same SoC may have different clocks and/or module clock parents,
depending on SoC revision. One option is to use different sets of clock
tables for each SoC revision. However, if the differences are small, it
is much more space-efficient to have a single set of clock tables, and
fix those up at runtime instead.
Hence provide three helpers:
- Two helpers to NULLify core and module clocks that do not exist on
some revisions (NULLified clocks are skipped during the registration
phase),
- One helper to reparent module clocks that have different clock
parents.
Stephen Boyd [Thu, 23 Mar 2017 23:08:46 +0000 (16:08 -0700)]
Merge tag 'sunxi-clk-fixes-for-4.11' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-fixes
Pull Allwinner clock fixes from Maxime Ripard:
A few fixes for a bunch of clocks on a few SoCs. The most important one is
probably one that fixes the NKMP clock frequency calculation and could end
up with clocking the CPU frequency to out of bounds rates.
* tag 'sunxi-clk-fixes-for-4.11' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux:
clk: sunxi-ng: fix recalc_rate formula of NKMP clocks
clk: sunxi-ng: Fix div/mult settings for osc12M on A64
clk: sunxi-ng: sun6i: Fix enable bit offset for hdmi-ddc module clock
clk: sunxi: ccu-sun5i needs nkmp
clk: sunxi-ng: mp: Adjust parent rate for pre-dividers
Andy Yan [Fri, 17 Mar 2017 17:18:38 +0000 (18:18 +0100)]
clk: rockchip: rename RK1108 to RV1108
Rockchip finally named the SOC as RV1108, so change it.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
[include rename in rk1108.dtsi to prevent compile errors] Signed-off-by: Heiko Stuebner <heiko@sntech.de>
clk: renesas: rcar-gen3-cpg: Pass mode pins to rcar_gen3_cpg_init()
Pass the mode pin states from the SoC-specific CPG/MSSR driver to the
R-Car Gen3 CPG driver core, as their state will be needed to make some
core clock configuration decisions.
In normal operation pll_u is under hardware control and has a fixed rate
of 480MHz. Hardware will turn on pll_u on whenever any of the XUSB
powerdomains is on. From a software point of view we model this is if
pll_u is always on using a fixed rate clock. However the bootloader
might or might not have configured pll_u this way. So we will check the
current state of pll_u at boot and reconfigure it if required.
There are 3 possiblities at kernel boot:
1) pll_u is under hardware control: do nothing
2) pll_u is under hardware control and enabled: enable hardware control
3) pll_u is disabled: enable pll_u and enable hardware control
In all cases we also check if UTMIPLL is under hardware control at boot
and configure it for hardware control if that is not the case.
The same is done during SC7 resume.
Thanks to Joseph Lo <josephl@nvidia.com> for bug fixes.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
Mikko Perttunen [Thu, 2 Mar 2017 14:16:16 +0000 (16:16 +0200)]
clk: tegra: Implement reset control reset
For completeness, also implement this reset framework API for Tegra.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Reviewed-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Arto Merilainen <amerilainen@nvidia.com> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
clk: tegra: Fix disable unused for clocks sharing enable bit
In case 2 clocks share an enable bit and one of them is enabled by a
driver and the other one is not, CCF will think it's enabled because it
will only look at the HW state. Therefore it will disable the clock and
thus also disable the other clock which was enabled. Solve this by
reading the initial state of the enable bit and incrementing the
refcount if it's set.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Tested-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
Add a super clock type which implements both mux and divider. This is
used for aclk.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Tested-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
Tegra210 has 3 inputs for Digital Microphones (DMICs). Provide the
required clocks for them.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Tested-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
checkpatch now warns for const ** and expects const * const * to be used
instead. This means we have to update the prototypes and function
declarations to handle this change.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Tested-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
Tegra210 has 3 DMIC inputs which can be clocked from the recovered clock
of several other audio inputs (eg. i2s0, i2s1, ...). To model this, we
add a 3 new clocks similar to the audio* clocks which handle the same
function for the I2S and SPDIF clocks.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Tested-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
This clock is used to clock the HDMI CEC interface.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Tested-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
When used as part of fractional ndiv calculations, the current range is
not enough because the denominator of the fraction is multiplied with m.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Tested-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
Return the actually achieved rate in cfg->output_rate rather than just
the requested rate. This is important to make clk_round_rate() return
the correct result.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Tested-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
clk: tegra: Don't warn for PLL defaults unnecessarily
If the PLL is on, only warn if the defaults are not yet set. Otherwise
be silent.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Tested-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Tested-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
The parent for afi is actually mselect, not clk_m.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Tested-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
The 2 ISP clocks (ispa and ispb) share a mux/divider control. So model
this as 1 mux/divider clock and child gate clocks.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Tested-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
pll_a1 was using CLK_RST_CONTROLLER_PLLA1_MISC_0 for IDDQ control rather
than the correct register CLK_RST_CONTROLLER_PLLA1_MISC_1. Also add
pll_a1 to the set of clocks defined for Tegra210.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Tested-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
Icenowy Zheng [Fri, 17 Mar 2017 20:19:43 +0000 (04:19 +0800)]
clk: sunxi-ng: fix recalc_rate formula of NKMP clocks
In commit e66f81bbd746 ("clk: sunxi-ng: Implement factors offsets"), the
final formula of NKMP clocks' recalc_rate is refactored; however, the
refactored formula broke the calculation due to some C language operand
priority problem -- the priority of operand >> is lower than * and /,
makes the formula being parsed as "(parent_rate * n * k) >> (p / m)", but
it should be "(parent_rate * n * k >> p) / m".
Add the pair of parentheses to fix up this issue. This pair of
parentheses used to exist in the old formula.
Philipp Tomsich [Wed, 15 Mar 2017 11:23:58 +0000 (12:23 +0100)]
clk: sunxi-ng: Fix div/mult settings for osc12M on A64
The mult/div for osc12M was previously backwards (giving a 48M rate
for osc12M). Fix it.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Christoph Muellner <christoph.muellner@theobroma-systems.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Elaine Zhang [Mon, 6 Feb 2017 02:50:35 +0000 (10:50 +0800)]
clk: rockchip: describe clk_gmac using the new muxgrf type on rk3328
With the newly introduced clk type for muxes in the grf we now can
describe some missing clocks, like the clk_gmac2io and clk_gmac2phy
that selects between clk_mac2io_src and gmac_clkin based on a bit
set in the general register files.
Elaine Zhang [Tue, 7 Mar 2017 11:05:15 +0000 (19:05 +0800)]
clk: rockchip: fix up rk3368 timer-ids
The timer-ids are wrong compared to the manual, probably due a simple
copy-paste mistake from the otherwise very similar rk3288. And there
are even more timers in the system than the ones wrongly listed here.
Timer-Ids were unused both in clock-driver as well as devicetree
till now, so fixing them won't break anything.
Tero Kristo [Thu, 9 Feb 2017 09:24:37 +0000 (11:24 +0200)]
clk: ti: convert to use proper register definition for all accesses
Currently, TI clock driver uses an encapsulated struct that is cast into
a void pointer to store all register addresses. This can be considered
as rather nasty hackery, and prevents from expanding the register
address field also. Instead, replace all the code to use proper struct
in place for this, which contains all the previously used data.
This patch is rather large as it is touching multiple files, but this
can't be split up as we need to avoid any boot breakage.
Signed-off-by: Tero Kristo <t-kristo@ti.com> Acked-by: Tony Lindgren <tony@atomide.com>
clksel register pointer should be used for the DPLL-MX autoidle handling.
Currently this is not setup at all. Fix by adding proper handling for the
register.
Signed-off-by: Tero Kristo <t-kristo@ti.com> Acked-by: Tony Lindgren <tony@atomide.com>
Tero Kristo [Thu, 9 Feb 2017 12:45:45 +0000 (14:45 +0200)]
clk: ti: divider: convert TI divider clock to use its own data representation
Instead of using the generic clock driver data struct, use one internal
for the TI clock driver itself. This allows modifying the register access
parts in subsequent patch.
Signed-off-by: Tero Kristo <t-kristo@ti.com> Acked-by: Tony Lindgren <tony@atomide.com>
Tero Kristo [Thu, 9 Feb 2017 12:40:40 +0000 (14:40 +0200)]
clk: ti: mux: convert TI mux clock to use its internal data representation
Instead of using the generic clock driver data struct, use one internal
for the TI clock driver itself. This allows modifying the register access
parts in subsequent patch.
Signed-off-by: Tero Kristo <t-kristo@ti.com> Acked-by: Tony Lindgren <tony@atomide.com>
Tero Kristo [Thu, 29 Sep 2016 09:05:00 +0000 (12:05 +0300)]
clk: ti: add API for creating aliases automatically for simple clock types
This API generates clock aliases automatically for simple clock types
(fixed-clock, fixed-factor-clock), so that we don't need to add the data
for these statically into tables. Shall be called from the SoC specific
clock init.
Signed-off-by: Tero Kristo <t-kristo@ti.com> Acked-by: Tony Lindgren <tony@atomide.com>
Tero Kristo [Thu, 29 Sep 2016 09:00:57 +0000 (12:00 +0300)]
clk: ti: add support for automatic clock alias generation
Large portions of the OMAP framework still depend on the support of
having clock aliases in place, so add support functions for generating
these automatically.
Signed-off-by: Tero Kristo <t-kristo@ti.com> Acked-by: Tony Lindgren <tony@atomide.com>
Heiko Stuebner [Wed, 1 Mar 2017 21:00:42 +0000 (22:00 +0100)]
clk: rockchip: Make uartpll a child of the gpll on rk3036
The shared uart-pll is on boot a child of the apll that can get changed
by cpu frequency scaling. So move it away to the more stable gpll to
make sure the uart doesn't break on cpu frequency changes.
This turned up during the 4.11 merge-window when commit 6a171b299379 ("serial: 8250_dw: Allow hardware flow control to be used")
added general termios enablement making the uart on rk3036 change
frequency and thus making it susceptible for the frequency scaling issue.
Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Heiko Stuebner [Wed, 1 Mar 2017 21:00:41 +0000 (22:00 +0100)]
clk: rockchip: add "," to mux_pll_src_apll_dpll_gpll_usb480m_p on rk3036
The mux_pll_src_apll_dpll_gpll_usb480m_p parent list was missing a ","
between the 3rd and 4th parent names, making them fall together and thus
lookups fail. Fix that.
Fixes: 5190c08b2989 ("clk: rockchip: add clock controller for rk3036") Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Leonard Crestez [Mon, 20 Feb 2017 13:20:56 +0000 (15:20 +0200)]
clk: core: Copy connection id
Some drivers use sprintf to build clk connection id names but the clk
core will save those strings and occasionally print them back. Duplicate
the con_id strings instead of fixing all the users.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Thomas Petazzoni [Wed, 21 Dec 2016 10:26:55 +0000 (11:26 +0100)]
dt-bindings: arm: update Armada CP110 system controller binding
It turns out that in the CP110 HW block present in Marvell Armada
7K/8K SoCs, gatable clock n°18 not only controls SD/MMC, but also the
GOP block. This commit updates the Device Tree binding for this piece
of hardware accordingly.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Arnd Bergmann [Tue, 14 Feb 2017 21:29:45 +0000 (22:29 +0100)]
clk: sunxi: ccu-sun5i needs nkmp
A randconfig build ran into this rare link error:
drivers/clk/sunxi-ng/ccu-sun5i.o:(.data.__compound_literal.1+0x4): undefined reference to `ccu_nkmp_ops'
drivers/clk/sunxi-ng/ccu-sun5i.o:(.data.__compound_literal.7+0x4): undefined reference to `ccu_nkmp_ops'
This adds the missing 'select'.
Fixes: 5e73761786d6 ("clk: sunxi-ng: Add sun5i CCU driver") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Chen-Yu Tsai [Tue, 14 Feb 2017 03:35:22 +0000 (11:35 +0800)]
clk: sunxi-ng: mp: Adjust parent rate for pre-dividers
The MP style clocks support an mux with pre-dividers. While the driver
correctly accounted for them in the .determine_rate callback, it did
not in the .recalc_rate and .set_rate callbacks.
This means when calculating the factors in the .set_rate callback, they
would be off by a factor of the active pre-divider. Same goes for
reading back the clock rate after it is set.
Douglas Anderson [Tue, 14 Feb 2017 21:01:14 +0000 (13:01 -0800)]
clk: rockchip: Set "ignore unused" for PMU M0 clocks on rk3399
The PMU Cortex M0 on rk3399 is intended to be used for things like
DDRFreq transitions, suspend/resume, and other things that are the
purview of ARM Trusted Firmware and not the kernel. As such, the
kernel shouldn't be messing with the clocks. Add CLK_IGNORE_UNUSED to
these clocks.
Without this change, the following was observed on a Chromebook with a
rk3399 (using not-yet-upstream ARM Trusted Firmware code and
not-yet-upstream kernel code based on kernel-4.4):
1. We init the clock framework.
2. We start up "DDRFreq", which causes ATF to occasionally fire up the
M0 for transitions. Each time ATF fires up the M0 it will turn on
these clocks and each time it is done it will turn them off.
3. We finally get to the the part of the kernel that calls
clk_disable_unused() and we disables the clocks.
You can see the race above. Basically everything is fine as long as
ARM Trusted Firmware isn't starting up the M0 at exactly the same time
that the kernel is disabling unused clocks. ...but if the race
happens then we go boom.
Signed-off-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
4) Fix sendmsg deadlock in rxrpc, from David Howells.
5) Add missing RCU locking to transport hashtable scan, from Xin Long.
6) Fix potential packet loss in mlxsw driver, from Ido Schimmel.
7) Fix race in NAPI handling between poll handlers and busy polling,
from Eric Dumazet.
8) TX path in vxlan and geneve need proper RCU locking, from Jakub
Kicinski.
9) SYN processing in DCCP and TCP need to disable BH, from Eric
Dumazet.
10) Properly handle net_enable_timestamp() being invoked from IRQ
context, also from Eric Dumazet.
11) Fix crash on device-tree systems in xgene driver, from Alban Bedel.
12) Do not call sk_free() on a locked socket, from Arnaldo Carvalho de
Melo.
13) Fix use-after-free in netvsc driver, from Dexuan Cui.
14) Fix max MTU setting in bonding driver, from WANG Cong.
15) xen-netback hash table can be allocated from softirq context, so use
GFP_ATOMIC. From Anoob Soman.
16) Fix MAC address change bug in bgmac driver, from Hari Vyas.
17) strparser needs to destroy strp_wq on module exit, from WANG Cong.
* git://git.kernel.org/pub/scm/linux/kernel/git/davem/net: (69 commits)
strparser: destroy workqueue on module exit
sfc: fix IPID endianness in TSOv2
sfc: avoid max() in array size
rds: remove unnecessary returned value check
rxrpc: Fix potential NULL-pointer exception
nfp: correct DMA direction in XDP DMA sync
nfp: don't tell FW about the reserved buffer space
net: ethernet: bgmac: mac address change bug
net: ethernet: bgmac: init sequence bug
xen-netback: don't vfree() queues under spinlock
xen-netback: keep a local pointer for vif in backend_disconnect()
netfilter: nf_tables: don't call nfnetlink_set_err() if nfnetlink_send() fails
netfilter: nft_set_rbtree: incorrect assumption on lower interval lookups
netfilter: nf_conntrack_sip: fix wrong memory initialisation
can: flexcan: fix typo in comment
can: usb_8dev: Fix memory leak of priv->cmd_msg_buffer
can: gs_usb: fix coding style
can: gs_usb: Don't use stack memory for USB transfers
ixgbe: Limit use of 2K buffers on architectures with 256B or larger cache lines
ixgbe: update the rss key on h/w, when ethtool ask for it
...
Linus Torvalds [Sat, 4 Mar 2017 19:36:19 +0000 (11:36 -0800)]
Merge tag 'kvm-4.11-2' of git://git.kernel.org/pub/scm/virt/kvm/kvm
Pull more KVM updates from Radim Krčmář:
"Second batch of KVM changes for the 4.11 merge window:
PPC:
- correct assumption about ASDR on POWER9
- fix MMIO emulation on POWER9
x86:
- add a simple test for ioperm
- cleanup TSS (going through KVM tree as the whole undertaking was
caused by VMX's use of TSS)
- fix nVMX interrupt delivery
- fix some performance counters in the guest
... and two cleanup patches"
* tag 'kvm-4.11-2' of git://git.kernel.org/pub/scm/virt/kvm/kvm:
KVM: nVMX: Fix pending events injection
x86/kvm/vmx: remove unused variable in segment_base()
selftests/x86: Add a basic selftest for ioperm
x86/asm: Tidy up TSS limit code
kvm: convert kvm.users_count from atomic_t to refcount_t
KVM: x86: never specify a sample period for virtualized in_tx_cp counters
KVM: PPC: Book3S HV: Don't use ASDR for real-mode HPT faults on POWER9
KVM: PPC: Book3S HV: Fix software walk of guest process page tables
Linus Torvalds [Sat, 4 Mar 2017 19:26:18 +0000 (11:26 -0800)]
Merge tag 'staging-4.11-rc1-part2' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging
Pull staging/IIO driver fixes from Greg KH:
"Here are a few small staging and IIO driver fixes for issues that
showed up after the big set if changes you merged last week.
Nothing major, just small bugs resolved in some IIO drivers, a lustre
allocation fix, and some RaspberryPi driver fixes for reported
problems, as well as a MAINTAINERS entry update.
All of these have been in linux-next for a week with no reported
issues"
* tag 'staging-4.11-rc1-part2' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging:
staging: fsl-mc: fix warning in DT ranges parser
MAINTAINERS: Remove Noralf Trønnes as fbtft maintainer
staging: vchiq_2835_arm: Make cache-line-size a required DT property
staging: bcm2835/mmal-vchiq: unlock on error in buffer_from_host()
staging/lustre/lnet: Fix allocation size for sv_cpt_data
iio: adc: xilinx: Fix error handling
iio: 104-quad-8: Fix off-by-one error when addressing flag register
iio: adc: handle unknow of_device_id data
Linus Torvalds [Sat, 4 Mar 2017 18:42:53 +0000 (10:42 -0800)]
Merge branch 'linus' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6
Pull crypto fixes from Herbert Xu:
- vmalloc stack regression in CCM
- Build problem in CRC32 on ARM
- Memory leak in cavium
- Missing Kconfig dependencies in atmel and mediatek
- XTS Regression on some platforms (s390 and ppc)
- Memory overrun in CCM test vector
* 'linus' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6:
crypto: vmx - Use skcipher for xts fallback
crypto: vmx - Use skcipher for cbc fallback
crypto: testmgr - Pad aes_ccm_enc_tv_template vector
crypto: arm/crc32 - add build time test for CRC instruction support
crypto: arm/crc32 - fix build error with outdated binutils
crypto: ccm - move cbcmac input off the stack
crypto: xts - Propagate NEED_FALLBACK bit
crypto: api - Add crypto_requires_off helper
crypto: atmel - CRYPTO_DEV_MEDIATEK should depend on HAS_DMA
crypto: atmel - CRYPTO_DEV_ATMEL_TDES and CRYPTO_DEV_ATMEL_SHA should depend on HAS_DMA
crypto: cavium - fix leak on curr if curr->head fails to be allocated
crypto: cavium - Fix couple of static checker errors
Linus Torvalds [Sat, 4 Mar 2017 05:36:56 +0000 (21:36 -0800)]
Merge tag 'scsi-misc' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi
Pull more SCSI updates from James Bottomley:
"This is the set of stuff that didn't quite make the initial pull and a
set of fixes for stuff which did.
The new stuff is basically lpfc (nvme), qedi and aacraid. The fixes
cover a lot of previously submitted stuff, the most important of which
probably covers some of the failing irq vectors allocation and other
fallout from having the SCSI command allocated as part of the block
allocation functions"
* tag 'scsi-misc' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi: (59 commits)
scsi: qedi: Fix memory leak in tmf response processing.
scsi: aacraid: remove redundant zero check on ret
scsi: lpfc: use proper format string for dma_addr_t
scsi: lpfc: use div_u64 for 64-bit division
scsi: mac_scsi: Fix MAC_SCSI=m option when SCSI=m
scsi: cciss: correct check map error.
scsi: qla2xxx: fix spelling mistake: "seperator" -> "separator"
scsi: aacraid: Fixed expander hotplug for SMART family
scsi: mpt3sas: switch to pci_alloc_irq_vectors
scsi: qedf: fixup compilation warning about atomic_t usage
scsi: remove scsi_execute_req_flags
scsi: merge __scsi_execute into scsi_execute
scsi: simplify scsi_execute_req_flags
scsi: make the sense header argument to scsi_test_unit_ready mandatory
scsi: sd: improve TUR handling in sd_check_events
scsi: always zero sshdr in scsi_normalize_sense
scsi: scsi_dh_emc: return success in clariion_std_inquiry()
scsi: fix memory leak of sdpk on when gd fails to allocate
scsi: sd: make sd_devt_release() static
scsi: qedf: Add QLogic FastLinQ offload FCoE driver framework.
...
WANG Cong [Fri, 3 Mar 2017 20:21:14 +0000 (12:21 -0800)]
strparser: destroy workqueue on module exit
Fixes: 43a0c6751a32 ("strparser: Stream parser for messages") Cc: Tom Herbert <tom@herbertland.com> Signed-off-by: Cong Wang <xiyou.wangcong@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
The following patchset contains Netfilter fixes for your net tree,
they are:
1) Missing check for full sock in ip_route_me_harder(), from
Florian Westphal.
2) Incorrect sip helper structure initilization that breaks it when
several ports are used, from Christophe Leroy.
3) Fix incorrect assumption when looking up for matching with adjacent
intervals in the nft_set_rbtree.
4) Fix broken netlink event error reporting in nf_tables that results
in misleading ESRCH errors propagated to userspace listeners.
====================
Signed-off-by: David S. Miller <davem@davemloft.net>
Linus Torvalds [Sat, 4 Mar 2017 00:48:48 +0000 (16:48 -0800)]
Merge branch 'libnvdimm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/nvdimm/nvdimm
Pull libnvdimm fixes from Dan Williams:
"A fix and regression test case for nvdimm namespace label
compatibility.
Details:
- An "nvdimm namespace label" is metadata on an nvdimm that
provisions dimm capacity into a "namespace" that can host a block
device / dax-filesytem, or a device-dax character device.
A namespace is an object that other operating environment and
platform firmware needs to comprehend for capabilities like booting
from an nvdimm.
The label metadata contains a checksum that Linux was not
calculating correctly leading to other environments rejecting the
Linux label.
These have received a build success notification from the kbuild
robot, and a positive test result from Nick who reported the problem"
* 'libnvdimm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/nvdimm/nvdimm:
nfit, libnvdimm: fix interleave set cookie calculation
tools/testing/nvdimm: make iset cookie predictable
Linus Torvalds [Sat, 4 Mar 2017 00:44:21 +0000 (16:44 -0800)]
Merge tag 'pci-v4.11-fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci
Pull PCI fixes from Bjorn Helgaas:
- fix NULL pointer dereferences in many DesignWare-based drivers due to
refactoring error
- fix Altera config write breakage due to my refactoring error
* tag 'pci-v4.11-fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci:
PCI: altera: Fix TLP_CFG_DW0 for TLP write
PCI: dwc: Fix crashes seen due to missing assignments
Linus Torvalds [Sat, 4 Mar 2017 00:20:06 +0000 (16:20 -0800)]
Merge branch 'parisc-4.11-1' of git://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linux
Pull parisc fixes and cleanups from Helge Deller:
"Nothing really important in this patchset: fix resource leaks in error
paths, coding style cleanups and code removal"
* 'parisc-4.11-1' of git://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linux:
parisc: Remove flush_user_dcache_range and flush_user_icache_range
parisc: fix a printk
parisc: ccio-dma: Handle return NULL error from ioremap_nocache
parisc: Define access_ok() as macro
parisc: eisa: Fix resource leaks in error paths
parisc: eisa: Remove coding style errors
Linus Torvalds [Sat, 4 Mar 2017 00:17:55 +0000 (16:17 -0800)]
Merge tag 'xtensa-20170303' of git://github.com/jcmvbkbc/linux-xtensa
Pull Xtensa updates from Max Filippov:
- clean up bootable image build targets: provide separate 'Image',
'zImage' and 'uImage' make targets that only build corresponding
image type. Make 'all' build all images appropriate for a platform
- allow merging vectors code into .text section as a preparation step
for XIP support
- fix handling external FDT when the kernel is built without
BLK_DEV_INITRD support
* tag 'xtensa-20170303' of git://github.com/jcmvbkbc/linux-xtensa:
xtensa: allow merging vectors into .text section
xtensa: clean up bootable image build targets
xtensa: move parse_tag_fdt out of #ifdef CONFIG_BLK_DEV_INITRD
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