Kevin Hilman [Fri, 23 Aug 2013 18:38:51 +0000 (11:38 -0700)]
Merge tag 'imx-soc-3.12' of git://git.linaro.org/people/shawnguo/linux-2.6 into next/soc
From Shawn Guo:
It contains a bunch of imx soc updates for 3.12.
- Add more ethernet phy fixups for imx6 boards
- Add some missing imx6q clocks into clock driver
- Add new clock types fixup mux and div to work around some ugly
hardware defect
- Consolidate L2 cache initialization function, so that it can be used
on more i.MX SoCs
- Replace magic numbers in mach-imx6q.c with well defined macros
- Small fixes for imx6q and pllv3 clock drivers
- Some random updates on imx defconfig files
* tag 'imx-soc-3.12' of git://git.linaro.org/people/shawnguo/linux-2.6: (33 commits)
phy: micrel: Add definitions for common Micrel PHY registers
ARM: imx: Re-select CONFIG_SND_SOC_IMX_MC13783 option
ARM: imx: Move anatop related from board file to anatop driver
ARM: imx_v6_v7_defconfig: Enable wireless support
ARM: imx_v4_v5_defconfig: Cleanup imx_v4_v5_defconfig
ARM: imx_v6_v7_defconfig: Add SATA support
ARM: imx_v6_v7_defconfig: Cleanup imx_v6_v7_defconfig
ARM: mx53: Allow suspend/resume
ARM: mach-imx: Select ARM_CPU_SUSPEND at ARCH_MXC level
ARM: imx_v6_v7_defconfig: Select CONFIG_TOUCHSCREEN_EGALAX
ARM: imx6q: add vdoa gate clock
ARM: imx6q: add the missing cko output selection
ARM: imx6q: add cko2 clocks
ARM: imx6q: add spdif gate clock
ARM: imx: clk-pllv3: improve the timeout waiting method
ARM: imx6: change some clocks to fixup clocks
ARM: imx: add common clock support for fixup mux
ARM: imx: add common clock support for fixup div
ARM: imx: Select MIGHT_HAVE_CACHE_L2X0
ARM: imx: fix imx_init_l2cache storage class
...
Kevin Hilman [Fri, 23 Aug 2013 18:37:18 +0000 (11:37 -0700)]
Merge tag 'imx-weim-3.12' of git://git.linaro.org/people/shawnguo/linux-2.6 into next/soc
From Shawn Guo:
This is a patch series that updates imx-weim bus driver to have it
support more i.MX SoCs. Because there is no maintainer for
drivers/bus so far, I'm forwarding it through IMX tree for 3.12 merge
window.
* tag 'imx-weim-3.12' of git://git.linaro.org/people/shawnguo/linux-2.6:
drivers: bus: imx-weim: Add support for i.MX1/21/25/27/31/35/50/51/53
drivers: bus: imx-weim: Add missing platform_driver.owner field
drivers: bus: imx-weim: use module_platform_driver_probe()
drivers: bus: imx-weim: Simplify error path
drivers: bus: imx-weim: Remove private driver data
Kevin Hilman [Thu, 22 Aug 2013 19:07:15 +0000 (12:07 -0700)]
Merge tag 'davinci-for-v3.12/dt' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci into next/soc
From Sekhar Nori:
DaVinci DT updates for v3.12
----------------------------
This set of patches add ethernet DT nodes
for DA850 and also remove now unneeded
specification of UART clock frequency so
kernel can now boot irrespective of what
the bootloader setting of UART frequency is.
* tag 'davinci-for-v3.12/dt' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci:
ARM: davinci: da850: do not specify clock_frequency for UART DT node
ARM: davinci: da850: add DT node for ethernet
ARM: davinci: da850: add OF_DEV_AUXDATA entry for davinci_emac
ARM: davinci: da850: add OF_DEV_AUXDATA entry for mdio.
ARM: davinci: da850: add DT node for mdio device
Kevin Hilman [Thu, 22 Aug 2013 18:44:44 +0000 (11:44 -0700)]
Merge tag 'davinci-for-v3.12/soc' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci into next/soc
From Sekhar Nori:
DaVinci SoC updates for v3.12
-----------------------------
This set of SoC updates contains changes to the
way UART clock is handled to enabled DT-boot to
obtain UART clock frequency instead of relying
on DT-binding being supplied. Similarly handling
of MDIO clock is fixed to make it easier to support
MDIO in DT-boot. Finally there is patch to remove
now unnecessary setting of wake-up capable flag for
RTC.
* tag 'davinci-for-v3.12/soc' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci:
ARM: davinci: fix clock lookup for mdio device
ARM: davinci: da8xx: remove hard coding of rtc device wakeup
ARM: davinci: serial: remove davinci_serial_setup_clk()
ARM: davinci: serial: get rid of davinci_uart_config
ARM: davinci: da8xx: remove da8xx_uart_clk_enable
ARM: davinci: uart: move to devid based clk_get
Kevin Hilman [Thu, 22 Aug 2013 16:21:52 +0000 (09:21 -0700)]
Merge tag 'ux500-core-for-arm-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson into next/soc
From Linus Walleij:
Core ux500 changes for v3.12:
- Add support for restart using the PRCMU
- Move secondary startup out of INIT section
- set coherent_dma_mask for DMA40
* tag 'ux500-core-for-arm-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson:
ARM: ux500: set coherent_dma_mask for dma40
ARM: ux500: remove u8500_secondary_startup from INIT section.
ARM: ux500: add restart support via prcmu
Dinh Nguyen [Tue, 13 Aug 2013 14:59:00 +0000 (09:59 -0500)]
phy: micrel: Add definitions for common Micrel PHY registers
Add defines for common Micrel PHY setups so that other platforms
can use them. Update imx61 and sama5 hardware to use the micrel_phy.h
PHY defines.
Also add support for the KSZ9021RLRN PHY.
Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Acked-by: David S. Miller <davem@davemloft.net> CC: Andrew Victor <linux@maxim.org.za> CC: Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com> Cc: netdev@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Commit 02502da45 (ASoC: imx-mc13783: Depend on ARCH_ARM) caused the selection of
CONFIG_SND_SOC_IMX_MC13783 to be impossible due to a wrong dependency, which
caused CONFIG_SND_SOC_IMX_MC13783 to be removed after the defconfigs cleanups.
The original selection problem has been fixed by 9f19de649f (ASoC: imx-mc13783:
Make SND_SOC_IMX_MC13783 visible again), so it is possible to select
CONFIG_SND_SOC_IMX_MC13783 again as originally done.
Current imx53_pm_init() implementation is incomplete as it lacks calling
suspend_set_ops().
Use a single imx5_pm_init() function to handle both mx51 and mx53.
This allows mx53 to enter in low-power mode.
Tested on a mx53qsb:
root@freescale /$ echo mem > /sys/power/state
PM: Syncing filesystems ... done.
mmc0: card e624 removed
Freezing user space processes ... (elapsed 0.001 seconds) done.
Freezing remaining freezable tasks ... (elapsed 0.001 seconds) done.
Suspending console(s) (use no_console_suspend to debug)
... (Press Power button)
PM: suspend of devices complete after 17.067 msecs
PM: suspend devices took 0.020 seconds
PM: late suspend of devices complete after 0.954 msecs
PM: noirq suspend of devices complete after 1.288 msecs
Disabling non-boot CPUs ...
PM: noirq resume of devices complete after 0.680 msecs
PM: early resume of devices complete after 0.914 msecs
PM: resume of devices complete after 44.955 msecs
PM: resume devices took 0.050 seconds
Restarting tasks ... done.
mmc0: host does not support reading read-only switch. assuming write-enable.
mmc0: new SDHC card at address e624
mmcblk0: mmc0:e624 SU04G 3.69 GiB
mmcblk0: p1 p2 p3
libphy: 63fec000.etherne:00 - Link is Down
libphy: 63fec000.etherne:00 - Link is Up - 100/Full
root@freescale /$
The clock output on imx6q CCM_CLKO1 pad is not always cko1 clock, and
there is a multiplexer to select between cko1 and cko2. Add this
missing selection as the clock cko.
Kevin Hilman [Wed, 21 Aug 2013 23:24:22 +0000 (16:24 -0700)]
Merge tag 'sunxi-core-for-3.12-2' of https://github.com/mripard/linux into next/soc
Allwinner sunXi core additions for 3.12, take 2
These patches add machine support for the Allwinner A20 and A31 SoCs
* tag 'sunxi-core-for-3.12-2' of https://github.com/mripard/linux:
ARM: sunxi: Introduce Allwinner A20 support
ARM: sun6i: Add restart code for the A31
ARM: sunxi: Add the Allwinner A31 compatible to the machine definition
ARM: davinci: da850: do not specify clock_frequency for UART DT node
DT kernel on da850-evm comes up with garbled UART logs. This is because
of mismatch in actual module clock rate and rate specified(clock-frequency)
in DT blob. kernel should not assume or depend on bootloaders clock
configuration, instead let it find the clock rate at runtime.
Issue discussed here before arriving on this implementation:
"ARM: davinci: da850 evm: update clock rate for UART 1/2 DT nodes"
https://patchwork.kernel.org/patch/2162271/
Signed-off-by: Manjunathappa, Prakash <prakash.pm@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
davinci: da8xx/omap-l1: mark RTC as a wakeup source
Signed-off-by: Hebbar Gururaja <gururaja.hebbar@ti.com> Acked-by: Kevin Hilman <khilman@linaro.org> Acked-by: Sekhar Nori <nsekhar@ti.com> Cc: Russell King <linux@arm.linux.org.uk> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Get rid of davinci_serial_setup_clk() since its not called
from multiple places now. Instead initialize clock in
davinci_serial_init() itself. This also helps get rid of
"serial_dev" member of struct davinci_soc_info.
Signed-off-by: Manjunathappa, Prakash <prakash.pm@ti.com> Suggested-by: Sekhar Nori <nsekhar@ti.com>
[nsekhar@ti.com: split removal of davinci_serial_setup_clk()
into a separate patch.] Signed-off-by: Sekhar Nori <nsekhar@ti.com>
ARM: davinci: serial: get rid of davinci_uart_config
"struct davinci_uart_config" was introduced to specify
UART ports brought out or enabled on the board. But
none of the boards use it for that purpose and we are
not going to add anymore board files, so remove the
structure.
Signed-off-by: Manjunathappa, Prakash <prakash.pm@ti.com> Suggested-by: Sekhar Nori <nsekhar@ti.com>
[nsekhar@ti.com: split patch to remove davinci_serial_setup_clk()
changes.] Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Kevin Hilman [Wed, 21 Aug 2013 17:16:55 +0000 (10:16 -0700)]
Merge tag 'tegra-for-3.12-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/soc
From: Stephen Warren:
ARM: tegra: core SoC enhancements for 3.12
This branch includes a number of enhancements to core SoC support for
Tegra devices. The major new features are:
* Adds a new CPU-power-gated cpuidle state for Tegra114.
* Adds initial system suspend support for Tegra114, initially supporting
just CPU-power-gating during suspend.
* Adds "LP1" suspend mode support for all of Tegra20/30/114. This mode
both gates CPU power, and places the DRAM into self-refresh mode.
* A new DT-driven PCIe driver to Tegra20/30. The driver is also moved
from arch/arm/mach-tegra/ to drivers/pci/host/.
The PCIe driver work depends on the following tag from Thomas Petazzoni:
git://git.infradead.org/linux-mvebu.git mis-3.12.2
... which is merged into the middle of this pull request.
* tag 'tegra-for-3.12-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra: (33 commits)
ARM: tegra: disable LP2 cpuidle state if PCIe is enabled
MAINTAINERS: Add myself as Tegra PCIe maintainer
PCI: tegra: set up PADS_REFCLK_CFG1
PCI: tegra: Add Tegra 30 PCIe support
PCI: tegra: Move PCIe driver to drivers/pci/host
PCI: msi: add default MSI operations for !HAVE_GENERIC_HARDIRQS platforms
ARM: tegra: add LP1 suspend support for Tegra114
ARM: tegra: add LP1 suspend support for Tegra20
ARM: tegra: add LP1 suspend support for Tegra30
ARM: tegra: add common LP1 suspend support
clk: tegra114: add LP1 suspend/resume support
ARM: tegra: config the polarity of the request of sys clock
ARM: tegra: add common resume handling code for LP1 resuming
ARM: pci: add ->add_bus() and ->remove_bus() hooks to hw_pci
of: pci: add registry of MSI chips
PCI: Introduce new MSI chip infrastructure
PCI: remove ARCH_SUPPORTS_MSI kconfig option
PCI: use weak functions for MSI arch-specific functions
ARM: tegra: unify Tegra's Kconfig a bit more
ARM: tegra: remove the limitation that Tegra114 can't support suspend
...
ARM: ux500: remove u8500_secondary_startup from INIT section.
This patch removes u8500_secondary_startup from _INIT section, there are
two reason for this removal.
1. discarding such a small code does not save much, given the RAM sizes.
2. Having this code discarded, creates corruption issue when we boot
smp-kernel with nr_cpus=1 or with single cpu node in DT.
Kevin Hilman [Mon, 19 Aug 2013 17:22:10 +0000 (10:22 -0700)]
Merge tag 'omap-for-v3.12/dra7xx' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/soc
From Tony Lindgren:
Minimal DRA7xx based SoC core support via Rajendra Nayak <rnayak@ti.com>
* tag 'omap-for-v3.12/dra7xx' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (849 commits)
ARM: DRA7: Add the build support in omap2plus
ARM: DRA7: hwmod: Reuse the soc_ops used for OMAP4/5
ARM: DRA7: id: Add cpu detection support for DRA7xx based SoCs'
ARM: DRA7: Kconfig: Make ARCH_NR_GPIO default to 512
ARM: DRA7: board-generic: Add basic DT support
ARM: DRA7: Resue the clocksource, clockevent support
ARM: DRA7: Reuse io tables and add a new .init_early
ARM: DRA7: Reuse all of PRCM and MPUSS SMP infra
Linux 3.11-rc5
btrfs: don't loop on large offsets in readdir
Btrfs: check to see if root_list is empty before adding it to dead roots
Btrfs: release both paths before logging dir/changed extents
Btrfs: allow splitting of hole em's when dropping extent cache
Btrfs: make sure the backref walker catches all refs to our extent
Btrfs: fix backref walking when we hit a compressed extent
Btrfs: do not offset physical if we're compressed
Btrfs: fix extent buffer leak after backref walking
Btrfs: fix a bug of snapshot-aware defrag to make it work on partial extents
btrfs: fix file truncation if FALLOC_FL_KEEP_SIZE is specified
dlm: kill the unnecessary and wrong device_close()->recalc_sigpending()
...
Maxime Ripard [Wed, 17 Jul 2013 07:47:18 +0000 (09:47 +0200)]
ARM: sunxi: Introduce Allwinner A20 support
The Allwinner A20 is a dual-core Cortex-A7-based SoC. It is
pin-compatible with the A10, and re-uses most of the IPs found in it,
plus some additional ones like a Gigabit Ethernet controller.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Maxime Ripard [Sun, 10 Mar 2013 14:56:30 +0000 (15:56 +0100)]
ARM: sunxi: Add the Allwinner A31 compatible to the machine definition
The Allwinner A31 is a quad-Cortex-A7 based SoC, which shares a lot of
IPs with the previous SoCs from Allwinner, like the PIO, I2C, UARTs,
timers, watchdog IPs, but also differs by dropping the WEMAC ethernet
controller and most notably dropping the in-house IRQ controller in
favor of a ARM GIC one.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* tag 'drivers-3.12' of git://git.infradead.org/linux-mvebu: (35 commits)
memory: mvebu-devbus: Remove unused variable
ARM: mvebu: Relocate PCIe node in Armada 370 RD board
ARM: mvebu: Fix AXP-WiFi-AP DT for MBUS DT binding
ARM: mvebu: add support for the AXP WiFi AP board
ARM: mvebu: use dts pre-processor for mv78230
PCI: mvebu: Adapt to the new device tree layout
bus: mvebu-mbus: Add devicetree binding
ARM: kirkwood: Relocate PCIe device tree nodes
ARM: kirkwood: Introduce MBUS_ID
ARM: kirkwood: Introduce MBus DT node
ARM: kirkwood: Use the preprocessor on device tree files
ARM: kirkwood: Split DT and legacy MBus initialization
ARM: mvebu: Relocate Armada 370/XP PCIe device tree nodes
ARM: mvebu: Relocate Armada 370/XP DeviceBus device tree nodes
ARM: mvebu: Add BootROM to Armada 370/XP device tree
ARM: mvebu: Add MBus to Armada 370/XP device tree
ARM: mvebu: Use the preprocessor on Armada 370/XP device tree files
ARM: mvebu: Initialize MBus using the DT binding
ARM: mvebu: Remove the harcoded BootROM window allocation
bus: mvebu-mbus: Factorize Armada 370/XP data structures
...
Peter Chen [Tue, 16 Jul 2013 02:23:20 +0000 (10:23 +0800)]
ARM: imx: clk-pllv3: improve the timeout waiting method
There are two improvements for this commit:
- Add comparing pll lock condition after while loop. It can
fix potential fake timeout problem caused by the code is just
scheduled out before compare the timeout, and the time of
scheduling out are more than one jiffies.
- Move timeout assignment more close to compare the timeout.
It can reduce the possibility the code is scheduled out, and
the timeout can be more precise.
Liu Ying [Thu, 4 Jul 2013 09:57:17 +0000 (17:57 +0800)]
ARM: imx6: change some clocks to fixup clocks
All the clocks controlled by the register 'CCM Serial Clock
Multiplexer Register 1' should be fixup clocks. This patch
changes those clocks from basic multiplexer or divider clocks
to fixup clocks.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Liu Ying [Thu, 4 Jul 2013 09:35:46 +0000 (17:35 +0800)]
ARM: imx: add common clock support for fixup mux
One register may have several fields to control some clocks. It
is possible that the read/write values of some fields may map to
different real functional values, so writing to the other fields
in the same register may break a working clock tree. A real case
is the aclk_podf field in the register 'CCM Serial Clock Multiplexer
Register 1' of i.MX6Q/SDL SoC. This patch introduces a fixup hook
for multiplexer clock which is called before writing a value to
clock registers to support this kind of multiplexer clocks.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Liu Ying [Thu, 4 Jul 2013 09:22:26 +0000 (17:22 +0800)]
ARM: imx: add common clock support for fixup div
One register may have several fields to control some clocks. It
is possible that the read/write values of some fields may map to
different real functional values, so writing to the other fields
in the same register may break a working clock tree. A real case
is the aclk_podf field in the register 'CCM Serial Clock Multiplexer
Register 1' of i.MX6Q/SDL SoC. This patch introduces a fixup hook
for divider clock which is called before writing a value to clock
registers to support this kind of divider clocks.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Vincent Stehlé [Wed, 10 Jul 2013 09:45:46 +0000 (11:45 +0200)]
ARM: imx: fix imx_init_l2cache storage class
This fixes the following compilation error:
arch/arm/mach-imx/system.c:101:123: error: static declaration of ‘imx_init_l2cache’ follows non-static declaration
In file included from arch/arm/mach-imx/system.c:32:0:
arch/arm/mach-imx/common.h:165:13: note: previous declaration of ‘imx_init_l2cache’ was here
arch/arm/mach-imx/system.c:101:123: warning: ‘imx_init_l2cache’ defined but not used [-Wunused-function]
Signed-off-by: Vincent Stehlé <vincent.stehle@freescale.com> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Russell King <linux@arm.linux.org.uk> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
ARM: imx: let L2 initialization be a common function
Move imx6q L2 initialization function imx6q_init_l2cache() into
system.c, and rename it imx_init_l2cache(), so that other platforms
other than imx6q can also use the function.
Sascha Hauer [Thu, 20 Jun 2013 15:34:31 +0000 (17:34 +0200)]
ARM: i.MX6: call ksz9021 phy fixup for all i.MX6 boards
In current U-Boot the sabrelite, nitrogen6x and titanium all need
the same fixup for the ksz9021 phy. Instead of limiting the fixup
to a single board apply them for all.
Nicolas Pitre [Wed, 14 Aug 2013 14:25:14 +0000 (10:25 -0400)]
ARM: vexpress/MCPM: fix cache disable sequence when CONFIG_FRAME_POINTER=y
If CONFIG_FRAME_POINTER=y we get the following error:
arch/arm/mach-vexpress/tc2_pm.c: In function 'tc2_pm_down':
arch/arm/mach-vexpress/tc2_pm.c:200:1: error: fp cannot be used in asm here
Let's fix that by explicitly preserving r11 on the stack and removing it
from the clobber list.
Reported-by: Russell King <rmk+kernel@arm.linux.org.uk> Reviewed-by: Dave Martin <Dave.Martin@arm.com> Signed-off-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Olof Johansson <olof@lixom.net>
Olof Johansson [Wed, 14 Aug 2013 08:09:40 +0000 (01:09 -0700)]
Merge tag 'renesas-soc2-for-v3.12' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc
From Simon Horman:
Second Round of Renesas ARM based SoC updates for v3.12
* Increased clock coverage for r8a7740 and r8a7790 SoCs
* tag 'renesas-soc2-for-v3.12' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: r8a7740: Add TPU clock entry for DT platforms
ARM: shmobile: r8a7790: clocks for Ether support
ARM: shmobile: r8a7740: Fix TPU clock name
ARM: shmobile: Insert align directives before 4 bytes data
ARM: shmobile: Force ARM mode to compile reset vector for secondary CPUs
ARM: shmobile: fix compile error when CONFIG_THUMB2_KERNEL=y
ARM: shmobile: Update romImage to relocate appended DTB
Olof Johansson [Wed, 14 Aug 2013 07:25:13 +0000 (00:25 -0700)]
Merge tag 'renesas-soc-for-v3.12' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc
From Simon Horman:
Renesas ARM based SoC updates for v3.12
* Setup arch timer based on MD pins on r8a7790 SoC
* Thermal driver support for r8a7790 SoC
* Make arch timer optional for r8a7790 and r8a73a4 SoCs
* CMT10 clock event for r8a7790 and r8a73a4 SoCs
* Increased clock coverage for r8a73a4 SoC
* MMCIF DMA definitions for r8a7740 SoC
* Disconnect SMP code from clocks on emev2 SoC
* tag 'renesas-soc-for-v3.12' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (49 commits)
ARM: shmobile: Setup r8a7790 arch timer based on MD pins
ARM: shmobile: Introduce r8a7790_read_mode_pins()
ARM: shmobile: r8a7740: add MMCIF DMA definitions
ARM: shmobile: Disconnect EMEV2 SMP code from clocks
ARM: shmobile: Make r8a73a4 Arch timer optional
ARM: shmobile: Add r8a73a4 CMT10 clock event
ARM: shmobile: Make r8a7790 Arch timer optional
ARM: shmobile: Add r8a7790 CMT00 clock event
ARM: shmobile: Sort r8a7790 MSTP entries
ARM: shmobile: r8a73a4: add clocks for I2C controllers
ARM: shmobile: r8a73a4: add Z2 clock support
ARM: shmobile: r8a73a4: safeguard against wrong clk_set_rate() uses
ARM: shmobile: r8a73a4: implement CPU clock scaling for CPUFreq
ARM: shmobile: r8a73a4: wait for completion when kicking the clock
ARM: shmobile: r8a7790: add thermal driver support
ARM: shmobile: r8a7790: add clocks for thermal
ARM: shmobile: Add SMSC ethernet chip to KZM9D DT reference
ARM: shmobile: KZM9D DT reference implementation
ARM: shmobile: r8a7790: add MMCIF and SDHI DT templates
ARM: shmobile: r8a73a4: add MMCIF and SDHI DT templates
...
Olof Johansson [Wed, 14 Aug 2013 05:07:52 +0000 (22:07 -0700)]
Merge tag 'tc2-pm' of git://git.linaro.org/people/pawelmoll/linux into next/soc
From Pawel Moll and Nicolas Pitre:
- Fixes to the existing Vexpress DCSCB backend.
- Lorenzo's minimal SPC driver required by the TC2 MCPM backend.
- The MCPM backend enabling SMP secondary boot and CPU hotplug
on the VExpress TC2 big.LITTLE platform.
- MCPM suspend method to the TC2 backend allowing basic CPU
idle/suspend. The cpuidle driver that hooks into this will be
submitted separately.
* tag 'tc2-pm' of git://git.linaro.org/people/pawelmoll/linux:
ARM: vexpress/TC2: implement PM suspend method
ARM: vexpress/TC2: basic PM support
ARM: vexpress: Add SCC to V2P-CA15_A7's device tree
ARM: vexpress/TC2: add Serial Power Controller (SPC) support
ARM: vexpress/dcscb: fix cache disabling sequences
Stephen Warren [Mon, 6 May 2013 20:19:19 +0000 (14:19 -0600)]
ARM: tegra: disable LP2 cpuidle state if PCIe is enabled
Tegra20 HW appears to have a bug such that PCIe device interrupts,
whether they are legacy IRQs or MSI, are lost when LP2 is enabled. To
work around this, simply disable LP2 if any PCIe devices with interrupts
are present. Detect this via the IRQ domain map operation. This is
slightly over-conservative; if a device with an interrupt is present but
the driver does not actually use them, LP2 will still be disabled.
However, this is a reasonable trade-off which enables a simpler
workaround.
Stephen Warren [Fri, 9 Aug 2013 14:49:25 +0000 (16:49 +0200)]
PCI: tegra: set up PADS_REFCLK_CFG1
The registers PADS_REFCLK_CFG are an array of 16-bit data, one entry per
PCIe root port. For Tegra30, we therefore need to write a 3rd entry in
this array. Doing so makes the mini-PCIe slot on Beaver operate correctly.
While we're at it, add some #defines to partially document the fields
within these 16-bit values.
Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
Jay Agarwal [Fri, 9 Aug 2013 14:49:24 +0000 (16:49 +0200)]
PCI: tegra: Add Tegra 30 PCIe support
Introduce a data structure to parameterize the driver according to SoC
generation, add Tegra30 specific code and update the device tree binding
document for Tegra30 support.
Signed-off-by: Jay Agarwal <jagarwal@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
Thierry Reding [Fri, 9 Aug 2013 14:49:19 +0000 (16:49 +0200)]
PCI: tegra: Move PCIe driver to drivers/pci/host
Move the PCIe driver from arch/arm/mach-tegra into the drivers/pci/host
directory. The motivation is to collect various host controller drivers
in the same location in order to facilitate refactoring.
The Tegra PCIe driver has been largely rewritten, both in order to turn
it into a proper platform driver and to add MSI (based on code by
Krishna Kishore <kthota@nvidia.com>) as well as device tree support.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com>
[swarren, split DT changes into a separate patch in another branch] Signed-off-by: Stephen Warren <swarren@nvidia.com>
Thomas Petazzoni [Tue, 13 Aug 2013 08:11:42 +0000 (10:11 +0200)]
PCI: msi: add default MSI operations for !HAVE_GENERIC_HARDIRQS platforms
Some platforms (e.g S390) don't use the generic hardirqs code and
therefore do not defined HAVE_GENERIC_HARDIRQS. This prevents using
the irq_set_chip_data() and irq_get_chip_data() functions that are
used for the default implementations of the MSI operations.
So, when CONFIG_GENERIC_HARDIRQS is not enabled, provide another
default implementation of the MSI operations, that simply errors
out. The architecture is responsible for implementing those operations
(which is the case on S390), and cannot use the msi_chip infrastructure.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
R Sricharan [Wed, 6 Feb 2013 14:55:40 +0000 (20:25 +0530)]
ARM: DRA7: id: Add cpu detection support for DRA7xx based SoCs'
The DRA7xx is a high-performance, infotainment application device,
based on enhanced OMAP architecture integrated on a 28-nm technology.
Since DRA7 is a platform supported only using DT, the cpu detection
is based on the compatibles passed from DT blobs as suggested here
http://lists.infradead.org/pipermail/linux-arm-kernel/2013-July/187712.html
Suggested-by: Felipe Balbi <balbi@ti.com> Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Rajendra Nayak <rnayak@ti.com>
R Sricharan [Thu, 7 Feb 2013 12:13:35 +0000 (17:43 +0530)]
ARM: DRA7: Kconfig: Make ARCH_NR_GPIO default to 512
DRA7xx has 8 GPIO banks so that there are 32x8 = 256 GPIOs.
In order for the gpiolib to detect and initialize these
and other TWL GPIOs, ARCH_NR_GPIO is set to 512 using the
kconfig default for DRA7.
Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Rajendra Nayak <rnayak@ti.com>
R Sricharan [Thu, 7 Feb 2013 08:23:05 +0000 (13:53 +0530)]
ARM: DRA7: board-generic: Add basic DT support
Describe minimal DT boot machine details for DRA7xx based SoC's. DRA7xx
family is based on dual core ARM CORTEX A15 using GIC as the interrupt controller.
The PRCM and timer infrastructure is reused from OMAP5 and so are the io
descriptor tables.
Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Rajendra Nayak <rnayak@ti.com>
R Sricharan [Wed, 3 Jul 2013 06:08:50 +0000 (11:38 +0530)]
ARM: DRA7: Reuse all of PRCM and MPUSS SMP infra
The PRCM and MPUSS parts of DRA7 devices are quite identical
to OMAP5 so as to reuse all the existing infrastructure around it.
Makefile updates to do just that.
Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Joseph Lo [Mon, 12 Aug 2013 09:40:06 +0000 (17:40 +0800)]
ARM: tegra: add LP1 suspend support for Tegra114
The LP1 suspend mode will power off the CPU, clock gated the PLLs and put
SDRAM to self-refresh mode. Any interrupt can wake up device from LP1. The
sequence when LP1 suspending:
* tunning off L1 data cache and the MMU
* storing some EMC registers, DPD (deep power down) status, clk source of
mselect and SCLK burst policy
* putting SDRAM into self-refresh
* switching CPU to CLK_M (12MHz OSC)
* tunning off PLLM, PLLP, PLLA, PLLC and PLLX
* switching SCLK to CLK_S (32KHz OSC)
* shutting off the CPU rail
The sequence of LP1 resuming:
* re-enabling PLLM, PLLP, PLLA, PLLC and PLLX
* restoring the clk source of mselect and SCLK burst policy
* setting up CCLK burst policy to PLLX
* restoring DPD status and some EMC registers
* resuming SDRAM to normal mode
* jumping to the "tegra_resume" from PMC_SCRATCH41
Due to the SDRAM will be put into self-refresh mode, the low level
procedures of LP1 suspending and resuming should be copied to
TEGRA_IRAM_CODE_AREA (TEGRA_IRAM_BASE + SZ_4K) when suspending. Before
restoring the CPU context when resuming, the SDRAM needs to be switched
back to normal mode. And the PLLs need to be re-enabled, SCLK burst policy
be restored. Then jumping to "tegra_resume" that was expected to be stored
in PMC_SCRATCH41 to restore CPU context and back to kernel.
Based on the work by: Bo Yan <byan@nvidia.com>
Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
Joseph Lo [Mon, 12 Aug 2013 09:40:05 +0000 (17:40 +0800)]
ARM: tegra: add LP1 suspend support for Tegra20
The LP1 suspend mode will power off the CPU, clock gated the PLLs and put
SDRAM to self-refresh mode. Any interrupt can wake up device from LP1. The
sequence when LP1 suspending:
* tunning off L1 data cache and the MMU
* putting SDRAM into self-refresh
* storing some EMC registers and SCLK burst policy
* switching CPU to CLK_M (12MHz OSC)
* switching SCLK to CLK_S (32KHz OSC)
* tunning off PLLM, PLLP and PLLC
* shutting off the CPU rail
The sequence of LP1 resuming:
* re-enabling PLLM, PLLP, and PLLC
* restoring some EMC registers and SCLK burst policy
* setting up CCLK burst policy to PLLP
* resuming SDRAM to normal mode
* jumping to the "tegra_resume" from PMC_SCRATCH41
Due to the SDRAM will be put into self-refresh mode, the low level
procedures of LP1 suspending and resuming should be copied to
TEGRA_IRAM_CODE_AREA (TEGRA_IRAM_BASE + SZ_4K) when suspending. Before
restoring the CPU context when resuming, the SDRAM needs to be switched
back to normal mode. And the PLLs need to be re-enabled, SCLK burst policy
be restored, CCLK burst policy be set in PLLP. Then jumping to
"tegra_resume" that was expected to be stored in PMC_SCRATCH41 to restore
CPU context and back to kernel.
Based on the work by:
Colin Cross <ccross@android.com>
Gary King <gking@nvidia.com>
Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
Joseph Lo [Mon, 12 Aug 2013 09:40:04 +0000 (17:40 +0800)]
ARM: tegra: add LP1 suspend support for Tegra30
The LP1 suspend mode will power off the CPU, clock gated the PLLs and put
SDRAM to self-refresh mode. Any interrupt can wake up device from LP1. The
sequence when LP1 suspending:
* tunning off L1 data cache and the MMU
* storing some EMC registers, DPD (deep power down) status, clk source of
mselect and SCLK burst policy
* putting SDRAM into self-refresh
* switching CPU to CLK_M (12MHz OSC)
* tunning off PLLM, PLLP, PLLA, PLLC and PLLX
* switching SCLK to CLK_S (32KHz OSC)
* shutting off the CPU rail
The sequence of LP1 resuming:
* re-enabling PLLM, PLLP, PLLA, PLLC and PLLX
* restoring the clk source of mselect and SCLK burst policy
* setting up CCLK burst policy to PLLX
* restoring DPD status and some EMC registers
* resuming SDRAM to normal mode
* jumping to the "tegra_resume" from PMC_SCRATCH41
Due to the SDRAM will be put into self-refresh mode, the low level
procedures of LP1 suspending and resuming should be copied to
TEGRA_IRAM_CODE_AREA (TEGRA_IRAM_BASE + SZ_4K) when suspending. Before
restoring the CPU context when resuming, the SDRAM needs to be switched
back to normal mode. And the PLLs need to be re-enabled, SCLK burst policy
be restored, CCLK burst policy be set in PLLX. Then jumping to
"tegra_resume" that was expected to be stored in PMC_SCRATCH41 to restore
CPU context and back to kernel.
Based on the work by: Scott Williams <scwilliams@nvidia.com>
Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
Joseph Lo [Mon, 12 Aug 2013 09:40:03 +0000 (17:40 +0800)]
ARM: tegra: add common LP1 suspend support
The LP1 suspending mode on Tegra means CPU rail off, devices and PLLs are
clock gated and SDRAM in self-refresh mode. That means the low level LP1
suspending and resuming code couldn't be run on DRAM and the CPU must
switch to the always on clock domain (a.k.a. CLK_M 12MHz oscillator). And
the system clock (SCLK) would be switched to CLK_S, a 32KHz oscillator.
The LP1 low level handling code need to be moved to IRAM area first. And
marking the LP1 mask for indicating the Tegra device is in LP1. The CPU
power timer needs to be re-calculated based on 32KHz that was originally
based on PCLK.
When resuming from LP1, the LP1 reset handler will resume PLLs and then
put DRAM to normal mode. Then jumping to the "tegra_resume" that will
restore full context before back to kernel. The "tegra_resume" handler
was expected to be found in PMC_SCRATCH41 register.
This is common LP1 procedures for Tegra, so we do these jobs mainly in
this patch:
* moving LP1 low level handling code to IRAM
* marking LP1 mask
* copying the physical address of "tegra_resume" to PMC_SCRATCH41
* re-calculate the CPU power timer based on 32KHz
Signed-off-by: Joseph Lo <josephl@nvidia.com>
[swarren, replaced IRAM_CODE macro with IO_ADDRESS(TEGRA_IRAM_CODE_AREA)] Signed-off-by: Stephen Warren <swarren@nvidia.com>
Joseph Lo [Mon, 12 Aug 2013 09:40:02 +0000 (17:40 +0800)]
clk: tegra114: add LP1 suspend/resume support
When the system suspends to LP1, the CPU clock source is switched to
CLK_M (12MHz Oscillator) during suspend/resume flow. The CPU clock
source is controlled by the CCLKG_BURST_POLICY register, and hence this
register must be restored during LP1 resume.
Cc: Mike Turquette <mturquette@linaro.org> Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
Joseph Lo [Mon, 12 Aug 2013 09:40:01 +0000 (17:40 +0800)]
ARM: tegra: config the polarity of the request of sys clock
When suspending to LP1 mode, the SYSCLK will be clock gated. And different
board may have different polarity of the request of SYSCLK, this patch
configure the polarity from the DT for the board.
Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
Joseph Lo [Mon, 12 Aug 2013 09:40:00 +0000 (17:40 +0800)]
ARM: tegra: add common resume handling code for LP1 resuming
Add support to the Tegra CPU reset vector to detect whether the CPU is
resuming from LP1 suspend state. If it is, branch to the LP1-specific
resume code.
When Tegra enters the LP1 suspend state, the SDRAM controller is placed
into a self-refresh state. For this reason, we must place the LP1 resume
code into IRAM, so that it is accessible before SDRAM access has been
re-enabled.
Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
ARM: pci: add ->add_bus() and ->remove_bus() hooks to hw_pci
Some PCI drivers may need to adjust the pci_bus structure after it has
been allocated by the Linux PCI core. The PCI core allows
architectures to implement the pcibios_add_bus() and
pcibios_remove_bus() for this purpose. This commit therefore extends
the hw_pci and pci_sys_data structures of the ARM PCI core to allow
PCI drivers to register ->add_bus() and ->remove_bus() in hw_pci,
which will get called when a bus is added or removed from the system.
This will be used for example by the Marvell PCIe driver to connect a
particular PCI bus with its corresponding MSI chip to handle Message
Signaled Interrupts.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Reviewed-by: Thierry Reding <thierry.reding@gmail.com> Acked-by: Russell King <rmk+kernel@arm.linux.org.uk> Tested-by: Daniel Price <daniel.price@gmail.com> Tested-by: Thierry Reding <thierry.reding@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This commit adds a very basic registry of msi_chip structures, so that
an IRQ controller driver can register an msi_chip, and a PCIe host
controller can find it, based on a 'struct device_node'.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Thierry Reding [Fri, 9 Aug 2013 20:27:08 +0000 (22:27 +0200)]
PCI: Introduce new MSI chip infrastructure
The new struct msi_chip is used to associated an MSI controller with a
PCI bus. It is automatically handed down from the root to its children
during bus enumeration.
This patch provides default (weak) implementations for the architecture-
specific MSI functions (arch_setup_msi_irq(), arch_teardown_msi_irq()
and arch_msi_check_device()) which check if a PCI device's bus has an
attached MSI chip and forward the call appropriately.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Tested-by: Daniel Price <daniel.price@gmail.com> Tested-by: Thierry Reding <thierry.reding@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Now that we have weak versions for each of the PCI MSI architecture
functions, we can actually build the MSI support for all platforms,
regardless of whether they provide or not architecture-specific
versions of those functions. For this reason, the ARCH_SUPPORTS_MSI
hidden kconfig boolean becomes useless, and this patch gets rid of it.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Tested-by: Daniel Price <daniel.price@gmail.com> Tested-by: Thierry Reding <thierry.reding@gmail.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Paul Mackerras <paulus@samba.org> Cc: linuxppc-dev@lists.ozlabs.org Cc: Martin Schwidefsky <schwidefsky@de.ibm.com> Cc: Heiko Carstens <heiko.carstens@de.ibm.com> Cc: linux390@de.ibm.com Cc: linux-s390@vger.kernel.org Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Ingo Molnar <mingo@redhat.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: x86@kernel.org Cc: Russell King <linux@arm.linux.org.uk> Cc: Tony Luck <tony.luck@intel.com> Cc: Fenghua Yu <fenghua.yu@intel.com> Cc: linux-ia64@vger.kernel.org Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Cc: David S. Miller <davem@davemloft.net> Cc: sparclinux@vger.kernel.org Cc: Chris Metcalf <cmetcalf@tilera.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
PCI: use weak functions for MSI arch-specific functions
Until now, the MSI architecture-specific functions could be overloaded
using a fairly complex set of #define and compile-time
conditionals. In order to prepare for the introduction of the msi_chip
infrastructure, it is desirable to switch all those functions to use
the 'weak' mechanism. This commit converts all the architectures that
were overidding those MSI functions to use the new strategy.
Note that we keep two separate, non-weak, functions
default_teardown_msi_irqs() and default_restore_msi_irqs() for the
default behavior of the arch_teardown_msi_irqs() and
arch_restore_msi_irqs(), as the default behavior is needed by x86 PCI
code.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Tested-by: Daniel Price <daniel.price@gmail.com> Tested-by: Thierry Reding <thierry.reding@gmail.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Paul Mackerras <paulus@samba.org> Cc: linuxppc-dev@lists.ozlabs.org Cc: Martin Schwidefsky <schwidefsky@de.ibm.com> Cc: Heiko Carstens <heiko.carstens@de.ibm.com> Cc: linux390@de.ibm.com Cc: linux-s390@vger.kernel.org Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Ingo Molnar <mingo@redhat.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: x86@kernel.org Cc: Russell King <linux@arm.linux.org.uk> Cc: Tony Luck <tony.luck@intel.com> Cc: Fenghua Yu <fenghua.yu@intel.com> Cc: linux-ia64@vger.kernel.org Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Cc: David S. Miller <davem@davemloft.net> Cc: sparclinux@vger.kernel.org Cc: Chris Metcalf <cmetcalf@tilera.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
projects / karo-tx-linux.git / log