Stephen Boyd [Mon, 2 May 2016 23:53:02 +0000 (16:53 -0700)]
Merge tag 'tegra-for-4.7-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-next
Pull tegra clk driver changes from Thierry Reding:
This set of changes contains a bunch of cleanups and minor fixes along
with some new clocks, mainly on Tegra210, in preparation for supporting
DisplayPort and HDMI 2.0.
* tag 'tegra-for-4.7-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
clk: tegra: dfll: Reformat CVB frequency table
clk: tegra: dfll: Properly clean up on failure and removal
clk: tegra: dfll: Make code more comprehensible
clk: tegra: dfll: Reference CVB table instead of copying data
clk: tegra: dfll: Update kerneldoc
clk: tegra: Fix PLL_U post divider and initial rate on Tegra30
clk: tegra: Initialize PLL_C to sane rate on Tegra30
clk: tegra: Fix pllre Tegra210 and add pll_re_out1
clk: tegra: Add sor_safe clock
clk: tegra: dpaux and dpaux1 are fixed factor clocks
clk: tegra: Add dpaux1 clock
clk: tegra: Use correct parent for dpaux clock
clk: tegra: Add fixed factor peripheral clock type
clk: tegra: Special-case mipi-cal parent on Tegra114
clk: tegra: Remove trailing blank line
clk: tegra: Constify peripheral clock registers
clk: tegra: Add interface to enable hardware control of SATA/XUSB PLLs
Stephen Boyd [Mon, 2 May 2016 23:43:03 +0000 (16:43 -0700)]
Merge tag 'v4.7-rockchip-clk3' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next
Pull rockchip clk updates from Heiko Stuebner:
A spelling fix and a bunch of rk3399 clock fixes.
* tag 'v4.7-rockchip-clk3' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
clk: rockchip: fix the rk3399 cifout clock
clk: rockchip: drop unnecessary CLK_IGNORE_UNUSED flags from rk3399
clk: rockchip: add some frequencies on the rk3399 PLL table
clk: rockchip: assign more necessary rk3399 clock ids
clk: rockchip: export some necessary rk3399 clock ids
clk: rockchip: rename rga clock-id on rk3399
clk: rockchip: add general gpu soft-reset on rk3399
clk: rockchip: fix the gate bit for i2c4 and i2c8 on rk3399
clk: rockchip: fix of spelling mistake on unsuccessful in pll clock type
clk: tegra: dfll: Properly clean up on failure and removal
Upon failure to probe the DFLL, the OPP table will not be cleaned up
properly. Fix this and while at it make sure the OPP table will also be
cleared upon driver removal.
Rename some variables and structure fields to make the code more
comprehensible. Also change the prototype of internal functions to be
more in line with the OPP core functions.
Lucas Stach [Mon, 29 Feb 2016 20:46:07 +0000 (21:46 +0100)]
clk: tegra: Fix PLL_U post divider and initial rate on Tegra30
The post divider value in the frequency table is wrong as it would lead
to the PLL producing an output rate of 960 MHz instead of the desired
480 MHz. This wasn't a problem as nothing used the table to actually
initialize the PLL rate, but the bootloader configuration was used
unaltered.
If the bootloader does not set up the PLL it will fail to come when used
under Linux. To fix this don't rely on the bootloader, but set the
correct rate in the clock driver.
Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Thierry Reding <treding@nvidia.com>
Lucas Stach [Mon, 29 Feb 2016 20:46:06 +0000 (21:46 +0100)]
clk: tegra: Initialize PLL_C to sane rate on Tegra30
If the bootloader does not touch PLL_C it will stay in its reset state,
failing to lock when enabled. This leads to consumers of this clock to
fail probing. Fix this by always programming the PLL with a sane rate,
which allows it to lock, at startup.
Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Thierry Reding <treding@nvidia.com>
The sor_safe clock is a fixed factor (1:17) clock derived from pll_p. It
has a gate bit in the peripheral clock registers. While the SOR is being
powered up, sor_safe can be used as the source until the SOR brick can
generate its own clock.
clk: tegra: dpaux and dpaux1 are fixed factor clocks
The dpaux (on Tegra124 and Tegra210) and dpaux1 (on Tegra210) are fixed
factor clocks (1:17) and derived from pll_p_out0 (pll_p). They also have
a gate bit in the peripheral clock registers.
clk: tegra: Add fixed factor peripheral clock type
Some of the peripheral clocks on Tegra are derived from one of the top-
level PLLs with a fixed factor. Support these clocks by implementing the
->enable() and ->disable() callbacks using the peripheral clock register
banks and the ->recalc_rate() by dividing the parent rate by the fixed
factor.
The peripheral clock registers are defined in static tables. These
tables never need to be modified at runtime, so they can reside in
read-only memory.
clk: tegra: Add interface to enable hardware control of SATA/XUSB PLLs
On Tegra210, hardware control of the SATA and XUSB pad PLLs must be
done during the UPHY enable sequence rather than the PLLE enable
sequence. Export functions to do this so that hardware control can
be enabled from the XUSB padctl driver.
Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
The rga clock supplying the working clock on the rk3399 is actually
called rga-core in the manual. As the clock id has neither been
assigned nor released with a full kernel release, we can still change
the id to the more appropriate naming.
Maxime Ripard [Wed, 23 Mar 2016 16:38:24 +0000 (17:38 +0100)]
clk: composite: Add unregister function
The composite clock didn't have any unregistration function, which forced
us to use clk_unregister directly on it.
While it was already not great from an API point of view, it also meant
that we were leaking the clk_composite structure allocated in
clk_register_composite.
Add a clk_unregister_composite function to fix this.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Neil Armstrong [Mon, 18 Apr 2016 10:01:35 +0000 (12:01 +0200)]
clk: Add Oxford Semiconductor OXNAS Standard Clocks
Add Oxford Semiconductor OXNAS SoC Family Standard Clocks support.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
[sboyd@codeaurora.org: Drop NULL/continue check in registration
loop] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Stephen Boyd [Wed, 20 Apr 2016 18:44:03 +0000 (11:44 -0700)]
Merge tag 'clk-renesas-for-v4.7-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next
clk: renesas: R-Car SYSC PM Domain Preparation
- Export the CPG/MSSR and CPG/MSTP attach/detach_dev callbacks, so
they can be called by the R-Car SYSC PM Domain driver.
* tag 'clk-renesas-for-v4.7-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
clk: renesas: cpg-mssr: Export cpg_mssr_{at,de}tach_dev()
clk: renesas: mstp: Provide dummy attach/detach_dev callbacks
clk: renesas: Provide Kconfig symbols for CPG/MSSR and CPG/MSTP support
Stephen Boyd [Wed, 20 Apr 2016 18:41:37 +0000 (11:41 -0700)]
Merge tag 'v4.7-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next
Pull some checkpatch silencers from Heiko Stuebner:
Fix quite some checkpatch warnings in the newly added
rk3399 header and also in the clock code itself.
* tag 'v4.7-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
clk: rockchip: fix checkpatch warning in core code
clk: rockchip: drop unnecessary header comment
clk: rockchip: reign in some overly long lines in the rk3399 controller
clk: rockchip: fix checkpatch errors in rk3399 dt-binding header
clk: rockchip: fix checkpatch warning in core code
We seem to have accumulated a bunch of checkpatch warnings, with mainly
overlong lines and two unnecessary allocation error messages.
Most were introduced with the recent multi-controller-support but some
were quite a bit older.
The R-Car SYSC PM Domain driver has to power manage devices in power
areas using clocks. To reuse code and to share knowledge of clocks
suitable for power management, this is ideally done through the existing
cpg_mssr_attach_dev() and cpg_mssr_detach_dev() callbacks.
Hence these callbacks can no longer rely on their "domain" parameter
pointing to the CPG/MSSR Clock Domain. To handle this, keep a pointer to
the clock domain in a static variable. cpg_mssr_attach_dev() has to
support probe deferral, as the R-Car SYSC PM Domain may be initialized,
and devices may be added to it, before the CPG/MSSR Clock Domain is
initialized.
Dummy callbacks are provided for the case where CPG/MSTP support is not
included, so the rcar-sysc driver won't have to care about this.
clk: renesas: mstp: Provide dummy attach/detach_dev callbacks
Provide dummy cpg_mstp_{at,de}tach_dev() PM Domain callbacks if CPG/MSTP
support is not included, so the rcar-sysc driver won't have to care
about this.
clk: renesas: Provide Kconfig symbols for CPG/MSSR and CPG/MSTP support
Currently the decision whether to build the renesas-cpg-mssr and
clk-mstp drivers is handled by Makefile logic. However, the rcar-sysc
driver will need to know whether CPG/MSSR and/or CPG/MSTP support are
available or not.
To avoid having to duplicate this logic, move it to Kconfig. Provide
non-visible CLK_RENESAS_CPG_MSSR and CLK_RENESAS_CPG_MSTP Kconfig
symbols, which can be used by both Makefiles and C code.
Eric Anholt [Wed, 13 Apr 2016 20:05:03 +0000 (13:05 -0700)]
clk: bcm2835: Fix PLL poweron
In poweroff, we set the reset bit and the power down bit, but only
managed to unset the reset bit for poweron. This meant that if HDMI
did -EPROBE_DEFER after it had grabbed its clocks, we'd power down the
PLLH (that had been on at boot time) and never recover.
Signed-off-by: Eric Anholt <eric@anholt.net> Fixes: 41691b8862e2 ("clk: bcm2835: Add support for programming the audio domain clocks") Cc: stable@vger.kernel.org Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Julia Lawall [Mon, 18 Apr 2016 14:55:34 +0000 (16:55 +0200)]
clk: qoriq: add __init attribute
Add __init attribute on a function that is only called from other __init
functions and that is not inlined, at least with gcc version 4.8.4 on an
x86 machine with allyesconfig. Currently, the function is put in the
.text.unlikely segment. Declaring it as __init will cause it to be put in
the .init.text and to disappear after initialization.
The result of objdump -x on the function before the change is as follows:
Done with the help of Coccinelle. The semantic patch checks for local
static non-init functions that are called from an __init function and are
not called from any other function.
Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
of_find_node_by_name() will call of_node_put() on the node so we need to
get it first to avoid warnings.
The cfg_node needs to be put after we have finished processing the
properties.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Tested-by: Nishanth Menon <nm@ti.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Stephen Boyd [Sun, 7 Feb 2016 08:34:13 +0000 (00:34 -0800)]
clk: fixed-rate: Add hw based registration APIs
Add registration APIs in the clk fixed-rate code to return struct
clk_hw pointers instead of struct clk pointers. This way we hide
the struct clk pointer from providers unless they need to use
consumer facing APIs.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Stephen Boyd [Sun, 7 Feb 2016 08:27:55 +0000 (00:27 -0800)]
clk: gpio: Add hw based registration APIs
Add registration APIs in the clk gpio code to return struct
clk_hw pointers instead of struct clk pointers. This way we hide
the struct clk pointer from providers unless they need to use
consumer facing APIs.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Stephen Boyd [Sun, 7 Feb 2016 08:20:31 +0000 (00:20 -0800)]
clk: composite: Add hw based registration APIs
Add registration APIs in the clk composite code to return struct
clk_hw pointers instead of struct clk pointers. This way we hide
the struct clk pointer from providers unless they need to use
consumer facing APIs.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Stephen Boyd [Sun, 7 Feb 2016 08:15:09 +0000 (00:15 -0800)]
clk: fractional-divider: Add hw based registration APIs
Add registration APIs in the clk fractional divider code to
return struct clk_hw pointers instead of struct clk pointers.
This way we hide the struct clk pointer from providers unless
they need to use consumer facing APIs.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Stephen Boyd [Sun, 7 Feb 2016 08:11:06 +0000 (00:11 -0800)]
clk: fixed-factor: Add hw based registration APIs
Add registration APIs in the clk fixed-factor code to return
struct clk_hw pointers instead of struct clk pointers. This way
we hide the struct clk pointer from providers unless they need to
use consumer facing APIs.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Stephen Boyd [Sun, 7 Feb 2016 08:05:48 +0000 (00:05 -0800)]
clk: mux: Add hw based registration APIs
Add registration APIs in the clk mux code to return struct clk_hw
pointers instead of struct clk pointers. This way we hide the
struct clk pointer from providers unless they need to use
consumer facing APIs.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Stephen Boyd [Sun, 7 Feb 2016 07:54:45 +0000 (23:54 -0800)]
clk: gate: Add hw based registration APIs
Add registration APIs in the clk gate code to return struct
clk_hw pointers instead of struct clk pointers. This way we hide
the struct clk pointer from providers unless they need to use
consumer facing APIs.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Stephen Boyd [Sun, 7 Feb 2016 07:26:37 +0000 (23:26 -0800)]
clk: divider: Add hw based registration APIs
Add registration APIs in the clk divider code to return struct
clk_hw pointers instead of struct clk pointers. This way we hide
the struct clk pointer from providers unless they need to use
consumer facing APIs.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Stephen Boyd [Mon, 8 Feb 2016 22:59:49 +0000 (14:59 -0800)]
clkdev: Add clk_hw based registration APIs
Now that we have a clk registration API that doesn't return
struct clks, we need to have some way to hand out struct clks via
the clk_get() APIs that doesn't involve associating struct clk
pointers with a struct clk_lookup. Luckily, clkdev already
operates on struct clk_hw pointers, except for the registration
facing APIs where it converts struct clk pointers into struct
clk_hw pointers almost immediately.
Let's add clk_hw based registration APIs so that we can skip the
conversion step and provide a way for clk provider drivers to
operate exclusively on clk_hw structs. This way we clearly
split the API between consumers and providers.
Cc: Russell King <linux@arm.linux.org.uk> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Stephen Boyd [Sat, 6 Feb 2016 01:38:26 +0000 (17:38 -0800)]
clk: Add clk_hw OF clk providers
Now that we have a clk registration API that doesn't return
struct clks, we need to have some way to hand out struct clks via
the clk_get() APIs that doesn't involve associating struct clk
pointers with an OF node. Currently we ask the OF provider to
give us a struct clk pointer for some clkspec, turn that struct
clk into a struct clk_hw and then allocate a new struct clk to
return to the caller.
Let's add a clk_hw based OF provider hook that returns a struct
clk_hw directly, so that we skip the intermediate step of
converting from struct clk to struct clk_hw. Eventually when
we've converted all OF clk providers to struct clk_hw based APIs
we can remove the struct clk based ones.
It should also be noted that we change the onecell provider to
have a flex array instead of a pointer for the array of clk_hw
pointers. This allows providers to allocate one structure of the
correct length in one step instead of two.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
We've largely split the clk consumer and provider APIs along
struct clk and struct clk_hw, but clk_register() still returns a
struct clk pointer for each struct clk_hw that's registered.
Eventually we'd like to only allocate struct clks when there's a
user, because struct clk is per-user now, so clk_register() needs
to change.
Let's add new APIs to register struct clk_hws, but this time
we'll hide the struct clk from the caller by returning an int
error code. Also add an unregistration API that takes the clk_hw
structure that was passed to the registration API. This way
provider drivers never have to deal with a struct clk pointer
unless they're using the clk consumer APIs.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Stephen Boyd [Sat, 6 Feb 2016 00:40:47 +0000 (16:40 -0800)]
clkdev: Remove clk_register_clkdevs()
Now that we've converted the only caller over to another clkdev
API, remove this one.
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Cc: Russell King <linux@arm.linux.org.uk> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
The internal clk header did contain a comment indicating that some of the
defined registers were shared over multiple clock controller variants.
In recent times, it was simply extended all the time and stopped providing
any meaningful information, so drop it and it's overlong line.
clk: rockchip: reign in some overly long lines in the rk3399 controller
We allow overlong lines in the array portitions describing the clock
trees to ease readability by having each element always at the same
position. But the rest of the code should honor the 80 char limit.
Fix the newly added rk3399 clock code to respect that.
clk: ti: dra7: fix kernel boot with arg 'clocksource=gp_timer'
The OMAP Platform code provides possibility to select GP Timer as
default clocksource instead of counter_32K by using bootcmd parameter
'clocksource', but the system will crash during early boot when this
option is used on dra7 or omap5 platforms, because it will hit BUG()
statement:
omap2_gptimer_clocksource_init
->BUG_ON(res);
This happens because clk_dev alias "sys_clkin_ck" is not registered.
Hence, fix it by adding missing "sys_clkin_ck" clk_dev aliases
definitions for omap5 and dra7.
Acked-by: Tero Kristo <t-kristo@ti.com> Cc: Tony Lindgren <tony@atomide.com> Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Tero Kristo [Wed, 16 Mar 2016 19:54:56 +0000 (21:54 +0200)]
clk: ti: amx3xx: limit the maximum frequency of DPLLs based on spec
AM33xx/AM43xx devices use the same DPLL IP blocks, which only support
maximum rate of 1GHz [1] for the default and 2GHz for the low-jitter type
DPLLs [2]. Reflect this limitation in the DPLL init code by adding the
max-rate parameter based on the DPLL types.
[1] Functional, integration & test specification for GS70 ADPLLS, Rev 1.0-01
[2] Functional, integration & test specification for GS70 ADPLLLJ, Rev 0.8-02
Signed-off-by: Tero Kristo <t-kristo@ti.com> Cc: Nishanth Menon <nm@ti.com> Cc: Tomi Valkeinen <tomi.valkeinen@ti.com> Cc: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Tero Kristo [Wed, 16 Mar 2016 19:54:55 +0000 (21:54 +0200)]
clk: ti: dpll: add support for specifying max rate for DPLLs
DPLLs typically have a maximum rate they can support, and this varies
from DPLL to DPLL. Add support of the maximum rate value to the DPLL
data struct, and also add check for this in the DPLL round_rate function.
Signed-off-by: Tero Kristo <t-kristo@ti.com> Reviewed-by: Nishanth Menon <nm@ti.com> Cc: Tomi Valkeinen <tomi.valkeinen@ti.com> Cc: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
clk: at91: fix check of clk_register() returned value
The clk_register() function returns a valid pointer to struct clk or
ERR_PTR() error code, this makes a check for returned NULL value
useless and may lead to oops on error path.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com> Fixes: bcc5fd49a0fd ("clk: at91: add a driver for the h32mx clock") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Lars Persson [Mon, 4 Apr 2016 09:23:23 +0000 (11:23 +0200)]
clk: add artpec-6 clock controller
Add a driver for the main clock controller of the Artpec-6 Soc.
Signed-off-by: Lars Persson <larper@axis.com>
[sboyd@codeaurora.org: Reformatted driver structure and of match] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Lars Persson [Mon, 4 Apr 2016 09:23:22 +0000 (11:23 +0200)]
clk: add device tree binding for Artpec-6 clock controller
Add device tree documentation for the main clock controller in the
Artpec-6 SoC.
Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Lars Persson <larper@axis.com>
[sboyd@codeaurora.org: Added unit address to binding example] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Suman Anna [Tue, 5 Apr 2016 18:28:57 +0000 (13:28 -0500)]
clk: ti: dflt: remove redundant unlikely
Commit 7aba4f5201d1 ("clk: ti: dflt: fix enable_reg validity check")
fixed a validation check by using an IS_ERR() macro within the
existing unlikely expression, but IS_ERR() macro already has an
unlikely inside it, so get rid of the redundant unlikely macro
from the validation check.
Reported-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Stephen Boyd [Fri, 15 Apr 2016 22:47:54 +0000 (15:47 -0700)]
Merge tag 'v4.7-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next
Pull rockchip clk updates from Heiko Stuebner:
This is first big chunk of Rockchip clock-related changes for 4.7.
Main change is probably the added support for the new rk3399 soc
and necessary infrastructure changes surrounding it.
The biggest chunk is probably that clock code is now able to
handle multiple clock providers in one system, as the rk3399
has two of those. A general one and another smaller one in a
separate power domain. The rk3399 also uses another new pll type.
Thankfully it just fits nicely into our current structure.
It also needs some parts like the cpuclk mux parameters to be
a bit more flexible and an new fractional divider subtype without
gate.
Apart from this big change we have some more fixes and removal
of forgotten variables.
* tag 'v4.7-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
clk: rockchip: add clock controller for the RK3399
dt-bindings: add bindings for rk3399 clock controller
clk: rockchip: add dt-binding header for rk3399
clk: rockchip: release io resource when failing to init clk
clk: rockchip: remove redundant checking of device_node
clk: rockchip: fix warning reported by kernel-doc
clk: rockchip: remove mux_core_reg from rockchip_cpuclk_reg_data
clk: rockchip: add new pll-type for rk3399 and similar socs
clk: rockchip: Add support for multiple clock providers
clk: rockchip: allow varying mux parameters for cpuclk pll-sources
clk: rockchip: add a COMPOSITE_FRACMUX_NOGATE type
Stephen Boyd [Fri, 15 Apr 2016 22:42:31 +0000 (15:42 -0700)]
Merge tag 'imx-clk-4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into clk-next
The i.MX clock update for 4.7:
- Register SAI clk as shared clocks to support SAI audio on i.MX6SX
- Add the missing ckil clock for i.MX7
- Update clk-gate2 and vf610 clock driver to prepare for suspend
support on VF610
- Fix DCU clock configurations and add TCON ipg clock to support DRM
display on VF610
* tag 'imx-clk-4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
clk: imx: vf610: fix whitespace in vf610-clock.h
clk: imx: vf610: add TCON ipg clock
clk: imx: vf610: fix DCU clock tree
clk: imx: add ckil clock for i.MX7
clk: imx: vf610: add suspend/resume support
clk: imx: vf610: add WKPU unit
clk: imx: vf610: leave DDR clock on
clk: imx: clk-gate2: allow custom gate configuration
clk: imx6sx: Register SAI clocks as shared clocks
Stephen Boyd [Fri, 15 Apr 2016 22:19:32 +0000 (15:19 -0700)]
Merge tag 'clk-v4.7-samsung' of git://linuxtv.org/snawrocki/samsung into clk-next
Pull samsung clk updates from Sylwester Nawrocki:
This includes addition of some missing clock tree definitions
(UART, MMC2 clocks) for exynos3250 SoC and exporting of IDs
for exynos543x SoC AMBA AXI bus clocks needed for bus frequency
scaling.
* tag 'clk-v4.7-samsung' of git://linuxtv.org/snawrocki/samsung:
clk: samsung: exynos542x: Add the clock id for ACLK
dt-bindings: clock: Add the clock id for ACLK clock of Exynos542x SoC
clk: samsung: exynos3250: Add MMC2 clock
clk: samsung: exynos3250: Add UART2 clock
dt-bindings: Add the clock id of UART2 and MMC2 for Exynos3250
When changing the clock-rate, currently a new parent is set first and a
divider adapted thereafter. This may result in the clock-rate overflowing
its target rate for a short time if the new parent has a higher rate than
the old parent.
While this often doesn't produce negative effects, it can affect components
in a voltage-scaling environment, like the GPU on the rk3399 socs, where
the voltage than simply is to low for the temporarily to high clock rate.
For general clock hirarchies this may need more extensive adaptions to
the common clock-framework, but at least for composite clocks having
both parent and rate settings it is easy to create a short-term solution to
make sure the clock-rate does not overflow the target.
dt-bindings: clock: Add the clock id for ACLK clock of Exynos542x SoC
This patch adds the clock id for ACLK clock of Exynos542x SoC.
ACLK clock means the source clock of AMBA AXI bus. This clock
id should be used for Bus frequency scaling.
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Tested-by: Markus Reichl <m.reichl@fivetechno.de> Tested-by: Anand Moon <linux.amoon@gmail.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Stefan Agner [Tue, 12 Apr 2016 00:59:38 +0000 (08:59 +0800)]
clk: imx: vf610: add TCON ipg clock
Add the ipg (bus) clock for the TCON modules (Timing Controller). This
module is required by the new DCU DRM driver, since the display signals
pass through TCON.
Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Stefan Agner [Tue, 5 Apr 2016 05:28:33 +0000 (22:28 -0700)]
clk: imx: vf610: fix DCU clock tree
Similar to an earlier fix for the SAI clocks, the DCU clock hierarchy
mixes the bus clock with the display controllers pixel clock. Tests
have shown that the gates in CCM_CCGR3/9 registers do not control
the DCU pixel clock, but only the register access clock (bus clock).
Fix this by defining the parent clock of VF610_CLK_DCUx to be the bus
clock (ipg_bus).
Since the clock has not been used far, there are no further changes
needed.
Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Lee Jones [Thu, 11 Feb 2016 21:19:11 +0000 (13:19 -0800)]
clk: Provide OF helper to mark clocks as CRITICAL
This call matches clocks which have been marked as critical in DT
and sets the appropriate flag. These flags can then be used to
mark the clock core flags appropriately prior to registration.
Legacy bindings requiring this feature must add the clock-critical
property to their binding descriptions, as it is not a part of
common-clock binding.
Cc: devicetree@vger.kernel.org Signed-off-by: Lee Jones <lee.jones@linaro.org> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/1455225554-13267-4-git-send-email-mturquette@baylibre.com
Lee Jones [Thu, 11 Feb 2016 21:19:10 +0000 (13:19 -0800)]
clk: WARN_ON about to disable a critical clock
Signed-off-by: Lee Jones <lee.jones@linaro.org> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/1455225554-13267-3-git-send-email-mturquette@baylibre.com
Lee Jones [Thu, 11 Feb 2016 21:19:09 +0000 (13:19 -0800)]
clk: Allow clocks to be marked as CRITICAL
Critical clocks are those which must not be gated, else undefined
or catastrophic failure would occur. Here we have chosen to
ensure the prepare/enable counts are correctly incremented, so as
not to confuse users with enabled clocks with no visible users.
Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/1455225554-13267-2-git-send-email-mturquette@baylibre.com
Make it clear that the "domain" parameter of the cpg_mstp_attach_dev()
and cpg_mstp_detach_dev() functions is not used.
The cpg_mstp_attach_dev() and cpg_mstp_detach_dev() callbacks are not
only used by the CPG/MSTP Clock Domain driver, but also by the R-Mobile
SYSC PM Domain driver.
clk: renesas: cpg-mssr: Drop check for CONFIG_PM_GENERIC_DOMAINS_OF
As of commit 71d076ceb245f0d9 ("ARM: shmobile: Enable PM and
PM_GENERIC_DOMAINS for SoCs with PM Domains"),
CONFIG_PM_GENERIC_DOMAINS_OF is always enabled for SoCs with a CPG/MSSR
block.
clk: renesas: mstp: Drop check for CONFIG_PM_GENERIC_DOMAINS_OF
As of commit 71d076ceb245f0d9 ("ARM: shmobile: Enable PM and
PM_GENERIC_DOMAINS for SoCs with PM Domains"),
CONFIG_PM_GENERIC_DOMAINS_OF is always enabled for SoCs with MSTP
clocks.
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