]> git.karo-electronics.de Git - linux-beck.git/log
linux-beck.git
8 years agoclk: imx7d: do not set parent of ethernet time/ref clocks
Stefan Agner [Sun, 3 Jul 2016 17:48:13 +0000 (10:48 -0700)]
clk: imx7d: do not set parent of ethernet time/ref clocks

All device trees currently in mainline specify the time clock parent
using the assigned-clocks/assigned-clock-parents method, there is no
need to statically assign the parent in the core clock driver.
Also all current boards provide an Ethernet reference clock for the
PHY externally, hence configuring the internal PHY reference clock.

Furthermore, and the actual driver of this patch, specify ethernet
related parents at that early point in boot leads to a warning:
bad: scheduling from the idle thread!

The reason for the warning is that setting the parent enables the ENET
PLL since we are using CLK_OPS_PARENT_ENABLE. Enabling the ENET PLL can
cause clk_pllv3_wait_lock to sleep. See also:
commit fc8726a2c021 ("clk: core: support clocks which requires parents
enable (part 2)").

Note that setting the ENET AXI root clock parent also requires ENET
PLL to be enabled. However, U-Boot typically leaves the ENET PLL on,
hence when the framework sets the parent of the first clock, it does
not need to wait for the PLL to come up. But because there is currently
no user of that clock, the PLL gets disabled after setting the parent.
Therefore, subsequent reparenting calls of any clock which somehow rely
on the ENET PLL, need to reenable the ENET PLL which leads to a sleep.
Removing those subsequent reparenting calls works around this issue.

Also remove comments. The code is really verbose enough.

Signed-off-by: Stefan Agner <stefan@agner.ch>
Tested-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/20160703174813.13970-1-stefan@agner.ch

8 years agoMerge branch 'clk-sunxi-ng' into clk-next
Michael Turquette [Mon, 11 Jul 2016 21:39:47 +0000 (14:39 -0700)]
Merge branch 'clk-sunxi-ng' into clk-next

8 years agoARM: dt: sun8i: switch the H3 to the new CCU driver
Maxime Ripard [Wed, 29 Jun 2016 19:05:35 +0000 (21:05 +0200)]
ARM: dt: sun8i: switch the H3 to the new CCU driver

Now that we have a different clock representation, switch to it.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/20160629190535.11855-15-maxime.ripard@free-electrons.com

8 years agoclk: sunxi-ng: h3: Fix Kconfig symbol typo
Maxime Ripard [Mon, 11 Jul 2016 20:34:48 +0000 (22:34 +0200)]
clk: sunxi-ng: h3: Fix Kconfig symbol typo

The Kconfig symbol for the sun8i SoC family was mistyped. Fix that.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/20160711203448.18062-2-maxime.ripard@free-electrons.com

8 years agoclk: sunxi-ng: h3: Fix audio clock divider offset
Maxime Ripard [Mon, 11 Jul 2016 20:34:47 +0000 (22:34 +0200)]
clk: sunxi-ng: h3: Fix audio clock divider offset

The code had a typo and got the wrong offset for the hardcoded divider, fix
that.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reported-by: Jean-Francois Moine <moinejf@free.fr>
Reported-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/20160711203448.18062-1-maxime.ripard@free-electrons.com

8 years agoMerge branch 'clk-sunxi-ng' into clk-next
Michael Turquette [Sat, 9 Jul 2016 01:08:56 +0000 (18:08 -0700)]
Merge branch 'clk-sunxi-ng' into clk-next

8 years agoclk: sunxi-ng: Add H3 clocks
Maxime Ripard [Wed, 29 Jun 2016 19:05:34 +0000 (21:05 +0200)]
clk: sunxi-ng: Add H3 clocks

Add the list of clocks and resets found in the H3 CCU.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/20160629190535.11855-14-maxime.ripard@free-electrons.com

8 years agoclk: sunxi-ng: Add N-K-M-P factor clock
Maxime Ripard [Wed, 29 Jun 2016 19:05:33 +0000 (21:05 +0200)]
clk: sunxi-ng: Add N-K-M-P factor clock

Introduce support for clocks that use a combination of two linear
multipliers (N and K factors), one linear divider (M) and one power of two
divider (P).

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/20160629190535.11855-13-maxime.ripard@free-electrons.com

8 years agoclk: sunxi-ng: Add N-K-M Factor clock
Maxime Ripard [Wed, 29 Jun 2016 19:05:32 +0000 (21:05 +0200)]
clk: sunxi-ng: Add N-K-M Factor clock

Introduce support for clocks that multiply and divide using two linear
multipliers and one linear divider.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/20160629190535.11855-12-maxime.ripard@free-electrons.com

8 years agoclk: sunxi-ng: Add N-M-factor clock support
Maxime Ripard [Wed, 29 Jun 2016 19:05:31 +0000 (21:05 +0200)]
clk: sunxi-ng: Add N-M-factor clock support

Introduce support for clocks that multiply and divide using linear factors.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/20160629190535.11855-11-maxime.ripard@free-electrons.com

8 years agoclk: sunxi-ng: Add N-K-factor clock support
Maxime Ripard [Wed, 29 Jun 2016 19:05:30 +0000 (21:05 +0200)]
clk: sunxi-ng: Add N-K-factor clock support

Introduce support for clocks that use a combination of two linear
multipliers.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/20160629190535.11855-10-maxime.ripard@free-electrons.com

8 years agoclk: sunxi-ng: Add M-P factor clock support
Maxime Ripard [Wed, 29 Jun 2016 19:05:29 +0000 (21:05 +0200)]
clk: sunxi-ng: Add M-P factor clock support

Introduce support for the clocks that combine a linear divider and a
power-of-two based one.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/20160629190535.11855-9-maxime.ripard@free-electrons.com

8 years agoclk: sunxi-ng: Add divider
Maxime Ripard [Wed, 29 Jun 2016 19:05:28 +0000 (21:05 +0200)]
clk: sunxi-ng: Add divider

Add support for the various dividers (linear, table or pow-of-two based)
found in the CCU.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/20160629190535.11855-8-maxime.ripard@free-electrons.com

8 years agoclk: sunxi-ng: Add phase clock support
Maxime Ripard [Wed, 29 Jun 2016 19:05:27 +0000 (21:05 +0200)]
clk: sunxi-ng: Add phase clock support

Add support for the clocks in the CCU that introduce a phase shift from
their parent clock.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/20160629190535.11855-7-maxime.ripard@free-electrons.com

8 years agoclk: sunxi-ng: Add mux clock support
Maxime Ripard [Wed, 29 Jun 2016 19:05:26 +0000 (21:05 +0200)]
clk: sunxi-ng: Add mux clock support

Some clocks in the Allwinner SoCs clocks unit are just muxes.

However, those muxes might also be found in some other complicated clocks
that would benefit from the code in there to deal with "advanced" features,
like pre-dividers.

Introduce a set of helpers to reduce the code duplication in such cases.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/20160629190535.11855-6-maxime.ripard@free-electrons.com

8 years agoclk: sunxi-ng: Add gate clock support
Maxime Ripard [Wed, 29 Jun 2016 19:05:25 +0000 (21:05 +0200)]
clk: sunxi-ng: Add gate clock support

Some clocks in the Allwinner SoCs clocks unit are just simple gates. Add
support for those clocks.

Since it's a feature that can also be found in more complex clocks, provide
a bunch of helpers that can be reused later on.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/20160629190535.11855-5-maxime.ripard@free-electrons.com

8 years agoclk: sunxi-ng: Add fractional lib
Maxime Ripard [Wed, 29 Jun 2016 19:05:24 +0000 (21:05 +0200)]
clk: sunxi-ng: Add fractional lib

Some clocks can be switched to a mode called fractional that have two fixed
output rate you can choose from.

Add a small library to deal with those clocks.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/20160629190535.11855-4-maxime.ripard@free-electrons.com

8 years agoclk: sunxi-ng: Add common infrastructure
Maxime Ripard [Wed, 29 Jun 2016 19:05:23 +0000 (21:05 +0200)]
clk: sunxi-ng: Add common infrastructure

Start our new clock infrastructure by adding the registration code, common
structure and common code.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/20160629190535.11855-3-maxime.ripard@free-electrons.com

8 years agodt-bindings: sunxi: Add CCU binding documentation
Maxime Ripard [Wed, 29 Jun 2016 19:05:22 +0000 (21:05 +0200)]
dt-bindings: sunxi: Add CCU binding documentation

Introduce a new binding with its documentation for the brand new clock
sub-framework.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/20160629190535.11855-2-maxime.ripard@free-electrons.com

8 years agoclk: imx: vf610: Disable automatic clock gating for lpuart in LPSTOP mode
Stefan Agner [Tue, 28 Jun 2016 05:32:28 +0000 (11:02 +0530)]
clk: imx: vf610: Disable automatic clock gating for lpuart in LPSTOP mode

In order to allow wake support in STOP sleep mode, clocks are needed. Use
imx_clk_gate2_cgr to disable automatic clock gating in low power mode STOP.
This allows to enable wake by UART using:
echo enabled > /sys/class/tty/ttyLP0/power/wakeup

However, if wake is not enabled, the driver should disable the clocks explicitly
to save power.

Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/20160628053235.5114-3-bhuvanchandra.dv@toradex.com

8 years agoclk: clk-conf: Fix error message when clock isn't found
Tomeu Vizoso [Fri, 8 Jul 2016 07:14:38 +0000 (09:14 +0200)]
clk: clk-conf: Fix error message when clock isn't found

When failing to lookup the assigned clock for setting its parents, we
were previously printing a misleading error message that lead to think
that it was the parent clock what couldn't be found.

Change error message to make clear that it's the assigned clock what
couldn't be found in this case.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/1467962078-30405-1-git-send-email-tomeu.vizoso@collabora.com

8 years agoMerge branch 'clk-s905' into clk-next
Michael Turquette [Fri, 8 Jul 2016 03:06:30 +0000 (20:06 -0700)]
Merge branch 'clk-s905' into clk-next

8 years agoclk: gxbb: expose CLKID_MMC_PCLK
Kevin Hilman [Thu, 7 Jul 2016 03:38:37 +0000 (20:38 -0700)]
clk: gxbb: expose CLKID_MMC_PCLK

The MMC_PCLK is needed for the SD/eMMC driver, expose to DT (and comment
out in clk driver)

Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/20160707033837.20029-1-khilman@baylibre.com

8 years agoclk: stm32f4: fix error handling
Christophe JAILLET [Sun, 3 Jul 2016 06:06:43 +0000 (08:06 +0200)]
clk: stm32f4: fix error handling

This is likely that checking 'clks[idx]' instead of 'clks[n]' is
expected here.

Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/1467526003-13318-1-git-send-email-christophe.jaillet@wanadoo.fr

8 years agoMerge branch 'clk-lpc32xx' into clk-next
Michael Turquette [Thu, 7 Jul 2016 00:51:42 +0000 (17:51 -0700)]
Merge branch 'clk-lpc32xx' into clk-next

8 years agoclk: lpc32xx: allow peripheral clock selection in device tree
Sylvain Lemieux [Fri, 3 Jun 2016 19:34:35 +0000 (15:34 -0400)]
clk: lpc32xx: allow peripheral clock selection in device tree

This patch add the support to select the peripheral clock (PERIPH)
as a parent clock source using the "assigned-clock-parents"
parameter in the device tree.

Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
Acked-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/1464982475-24738-1-git-send-email-slemieux.tyco@gmail.com

8 years agoclk: sunxi: make clk-* explicitly non-modular
Paul Gortmaker [Mon, 4 Jul 2016 21:12:18 +0000 (17:12 -0400)]
clk: sunxi: make clk-* explicitly non-modular

We have the following file --> Kconfig mapping:

sunxi/clk-factors.c              obj-y
sunxi/clk-sun6i-apb0-gates.c     CONFIG_MFD_SUN6I_PRCM (bool)
sunxi/clk-sun6i-apb0.c           CONFIG_MFD_SUN6I_PRCM
sunxi/clk-sun6i-ar100.c          CONFIG_MFD_SUN6I_PRCM
sunxi/clk-sun8i-apb0.c           CONFIG_MFD_SUN6I_PRCM
sunxi/clk-sun9i-mmc.c            obj-y

Hence none of these are being built as a module by anyone.

Lets remove the modular code that is essentially orphaned, so that
when reading the drivers there is no doubt they are builtin-only.  All
drivers get mostly the same changes, so they are handled in batch.

Changes are (1) convert to builtin_platform_register, (2) use the
init.h header, (3) delete the MODULE_LICENCE/MODULE_AUTHOR and
associated tags, and (4) delete any ".remove" functions.

There was a stray module.h in a file not using any init.h or
module.h stuff, so we simply removed that one.

In two cases, we explicitly disallow a driver unbind, since that
doesn't have a sensible use case anyway, and it allows us to drop
the ".remove" code for non-modular drivers.

Since module_platform_driver() uses the same init level priority as
builtin_platform_driver() the init ordering remains unchanged with
this commit.

We delete the MODULE_LICENSE etc. tags since all that information
is already contained at the top of each file in the comments.

Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Cc: Chen-Yu Tsai <wens@csie.org>
Cc: "Emilio López" <emilio@elopez.com.ar>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: linux-clk@vger.kernel.org
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/20160704211220.5685-9-paul.gortmaker@windriver.com

8 years agoclk: oxnas: make it explicitly non-modular
Paul Gortmaker [Mon, 4 Jul 2016 21:12:15 +0000 (17:12 -0400)]
clk: oxnas: make it explicitly non-modular

The Kconfig currently controlling compilation of this code is:

drivers/clk/Kconfig:config COMMON_CLK_OXNAS
drivers/clk/Kconfig:    bool "Clock driver for the OXNAS SoC Family"

...meaning that it currently is not being built as a module by anyone.

Lets remove the modular code that is essentially orphaned, so that
when reading the driver there is no doubt it is builtin-only.

We explicitly disallow a driver unbind, since that doesn't have a
sensible use case anyway, and it allows us to drop the ".remove"
code for non-modular drivers.

Since module_platform_driver() uses the same init level priority as
builtin_platform_driver() the init ordering remains unchanged with
this commit.

Also note that MODULE_DEVICE_TABLE is a no-op for non-modular code.

Cc: Stephen Boyd <sboyd@codeaurora.org>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Cc: linux-clk@vger.kernel.org
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/20160704211220.5685-6-paul.gortmaker@windriver.com

8 years agoclk: Kconfig: Name RK818 in Kconfig for COMMON_CLK_RK808
Wadim Egorov [Thu, 2 Jun 2016 06:50:27 +0000 (08:50 +0200)]
clk: Kconfig: Name RK818 in Kconfig for COMMON_CLK_RK808

The RK808 and RK818 PMICs are using a similar register map.
We can reuse the clk driver for the RK818 PMIC. So let's add
the RK818 in the Kconfig description.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/1464850228-17244-4-git-send-email-w.egorov@phytec.de

8 years agoclk: hi6220: Change syspll and media_syspll clk to 1.19GHz
Xinliang Liu [Wed, 29 Jun 2016 08:45:54 +0000 (16:45 +0800)]
clk: hi6220: Change syspll and media_syspll clk to 1.19GHz

In the bootloader of HiKey/96boards, syspll and media_syspll clk
was initialized to 1.19GHz. So, here changes it in kernel accordingly.

1.19GHz was chosen over 1.2GHz because at 1.19GHz we get more precise
HDMI pixel clock (1.19G/16 = 74.4MHz) for 1280x720p@60Hz HDMI
(74.25MHz required by standards). Closer pixel clock means better
compatibility to HDMI monitors.

Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
Signed-off-by: Xinliang Liu <xinliang.liu@linaro.org>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/1467189955-21694-1-git-send-email-guodong.xu@linaro.org

8 years agoclk: meson: make gxbb explicitly non-modular
Paul Gortmaker [Mon, 4 Jul 2016 21:12:12 +0000 (17:12 -0400)]
clk: meson: make gxbb explicitly non-modular

The Kconfig currently controlling compilation of this code is:

drivers/clk/meson/Kconfig:config COMMON_CLK_GXBB
drivers/clk/meson/Kconfig:      bool

...meaning that it currently is not being built as a module by anyone.

Lets remove the modular code that is essentially orphaned, so that
when reading the driver there is no doubt it is builtin-only.

Since module_init translates to device_initcall in the non-modular
case, the init ordering remains unchanged with this commit.

Also note that MODULE_DEVICE_TABLE and ALIAS are no-op for non-modules.

We also delete the MODULE_LICENSE tag etc. since all that information
was (or is now) contained at the top of the file in the comments.

Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Carlo Caione <carlo@caione.org>
Cc: Kevin Hilman <khilman@baylibre.com>
Cc: linux-clk@vger.kernel.org
Cc: linux-amlogic@lists.infradead.org
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/20160704211220.5685-3-paul.gortmaker@windriver.com

8 years agoclk: meson8b: make it explicitly non-modular
Paul Gortmaker [Mon, 4 Jul 2016 21:12:11 +0000 (17:12 -0400)]
clk: meson8b: make it explicitly non-modular

The Kconfig currently controlling compilation of this code is:

drivers/clk/meson/Kconfig:config COMMON_CLK_MESON8B
drivers/clk/meson/Kconfig:      bool

...meaning that it currently is not being built as a module by anyone.
However a recent commit added a bunch of modular boilerplate to this
driver.

Lets remove the modular code that is essentially orphaned, so that
when reading the driver there is no doubt it is builtin-only.

Since module_init translates to device_initcall in the non-modular
case, the init ordering remains unchanged with this commit.

Also note that MODULE DEVICE_TABLE/ALIAS are no-op when non-modular.

We also delete the MODULE_LICENSE tag etc. since all that information
was (or is now) contained at the top of the file in the comments.

Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Carlo Caione <carlo@caione.org>
Cc: Kevin Hilman <khilman@baylibre.com>
Cc: linux-clk@vger.kernel.org
Cc: linux-amlogic@lists.infradead.org
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/20160704211220.5685-2-paul.gortmaker@windriver.com

8 years agoclk: qcom: add EBI2 clocks to the MSM8660 GCC
Linus Walleij [Fri, 1 Jul 2016 15:54:01 +0000 (17:54 +0200)]
clk: qcom: add EBI2 clocks to the MSM8660 GCC

This adds the EBI2 2X and EBI2 clocks to the MSM8660/APQ8060
GCC. This is necessary to enable clocking of the external bus
interface so that peripherals on it can be mounted. These two
clocks are simple gated branch clocks.

In the vendor tree clock-8x60, these clocks have some kind of
dependency, the EBI2 clock has .depends = &ebi2_2x_clk.c,
what this means is undocumented, it doesn't seem like there
is a parent/child relationship, so the solution I chose was to
just have the EBI2 driver get and enable both clocks.

Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
8 years agoclk: imx7d: only enable minimum required clocks
Dong Aisheng [Thu, 30 Jun 2016 09:31:18 +0000 (17:31 +0800)]
clk: imx7d: only enable minimum required clocks

Formerly clk core does not support imx7d clock type well that all
its clock operations requires the parent clock on.
Therefore we enabled all clocks by default in clock driver
initialization for other module clocks operate well.

After patch 'clk: imx7d: using api with flag CLK_OPS_PARENT_ENABLE',
clk core can handle such clock type well, so we don't have to enable
them all by default anymore. Instead, we only enable a minimum required
set of clocks.

Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
8 years agoclk: imx7d: using api with flag CLK_OPS_PARENT_ENABLE
Dong Aisheng [Thu, 30 Jun 2016 09:31:17 +0000 (17:31 +0800)]
clk: imx7d: using api with flag CLK_OPS_PARENT_ENABLE

i.MX7D requires all clocks operations including enable/disable,
rate change and re-parent with its parent clock on.
Changing to the correct APIs to tell clk core such requirement.

Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
8 years agoclk: imx: add clk api for supporting CLK_OPS_PARENT_ENABLE clocks
Dong Aisheng [Thu, 30 Jun 2016 09:31:16 +0000 (17:31 +0800)]
clk: imx: add clk api for supporting CLK_OPS_PARENT_ENABLE clocks

IMX SoCs like i.MX7D requires using CLK_OPS_PARENT_ENABLE flags,
adding the corresponding clock APIs variants for easily to use.

Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
8 years agoclk: imx: re-order and concentrate the same type of clk api
Dong Aisheng [Thu, 30 Jun 2016 09:31:15 +0000 (17:31 +0800)]
clk: imx: re-order and concentrate the same type of clk api

Re-order and concentrate the same type of clk api for better
code maintenance.

Cc: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
8 years agoclk: core: support clocks which requires parents enable (part 2)
Dong Aisheng [Thu, 30 Jun 2016 09:31:14 +0000 (17:31 +0800)]
clk: core: support clocks which requires parents enable (part 2)

On Freescale i.MX7D platform, all clocks operations, including
enable/disable, rate change and re-parent, requires its parent clock on.
Current clock core can not support it well.
This patch adding flag CLK_OPS_PARENT_ENABLE to handle this special case in
clock core that enable its parent clock firstly for each operation and
disable it later after operation complete.

The patch part 2 fixes set clock rate and set parent while its parent
is off. The most special case is for set_parent() operation which requires
all parents including both old and new one to be enabled at the same time
during the operation.

Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
[sboyd@codeaurora.org: Move set_rate tracepoint after prepare_enable]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
8 years agoclk: core: support clocks which requires parents enable (part 1)
Dong Aisheng [Thu, 30 Jun 2016 09:31:13 +0000 (17:31 +0800)]
clk: core: support clocks which requires parents enable (part 1)

On Freescale i.MX7D platform, all clocks operations, including
enable/disable, rate change and re-parent, requires its parent
clock enable. Current clock core can not support it well.
This patch introduce a new flag CLK_OPS_PARENT_ENABLE to handle this
special case in clock core that enable its parent clock firstly for
each operation and disable it later after operation complete.

The patch part 1 fixes the possible disabling clocks while its parent
is off during kernel booting phase in clk_disable_unused_subtree().

Before the completion of kernel booting, clock tree is still not built
completely, there may be a case that the child clock is on but its
parent is off which could be caused by either HW initial reset state
or bootloader initialization.

Taking bootloader as an example, we may enable all clocks in HW by default.
And during kernel booting time, the parent clock could be disabled in its
driver probe due to calling clk_prepare_enable and clk_disable_unprepare.
Because it's child clock is only enabled in HW while its SW usecount
in clock tree is still 0, so clk_disable of parent clock will gate
the parent clock in both HW and SW usecount ultimately. Then there will
be a child clock is still on in HW but its parent is already off.

Later in clk_disable_unused(), this clock disable accessing while its
parent off will cause system hang due to the limitation of HW which
must require its parent on.

This patch simply enables the parent clock first before disabling
if flag CLK_OPS_PARENT_ENABLE is set in clk_disable_unused_subtree().
This is a simple solution and only affects booting time.

After kernel booting up the clock tree is already created, there will
be no case that child is off but its parent is off.
So no need do this checking for normal clk_disable() later.

Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
8 years agoclk: move clk_disable_unused after clk_core_disable_unprepare function
Dong Aisheng [Thu, 30 Jun 2016 09:31:12 +0000 (17:31 +0800)]
clk: move clk_disable_unused after clk_core_disable_unprepare function

No function level change, just moving code place.
clk_disable_unused function will need to call clk_core_prepare_enable/
clk_core_disable_unprepare when adding CLK_OPS_PARENT_ENABLE features.
So move it after clk_core_disable_unprepare to avoid adding forward
declared functions later.

Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
8 years agoclk: introduce clk_core_enable_lock and clk_core_disable_lock functions
Dong Aisheng [Thu, 30 Jun 2016 09:31:11 +0000 (17:31 +0800)]
clk: introduce clk_core_enable_lock and clk_core_disable_lock functions

This can be useful when clock core wants to enable/disable clocks.
Then we don't have to convert the struct clk_core to struct clk to call
clk_enable/clk_disable which is a bit un-align with exist using.

And after introduce clk_core_{enable|disable}_lock, we can refine
clk_enable and clk_disable a bit.

As well as clk_core_{enable|disable}_lock, we also added
clk_core_{prepare|unprepare}_lock and clk_core_prepare_enable/
clk_core_unprepare_disable for clock core to easily use.

Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
8 years agoMerge tag 'v4.8-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind...
Stephen Boyd [Sat, 2 Jul 2016 00:30:42 +0000 (17:30 -0700)]
Merge tag 'v4.8-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next

Pull rockchip clk driver updates from Heiko Stuebner:

Placeholder for the rk3399 watchdog pclk, some newly exported
rk3228 clockids and a small fix for the not yet used spdif to
displayport clock on the rk3399.

* tag 'v4.8-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  clk: rockchip: fix incorrect rk3399 spdif-DPTX divider bits
  clk: rockchip: export rk3228 MAC clocks
  clk: rockchip: rename rk3228 sclk_macphy_50m to sclk_mac_extclk
  clk: rockchip: export rk3228 audio clocks
  clk: rockchip: include rk3228 downstream muxes into fractional dividers
  clk: rockchip: fix incorrect rk3228 clock registers
  clk: rockchip: add clock-ids for rk3228 MAC clocks
  clk: rockchip: add clock-ids for rk3228 audio clocks
  clk: rockchip: add a dummy clock for the watchdog pclk on rk3399

8 years agoMerge tag 'tegra-for-4.8-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra...
Stephen Boyd [Sat, 2 Jul 2016 00:27:14 +0000 (17:27 -0700)]
Merge tag 'tegra-for-4.8-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-next

Pull tegra clk driver updates from Thierry Reding:

Fixes and enhancements mostly for Tegra210 clocks that allow DSI and
HDMI to work on Tegra X1. There's also a refactoring, including fixes,
the USB PLL.

* tag 'tegra-for-4.8-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  clk: tegra: Initialize UTMI PLL when enabling PLLU
  clk: tegra: Micro-optimize Tegra210 clock setup
  clk: tegra: Make sor_safe the parent of dpaux and dpaux1
  clk: tegra: Mark timer clock as critical
  clk: tegra: Enable sor1 and sor1_src on Tegra210
  clk: tegra: Squash sor1 safe/brick/src into a single mux
  clk: tegra: Disable spread spectrum on pll_d2
  clk: tegra: Fixup post dividers on Tegra210

8 years agoclk: fixed-factor: Allow for a few clocks to change the parent rate
Maxime Ripard [Wed, 22 Jun 2016 09:15:54 +0000 (11:15 +0200)]
clk: fixed-factor: Allow for a few clocks to change the parent rate

The only way for a fixed factor clock to change its rate would be to change
its parent rate.

Since passing blindly CLK_SET_RATE_PARENT might break a lot of platforms
that were relying on the fact that the parent rate wouldn't change,
introduce a compatible-based whitelist that will allow clocks to opt-in
that flag.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
8 years agoclk: rockchip: fix incorrect rk3399 spdif-DPTX divider bits
Xing Zheng [Thu, 30 Jun 2016 02:18:59 +0000 (10:18 +0800)]
clk: rockchip: fix incorrect rk3399 spdif-DPTX divider bits

The CLKSEL_CON32 bit_0 is controlled for spdif_8ch, not spdif_rec_dptx,
it should be bit_8, let's fix it.

Fixes: 115510053e5e ("clk: rockchip: add clock controller for the RK3399")
Reported-by: Chris Zhong <zyw@rock-chips.com>
Tested-by: Chris Zhong <zyw@rock-chips.com>
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Cc: stable@vger.kernel.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
8 years agoclk: rockchip: export rk3228 MAC clocks
Xing Zheng [Tue, 21 Jun 2016 04:59:47 +0000 (12:59 +0800)]
clk: rockchip: export rk3228 MAC clocks

This patch exports related MAC clocks for dts reference.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
8 years agoclk: rockchip: rename rk3228 sclk_macphy_50m to sclk_mac_extclk
Xing Zheng [Tue, 21 Jun 2016 04:53:30 +0000 (12:53 +0800)]
clk: rockchip: rename rk3228 sclk_macphy_50m to sclk_mac_extclk

The sclk_macphy_50m is confusing, the sclk_mac_extclk describes
a external clock  clearly.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
8 years agoclk: rockchip: export rk3228 audio clocks
Xing Zheng [Tue, 21 Jun 2016 04:53:29 +0000 (12:53 +0800)]
clk: rockchip: export rk3228 audio clocks

This patch exports related i2s/spdif clocks for dts reference.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
8 years agoMerge branch 'v4.8-shared/clkids' into v4.8-clk/next
Heiko Stuebner [Thu, 30 Jun 2016 23:49:53 +0000 (01:49 +0200)]
Merge branch 'v4.8-shared/clkids' into v4.8-clk/next

8 years agoclk: rockchip: include rk3228 downstream muxes into fractional dividers
Xing Zheng [Tue, 21 Jun 2016 04:53:28 +0000 (12:53 +0800)]
clk: rockchip: include rk3228 downstream muxes into fractional dividers

During the initial conversion to the newly introduced combined fractional
dividers+muxes the rk3228 clocks were left out, so convert them now.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
8 years agoMerge tag 'imx-clk-4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo...
Stephen Boyd [Thu, 30 Jun 2016 20:16:20 +0000 (13:16 -0700)]
Merge tag 'imx-clk-4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into clk-next

Pull i.MX clk driver updates from Shawn Guo:

 - A few correction and improvements on pllv3 driver around AV pll clock
   rate calculation, parent setting and power bit handling
 - Correct i.MX6UL GPT2 clock names
 - A couple of minor fixes on i.MX7D clock driver on DRAM clocks

* tag 'imx-clk-4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  clk: imx6ul: fix gpt2 clock names
  clk: imx: refine the powerdown bit of clk-pllv3
  clk: imx: clk-pllv3: fix incorrect handle of enet powerdown bit
  clk: imx: fix pll clock parents
  clk: imx7d: correct dram pll type
  clk: imx7d: correct dram root clk parent select
  clk: imx: correct AV PLL rate formula

8 years agoMerge branch 'clk-hw-unregister-fixed-rate' into clk-next
Stephen Boyd [Thu, 30 Jun 2016 20:07:58 +0000 (13:07 -0700)]
Merge branch 'clk-hw-unregister-fixed-rate' into clk-next

* clk-hw-unregister-fixed-rate:
  clk: fixed-rate: add clk_hw_unregister_fixed_rate()

8 years agoclk: fixed-rate: add clk_hw_unregister_fixed_rate()
Masahiro Yamada [Sun, 22 May 2016 05:33:35 +0000 (14:33 +0900)]
clk: fixed-rate: add clk_hw_unregister_fixed_rate()

This will be used to migrate to the clk_hw APIs.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
8 years agoclk: hisilicon: hi3519: add driver remove path and fix some issues
Jiancheng Xue [Wed, 15 Jun 2016 06:26:38 +0000 (14:26 +0800)]
clk: hisilicon: hi3519: add driver remove path and fix some issues

1. Add driver remove path.
2. Fix some issues.
   -Fix the ordering issue about clock provider being published.
   -Add error checking upon registering clocks.

Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
8 years agoclk: hisilicon: add hisi_clk_unregister_* functions
Jiancheng Xue [Wed, 15 Jun 2016 06:26:37 +0000 (14:26 +0800)]
clk: hisilicon: add hisi_clk_unregister_* functions

Add hisi_clk_unregister_* functions.

Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
8 years agoclk: hisilicon: add error processing for hisi_clk_register_* functions
Jiancheng Xue [Wed, 15 Jun 2016 06:26:36 +0000 (14:26 +0800)]
clk: hisilicon: add error processing for hisi_clk_register_* functions

Add error processing for hisi_clk_register_* functions.

Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
8 years agoclk: hisilicon: add hisi_clk_alloc function.
Jiancheng Xue [Wed, 15 Jun 2016 06:26:35 +0000 (14:26 +0800)]
clk: hisilicon: add hisi_clk_alloc function.

Before, there was an ordering issue that the clock provider
had been published in hisi_clk_init before it could provide
valid clocks to consumers. hisi_clk_alloc is just used to
allocate memory space for struct hisi_clock_data. It makes
it possible to publish the provider after the clocks are ready.

Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
8 years agoreset: hisilicon: change the definition of hisi_reset_init
Jiancheng Xue [Wed, 15 Jun 2016 06:26:34 +0000 (14:26 +0800)]
reset: hisilicon: change the definition of hisi_reset_init

Change the input arguments type to struct platform_device pointer.

Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
8 years agoclk: s2mps11: Migrate to clk_hw based OF and registration APIs
Stephen Boyd [Wed, 1 Jun 2016 23:15:24 +0000 (16:15 -0700)]
clk: s2mps11: Migrate to clk_hw based OF and registration APIs

Now that we have clk_hw based provider APIs to register clks, we
can get rid of struct clk pointers while registering clks in
these drivers, allowing us to move closer to a clear split of
consumer and provider clk APIs.

Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org>
Acked-by: Andi Shyti <andi.shyti@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
8 years agoclk: stm32f4: Migrate to clk_hw based OF and registration APIs
Stephen Boyd [Wed, 1 Jun 2016 23:15:29 +0000 (16:15 -0700)]
clk: stm32f4: Migrate to clk_hw based OF and registration APIs

Now that we have clk_hw based provider APIs to register clks, we
can get rid of struct clk pointers while registering clks in
these drivers, allowing us to move closer to a clear split of
consumer and provider clk APIs.

Cc: Daniel Thompson <daniel.thompson@linaro.org>
Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
8 years agoclk: bcm: iproc: Migrate to clk_hw based registration and OF APIs
Stephen Boyd [Wed, 1 Jun 2016 23:15:04 +0000 (16:15 -0700)]
clk: bcm: iproc: Migrate to clk_hw based registration and OF APIs

Now that we have clk_hw based provider APIs to register clks, we
can get rid of struct clk pointers while registering clks in
these drivers, allowing us to move closer to a clear split of
consumer and provider clk APIs.

Cc: Jon Mason <jonmason@broadcom.com>
Cc: Simran Rai <ssimran@broadcom.com>
Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org>
Tested-by: Ray Jui <rjui@broadcom.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
8 years agoclk: u300: Migrate to clk_hw based registration APIs
Stephen Boyd [Wed, 1 Jun 2016 23:15:31 +0000 (16:15 -0700)]
clk: u300: Migrate to clk_hw based registration APIs

Now that we have clk_hw based provider APIs to register clks, we
can get rid of struct clk pointers while registering clks in
these drivers, allowing us to move closer to a clear split of
consumer and provider clk APIs.

Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
8 years agoclk: nomadik: Migrate to clk_hw based OF and registration APIs
Stephen Boyd [Wed, 1 Jun 2016 23:15:19 +0000 (16:15 -0700)]
clk: nomadik: Migrate to clk_hw based OF and registration APIs

Now that we have clk_hw based provider APIs to register clks, we
can get rid of struct clk pointers while registering clks in
these drivers, allowing us to move closer to a clear split of
consumer and provider clk APIs.

Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
8 years agoclk: highbank: Migrate to clk_hw based registration and OF APIs
Stephen Boyd [Wed, 1 Jun 2016 23:15:02 +0000 (16:15 -0700)]
clk: highbank: Migrate to clk_hw based registration and OF APIs

Now that we have clk_hw based provider APIs to register clks, we
can get rid of struct clk pointers in this driver, allowing us to
move closer to a clear split of consumer and provider clk APIs.

Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
8 years agoMerge branch 'clk-st-critical' into clk-next
Stephen Boyd [Thu, 30 Jun 2016 19:19:22 +0000 (12:19 -0700)]
Merge branch 'clk-st-critical' into clk-next

* clk-st-critical:
  clk: st: clkgen-pll: Detect critical clocks
  clk: st: clkgen-fsyn: Detect critical clocks
  clk: st: clk-flexgen: Detect critical clocks

8 years agoclk: st: clkgen-pll: Detect critical clocks
Lee Jones [Tue, 7 Jun 2016 11:19:27 +0000 (12:19 +0100)]
clk: st: clkgen-pll: Detect critical clocks

Utilise the new Critical Clock infrastructure to mark clocks which
much not be disabled as CRITICAL.

Clocks are marked as CRITICAL using clk flags.  This patch also
ensures flags are peculated through the framework in the correct
manner.

Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
8 years agoclk: st: clkgen-fsyn: Detect critical clocks
Lee Jones [Tue, 7 Jun 2016 11:19:26 +0000 (12:19 +0100)]
clk: st: clkgen-fsyn: Detect critical clocks

Utilise the new Critical Clock infrastructure to mark clocks which
much not be disabled as CRITICAL.

Clocks are marked as CRITICAL using clk flags.  This patch also
ensures flags are peculated through the framework in the correct
manner.

Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
8 years agoclk: st: clk-flexgen: Detect critical clocks
Lee Jones [Tue, 7 Jun 2016 11:19:25 +0000 (12:19 +0100)]
clk: st: clk-flexgen: Detect critical clocks

Utilise the new Critical Clock infrastructure to mark clocks which
much not be disabled as CRITICAL.

While we're at it, reduce the coverage of the flex_flags variable,
since it's only really used in a single for() loop.

Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
8 years agoMerge branch 'clk-hi6220-rtc' into clk-next
Stephen Boyd [Thu, 30 Jun 2016 19:14:50 +0000 (12:14 -0700)]
Merge branch 'clk-hi6220-rtc' into clk-next

* clk-hi6220-rtc:
  clk: hi6220: Add RTC clock for pl031

8 years agoclk: hi6220: Add RTC clock for pl031
Zhangfei Gao [Thu, 30 Jun 2016 00:48:44 +0000 (17:48 -0700)]
clk: hi6220: Add RTC clock for pl031

Adds clk support for the pl031 RTC on hi6220

Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Wei Xu <xuwei5@hisilicon.com>
Cc: Guodong Xu <guodong.xu@linaro.org>
Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
[jstultz: Forward ported, tweaked commit description]
Signed-off-by: John Stultz <john.stultz@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
8 years agoclk: tegra: Initialize UTMI PLL when enabling PLLU
Andrew Bresticker [Thu, 26 May 2016 16:41:31 +0000 (12:41 -0400)]
clk: tegra: Initialize UTMI PLL when enabling PLLU

Move the UTMI PLL initialization code form clk-tegra<chip>.c files into
clk-pll.c. UTMI PLL was being configured and set in HW control right
after registration. However, when the clock init_table is processed and
child clks of PLLU are enabled, it will call in and enable PLLU as
well, and initiate SW enabling sequence even though PLLU is already in
HW control. This leads to getting UTMIPLL stuck with a SEQ_BUSY status.

Doing the initialization once during pllu_enable means we configure it
properly into HW control.

A side effect of the commonization/localization of the UTMI PLL init
code, is that it corrects some errors that were present for earlier
generations. For instance, in clk-tegra124.c, it used to have:

    #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 6)

when the correct shift to use is present in the new version:

    #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27)

which matches the Tegra124 TRM register definition.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
[rklein: Merged in some later fixes for potential deadlocks]
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
[treding: coding style bike-shedding, remove unused variable]
Signed-off-by: Thierry Reding <treding@nvidia.com>
8 years agoMerge 'clk-notify' into clk-next
Stephen Boyd [Wed, 29 Jun 2016 17:54:13 +0000 (10:54 -0700)]
Merge 'clk-notify' into clk-next

* clk-notify:
  clk: Provide notifier stubs when !COMMON_CLK

8 years agoMerge tag 'clk-renesas-for-v4.8-tag2' of git://git.kernel.org/pub/scm/linux/kernel...
Stephen Boyd [Wed, 29 Jun 2016 17:53:31 +0000 (10:53 -0700)]
Merge tag 'clk-renesas-for-v4.8-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next

Pull second batch of Renesas clk driver updates from Geert
Uytterhoeven:

  - Add support for R-Car V2H,
  - Add FDP1, DRIF, and thermal clocks on R-Car H3,
  - Correct a wrong parent clock.

* tag 'clk-renesas-for-v4.8-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: renesas: r8a7795: Add THS/TSC clock
  clk: renesas: r8a7795: Add DRIF clock
  clk: renesas: r8a7795: Correct lvds clock parent
  clk: renesas: r8a7795: Provide FDP1 clocks
  clk: renesas: Add R8A7792 support
  clk: renesas: mstp: Document R8A7792 support
  clk: renesas: rcar-gen2: Document R8A7792 support

8 years agoclk: Provide notifier stubs when !COMMON_CLK
Krzysztof Kozlowski [Tue, 28 Jun 2016 11:25:04 +0000 (13:25 +0200)]
clk: Provide notifier stubs when !COMMON_CLK

The clk notifier symbols are hidden by COMMON_CLK.  However on some
platforms HAVE_CLK might be set while COMMON_CLK not which leads to
compile test build errors like:

$ make.cross ARCH=sh
   drivers/devfreq/tegra-devfreq.c: In function 'tegra_actmon_rate_notify_cb':
>> drivers/devfreq/tegra-devfreq.c:391:16: error: 'POST_RATE_CHANGE' undeclared (first use in this function)
     if (action != POST_RATE_CHANGE)
                   ^
   drivers/devfreq/tegra-devfreq.c: In function 'tegra_devfreq_probe':
>> drivers/devfreq/tegra-devfreq.c:654:8: error: implicit declaration of function 'clk_notifier_register' [-Werror=implicit-function-declaration]
     err = clk_notifier_register(tegra->emc_clock, &tegra->rate_change_nb);
           ^

Export the macros and data type declarations outside of COMMON_CLK ifdef
and provide stubs to fix the compile testing.

Reported-by: kbuild test robot <lkp@intel.com>
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Tested-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
8 years agoMerge tag 'clk-renesas-for-v4.8-tag1' of git://git.kernel.org/pub/scm/linux/kernel...
Stephen Boyd [Tue, 28 Jun 2016 23:36:34 +0000 (16:36 -0700)]
Merge tag 'clk-renesas-for-v4.8-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next

Pull support for Renesas R-car M3-W from Geert Uytterhoeven:

Add initial support for the Clock Pulse Generator and Module Standby and
Software Reset modules on the Renesas R-Car M3-W SoC:
  - Basic core clocks,
  - SCIF2 (console) module clock,
  - INTC-AP (GIC) module clock.

* tag 'clk-renesas-for-v4.8-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: renesas: cpg-mssr: Add support for R-Car M3-W
  clk: renesas: cpg-mssr: Extract common R-Car Gen3 support code
  clk: renesas: Add r8a7796 CPG Core Clock Definitions
  clk: renesas: cpg-mssr: Document r8a7796 support

8 years agoclk: qcom: Remove gcc_aggre1_pnoc_ahb_clk from msm8996
Stephen Boyd [Tue, 21 Jun 2016 22:53:14 +0000 (15:53 -0700)]
clk: qcom: Remove gcc_aggre1_pnoc_ahb_clk from msm8996

This clk is critical to operation of the SoC and should never be
turned off. Furthermore, there are no consumers of this clk so
let's just delete it so things like eMMC work.

Reported-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Fixes: b1e010c0730a ("clk: qcom: Add MSM8996 Global Clock Control (GCC) driver")
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
8 years agoclk: tegra: Micro-optimize Tegra210 clock setup
Thierry Reding [Thu, 23 Jun 2016 10:52:31 +0000 (12:52 +0200)]
clk: tegra: Micro-optimize Tegra210 clock setup

sor_safe being the parent of the dpaux and dpaux1 clocks, it's not only
natural, but also slightly more efficient, to initialize it before its
children. This avoids orphaning the dpaux and dpaux1 clocks only to get
them reparented when the sor_safe clock is registered.

Acked-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
8 years agoclk: tegra: Make sor_safe the parent of dpaux and dpaux1
Thierry Reding [Thu, 23 Jun 2016 10:52:30 +0000 (12:52 +0200)]
clk: tegra: Make sor_safe the parent of dpaux and dpaux1

It turns out that sor_safe, rather than pll_p, is the parent of the
dpaux and dpaux1 clocks.

Acked-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
8 years agoMerge remote-tracking branch 'clk/clk-s905' into clk-next
Michael Turquette [Thu, 23 Jun 2016 01:20:12 +0000 (18:20 -0700)]
Merge remote-tracking branch 'clk/clk-s905' into clk-next

8 years agoclk: gxbb: add AmLogic GXBB clk controller driver
Michael Turquette [Mon, 23 May 2016 22:44:26 +0000 (15:44 -0700)]
clk: gxbb: add AmLogic GXBB clk controller driver

The gxbb clock controller is the primary clock generation unit for the
AmLogic GXBB SoC. It is clocked by a fixed 24MHz xtal, contains several
PLLs and the usual post-dividers, muxes, dividers and leaf gates that
are fed into various IP blocks in the SoC.

Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
8 years agoclk: gxbb: Document bindings for the GXBB clock controller
Michael Turquette [Thu, 9 Jun 2016 23:20:47 +0000 (16:20 -0700)]
clk: gxbb: Document bindings for the GXBB clock controller

Add documentations for the clock controller.

Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
8 years agoclk: meson: fractional pll support
Michael Turquette [Tue, 7 Jun 2016 01:08:15 +0000 (18:08 -0700)]
clk: meson: fractional pll support

Fractional MPLLs are a superset of the existing AmLogic MPLLs. They add
in a couple of new bitfields for further dividing the clock rate to
achieve rates with fractional hertz.

Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
8 years agoclk: meson: add mpll support
Michael Turquette [Tue, 7 Jun 2016 06:16:17 +0000 (23:16 -0700)]
clk: meson: add mpll support

MPLLs are adjustable rate clocks derived from PLLs. On both Meson8b and
GXBB they appear to be only derived from fixed_pll.

Add support for these clock types so that they can be added to their
respective drivers.

Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
8 years agoclk: meson: add peripheral gate macro
Michael Turquette [Tue, 7 Jun 2016 23:00:55 +0000 (16:00 -0700)]
clk: meson: add peripheral gate macro

There are a series of peripheral and system gate clocks that fan out
from the clk81 signal. Add a helper macro to statically initialize these
gate clocks.

Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
8 years agoclk: meson: only build selected platforms
Michael Turquette [Mon, 23 May 2016 21:29:13 +0000 (14:29 -0700)]
clk: meson: only build selected platforms

Break the AmLogic clock code up so that only the necessary parts are
compiled and linked. The core code is selected by both arm and arm64
builds with COMMON_CLK_AMLOGIC. The individual drivers have their own
config options as well.

Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
8 years agoclk: meson8b: convert to platform_driver
Michael Turquette [Wed, 11 May 2016 18:11:18 +0000 (11:11 -0700)]
clk: meson8b: convert to platform_driver

This patch creates a proper platform_driver for the meson8b clock
controller. Use of CLK_OF_DECLARE is removed, and can be added back in
later if very early registration of some clocks is required.

Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
8 years agoclk: meson8b: clean up composite clocks
Michael Turquette [Thu, 28 Apr 2016 19:01:51 +0000 (12:01 -0700)]
clk: meson8b: clean up composite clocks

Remove the composite clock registration function and helpers. Replace
unnecessary configuration struct with static initialization of the
desired clock type.

To preserve git bisect this patch also flips the switch and starts using
of_clk_add_hw_provider instead of the deprecated meson_clk_register_clks
method. As a byproduct clk.c can be deleted.

Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
8 years agoclk: meson8b: remove mali clk
Michael Turquette [Thu, 5 May 2016 14:56:42 +0000 (07:56 -0700)]
clk: meson8b: remove mali clk

This clock is undocumented and always orphaned. Get rid of it until we
have more complete clock tree documentation.

Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
8 years agoclk: meson8b: clean up cpu clocks
Michael Turquette [Sat, 30 Apr 2016 19:47:36 +0000 (12:47 -0700)]
clk: meson8b: clean up cpu clocks

Remove the cpu clock registration function and helpers. Replace
unnecessary configuration struct with static initialization of the
desired clock type.

Ninja rename a5_clk to cpu_clk to better align with cpufreq convention.

Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
8 years agoclk: meson8b: clean up fixed factor clocks
Michael Turquette [Thu, 28 Apr 2016 19:01:58 +0000 (12:01 -0700)]
clk: meson8b: clean up fixed factor clocks

Remove the fixed factor registration function and helpers. Replace
unnecessary configuration struct with static initialization of the
desired clock type.

Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
8 years agoclk: meson8b: clean up pll clocks
Michael Turquette [Thu, 28 Apr 2016 19:01:42 +0000 (12:01 -0700)]
clk: meson8b: clean up pll clocks

Remove the pll registration function and helpers. Replace unnecessary
configuration struct with static initialization of the desired clock
type.

Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
8 years agoclk: meson8b: clean up fixed rate clocks
Michael Turquette [Thu, 28 Apr 2016 19:00:52 +0000 (12:00 -0700)]
clk: meson8b: clean up fixed rate clocks

Remove the fixed_rate registration function and helpers from clkc.[ch].
Replace unnecessary configuration struct with static initialization of
the desired clock type.

While we're here, begin the transition to a proper platform_driver and
call of_clk_add_hw_provider with a shiny new struct clk_hw_onecell_data.

Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
8 years agoclk: meson8b: rectify reg offsets with datasheet
Michael Turquette [Fri, 29 Apr 2016 00:18:52 +0000 (17:18 -0700)]
clk: meson8b: rectify reg offsets with datasheet

The register offsets in the data sheet are confusing. Document them more
thoroughly.

Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
8 years agoclk: tegra: Mark timer clock as critical
Thierry Reding [Tue, 21 Jun 2016 15:30:35 +0000 (17:30 +0200)]
clk: tegra: Mark timer clock as critical

The timer clock feeds the timer block, which, among other things, is
used to drive the SOR lane sequencer. Since the Tegra timer driver is
not enabled on 64-bit ARM, nothing currently claims that clock and it
gets disabled by the common clock framework at late_init time.

Given the non-obvious dependencies, the timer clock can be considered
a critical part of the SoC infrastructure, requiring its clock source
to be always on.

Acked-by: Rhyland Klein <rklein@nvidia.com>
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
8 years agoclk: rockchip: fix incorrect rk3228 clock registers
Xing Zheng [Tue, 21 Jun 2016 04:53:27 +0000 (12:53 +0800)]
clk: rockchip: fix incorrect rk3228 clock registers

Due to copy and paste carelessly, RK3288_CLKxxx references are incorrect,
we need to fix them.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
8 years agoclk: rockchip: add clock-ids for rk3228 MAC clocks
Xing Zheng [Tue, 21 Jun 2016 04:59:47 +0000 (12:59 +0800)]
clk: rockchip: add clock-ids for rk3228 MAC clocks

This patch exports related MAC clocks for dts reference.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
8 years agoclk: rockchip: add clock-ids for rk3228 audio clocks
Xing Zheng [Tue, 21 Jun 2016 04:53:29 +0000 (12:53 +0800)]
clk: rockchip: add clock-ids for rk3228 audio clocks

This patch exports related i2s/spdif clocks for dts reference.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
8 years agoclk: renesas: r8a7795: Add THS/TSC clock
Khiem Nguyen [Sun, 19 Jun 2016 02:34:18 +0000 (09:34 +0700)]
clk: renesas: r8a7795: Add THS/TSC clock

Signed-off-by: Khiem Nguyen <khiem.nguyen.xt@rvc.renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
8 years agoclk: renesas: r8a7795: Add DRIF clock
Ramesh Shanmugasundaram [Fri, 17 Jun 2016 12:25:14 +0000 (13:25 +0100)]
clk: renesas: r8a7795: Add DRIF clock

This patch adds DRIF module clocks for r8a7795 SoC.

Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
8 years agoclk: renesas: r8a7795: Correct lvds clock parent
Geert Uytterhoeven [Fri, 10 Jun 2016 07:36:44 +0000 (09:36 +0200)]
clk: renesas: r8a7795: Correct lvds clock parent

According to the latest information, the parent clock of the LVDS module
clock is the S0D4 clock, not the S2D1 clock.

Note that this change has no influence on actual operation, as the
rcar-du LVDS encoder driver doesn't use the parent clock's rate.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>