Wu, Josh [Mon, 19 Jan 2015 07:25:56 +0000 (15:25 +0800)]
ARM: at91: mmc portA support is only for at91sam9g20ek_2mmc board
Current the MMC support will enable MCI port A, Which is only exist
for 2mmc board.
So by default we need to disable MMC (port A) support. And only enable
it for 2mmc board. Otherwise, dataflash won't work in at91sam9260ek board
as MMC has confliction with Dataflash in the CLK pin.
Bo Shen [Fri, 16 Jan 2015 02:55:46 +0000 (10:55 +0800)]
ARM: atmel: cleanup: remove at91cap9 related code
As the at91cap9adk board is removed by commit: b5508344
(ARM: remove broken "at91cap9adk" board), so the at91cap9
code is not used anymore, and also the document for
at91cap9 can not be found on www.atmel.com, so remove the
at91cap9 related code.
Signed-off-by: Bo Shen <voice.shen@atmel.com> Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>
Bo Shen [Mon, 15 Dec 2014 05:24:29 +0000 (13:24 +0800)]
ARM: atmel: sama5: add sfr register header file
The SFR (special function registers) can be shared bwteen
sama5d3 and sama5d4 soc.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
[whitespace adoptions for 80 char compliance] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Bo Shen [Mon, 15 Dec 2014 05:24:28 +0000 (13:24 +0800)]
ARM: atmel: sama5: add bus matrix header file
This matrix header file can be shared between sama5d3 and sama5d4 soc.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
[whitespace adaptions for 80 char compliance] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Bin Meng [Wed, 4 Feb 2015 08:26:12 +0000 (16:26 +0800)]
x86: Add SPI support to quark/galileo
The Quark SoC contains a legacy SPI controller in the legacy bridge
which is ICH7 compatible. Like Tunnel Creek and BayTrail, the BIOS
control register offset in the ICH SPI driver is wrong for the Quark
SoC too, unprotect_spi_flash() is added to enable the flash write.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Wed, 4 Feb 2015 08:26:10 +0000 (16:26 +0800)]
x86: galileo: Add GPIO support
Quark SoC has a legacy GPIO block in the legacy bridge (D0:F31),
which is just the same one found in other x86 chipset. Since we
programmed the GPIO register block base address, we should be
able to enable the GPIO support on Intel Galileo board.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Wed, 4 Feb 2015 08:26:09 +0000 (16:26 +0800)]
x86: quark: Initialize non-standard BARs
Quark SoC has some non-standard BARs (excluding PCI standard BARs)
which need be initialized with suggested values. This includes GPIO,
WDT, RCBA, PCIe ECAM and some ACPI register block base addresses.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Thu, 5 Feb 2015 15:42:21 +0000 (23:42 +0800)]
x86: quark: Bypass TSC calibration
For some unknown reason, the TSC calibration via PIT does not work on
Quark. Enable bypassing TSC calibration and override TSC_FREQ_IN_MHZ
to 400 per Quark datasheet in the Kconfig.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Mon, 2 Feb 2015 14:35:26 +0000 (22:35 +0800)]
x86: quark: Add Cache-As-RAM initialization
Quark SoC contains an embedded 512KiB SRAM (eSRAM) that is
initialized by hardware. eSRAM is the ideal place to be used
for Cache-As-RAM (CAR) before system memory is available.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Mon, 2 Feb 2015 14:35:25 +0000 (22:35 +0800)]
x86: Define macros for pci configuration space access
Move PCI_REG_ADDR and PCI_REG_DATA from arch/x86/lib/pci_type1.c to
arch/x86/include/asm/pci.h, also define PCI_CFG_EN so that these
macros can be used for pci configuration space access.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Mon, 2 Feb 2015 14:35:24 +0000 (22:35 +0800)]
x86: quark: Add routines to access message bus registers
In the Quark SoC, some chipset commands are accomplished by utilizing
the internal message network within the host bridge (D0:F0). Accesses
to this network are accomplished by populating the message control
register (MCR), Message Control Register eXtension (MCRX) and the
message data register (MDR).
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Simon Glass [Wed, 28 Jan 2015 05:13:47 +0000 (22:13 -0700)]
x86: Add support for Intel Minnowboard Max
This is a relatively low-cost x86 board in a small form factor. The main
peripherals are uSD, USB, HDMI, Ethernet and SATA. It uses an Atom 3800
series CPU. So far only the dual core 2GB variant is supported.
This uses the existing FSP support. Binary blobs are required to make this
board work. The microcode update is included as a patch (all 3000 lines of
it).
Change-Id: I0088c47fe87cf08ae635b343d32c332269062156 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Wed, 28 Jan 2015 05:13:44 +0000 (22:13 -0700)]
scsi: bootstage: Measure time taken to scan the bus
On some hardware this time can be significant. Add bootstage support for
measuring this. The result can be obtained using 'bootstage report' or
passed on to the Linux via the device tree.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Wed, 28 Jan 2015 05:13:42 +0000 (22:13 -0700)]
x86: Allow a UART to be set up before the FSP is ready
Since the FSP is a black box it helps to have some sort of debugging
available to check its inputs. If the debug UART is in use, set it up
after CAR is available.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Wed, 28 Jan 2015 05:13:39 +0000 (22:13 -0700)]
x86: mmc: Move common FSP functions into a common file
Since these board functions seem to be the same for all boards which use
FSP, move them into a common file. We can adjust this later if future FSPs
need more flexibility.
This creates a generic PCI MMC device.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
Stefan Roese [Mon, 19 Jan 2015 10:33:40 +0000 (11:33 +0100)]
arm: mvebu: drivers/ddr: Add DDR3 driver with training code from Marvell bin_hdr
This patch adds the DDR3 setup and training code taken from the Marvell
U-Boot repository. This code used to be included as a binary (bin_hdr)
into the AXP boot image. Not linked with the main U-Boot. With this code
addition and the following serdes/PHY setup code, the Armada-XP support
in mainline U-Boot is finally self-contained. So the complete image
for booting can be built from mainline U-Boot. Without any additional
external inclusion. Hopefully other MVEBU SoC's will follow here.
Support for some SoC's has been removed in this version. This is:
MV_MSYS:
The code referred to by the MV_MSYS define is currently unused. And its
not really planned to support this in mainline. So lets remove it to
make the code clearer and increase the readability.
MV88F68XX (A38x):
The code referred to by the MV88F68XX define (A38x) is currently unused.
And its partial and not sufficient for this device in this stage.
So lets remove it to make the code clearer and increase the readability.
MV88F66XX (ALP):
The code referred to by the MV88F66XX define is currently unused. And its
not really planned to support this in mainline. So lets remove it to
make the code clearer and increase the readability.
MV88F78X60_Z1:
The code referred to by the MV88F78X60_Z1 define is currently unused. As the
Z1 revision of the AXP is not supported in mainline anymore.
So lets remove it to make the code clearer and increase the readability.
Remove support for Z1 & A0 AXP revisions (steppings). The current stepping
is B0 and this is the only one that is actively supported in this code
version.
Tested on AXP using a SPD DIMM setup on the Marvell DB-MV784MP-GP board and
on a custom fixed DDR configuration board (maxbcm).
Note:
This code has undergone many hours of coding-style cleanup and refactoring.
It still is not checkpatch clean though, I'm afraid. As the factoring of the
code has so many levels of indentation that many lines are longer than 80
chars. This might be some task to tackly later on.
Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Luka Perkov <luka.perkov@sartura.hr>
Stefan Roese [Mon, 19 Jan 2015 10:33:41 +0000 (11:33 +0100)]
arm: mvebu: Add Serdes PHY config code
This code is ported from the Marvell bin_hdr code into mainline
SPL U-Boot. It needs to be executed very early so that the devices
connected to the serdes PHY are configured correctly.
Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Luka Perkov <luka.perkov@sartura.hr>
Stefan Roese [Mon, 19 Jan 2015 10:33:42 +0000 (11:33 +0100)]
arm: armada-xp: Add SPL support used to include the DDR training code
This patch adds SPL support to the Marvell Armada-XP. With this addition
the bin_hdr integration is not needed any more. The SPL will first
initialize the serdes/PHY and the call the DDR setup and training code
now integrated into mainline U-Boot.
Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Luka Perkov <luka.perkov@sartura.hr>
Stefan Roese [Mon, 19 Jan 2015 10:33:44 +0000 (11:33 +0100)]
tools: kwbimage: Support u-boot.img padding to CONFIG_SYS_SPI_U_BOOT_OFFS
This is used on the AXP boards, to pad u-boot.img to the desired offset in
SPI flash (only this boot target supported right now). This offset is
used by the SPL then to load u-boot.img into SDRAM and execute it there.
Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Luka Perkov <luka.perkov@sartura.hr>
Stefan Roese [Mon, 19 Jan 2015 10:33:47 +0000 (11:33 +0100)]
arm: maxbcm: Enable SPL to include DDR training code into U-Boot
This patch adds SPL support to the maxbcm MV78460 based board. Including
the fixed DDR configuratrion needed for the DDR training code. And the
the serdes PHY init code.
Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Luka Perkov <luka.perkov@sartura.hr>
Stefan Roese [Mon, 19 Jan 2015 10:33:48 +0000 (11:33 +0100)]
arm: mvebu: Placeholder bin_hdr file can now be removed
With this patchset the Marvell bin_hdr (DDR training) code is intergrated
into mainline U-Boot. We can remove the placeholder file again, which was
only introduced to make U-Boot compile and link again.
Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Luka Perkov <luka.perkov@sartura.hr>
Masahiro Yamada [Thu, 5 Feb 2015 05:42:58 +0000 (14:42 +0900)]
ARM: UniPhier: do not compile unnecessary objects
It is true that unused functions are removed from the ELF image
by the compiler's garbage collection but relying on it too much
does not look nice.
Currently, the build is taking more than it should.
Refactor the makefiles to compile only files that are really needed.
CONFIG_SOC_INIT and CONFIG_DRAM_INIT are no longer needed by the
optimization.
Since commit 0365ffcc0bd6 (generic-board: show model name in
board_init_f() too), checkboard() is invoked only when
show_board_info() fails to get the model name from Device Tree.
It never happens because UniPhier SoCs now only work with
CONFIG_OF_CONTROL and all the root nodes of UniPhier device trees
have the "model" property.
Masahiro Yamada [Thu, 5 Feb 2015 05:42:56 +0000 (14:42 +0900)]
ARM: UniPhier: revive support card info
Since commit 0365ffcc0bd6 (generic-board: show model name in
board_init_f() too), the support card information has not been
displayed because check_support_card() is invoked only when
show_board_info() fails to get the model name from Device Tree.
This commit adds misc_init_f() function to call check_support_card()
from there.
Masahiro Yamada [Thu, 5 Feb 2015 05:30:25 +0000 (14:30 +0900)]
ARM: UniPhier: move EEPROM device node into a separate DTS
This EEPROM chip is installed on the expansion board commonly used
on UniPhier platform. To avoid duplicated description, move the
EEPROM node to a separate file and include it from other device tree
sources.
Simon Glass [Wed, 28 Jan 2015 05:13:37 +0000 (22:13 -0700)]
x86: Adjust the FSP types slightly
To avoid casts, find_fsp_header() should return a pointer. Add asmlinkage
to two API functions which use that convention. UPD_TERMINATOR is common
so move it into a common file.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Wed, 28 Jan 2015 05:13:26 +0000 (22:13 -0700)]
x86: Enhance the microcode tool to support header files as input
Sometimes microcode is delivered as a header file. Allow the tool to
support this as well as collecting multiple microcode blocks into a
single update.
Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Fri, 30 Jan 2015 19:04:56 +0000 (12:04 -0700)]
arm: Show relocated PC/LR in the register dump
If we don't know the relocation address, the raw values are not very useful.
Show the pre-relocation values as well as these can be looked up in
System.map, etc.
Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Heiko Schocher [Tue, 20 Jan 2015 09:06:18 +0000 (10:06 +0100)]
arm, imx6, aristainetos: board updates
- use linux display timing settings
- change backlight duty cycle 500ns
- some defaultenvironment changes
- change fit_addr_r to 0x14000000 as needed if
MAX_LOCKDEP_SUBCLASSES in linux gets increased.
- Environment now at 0xd0000 in nand flash
Nikita Kiryanov [Wed, 14 Jan 2015 08:42:54 +0000 (10:42 +0200)]
common: convert compulab splash load code to common code
Move board/compulab/common/splash.c code to
common/splash_source.c to make it available for everybody. This move
renames cl_splash_screen_prepare() to splash_source_load(), and
the compilation of this code is conditional on CONFIG_SPLASH_SOURCE.
splash_source features:
* Provide a standardized way for declaring board specific splash screen
locations
* Provide existing routines for auto loading the splash image from the
locations as declared by the board
* Introduce the "splashsource" environment variable, which makes it
possible to select the splash image source.
cm-t35 and cm-fx6 are updated to use the modified version.
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Cc: Stefano Babic <sbabic@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Anatolij Gustschin <agust@denx.de> Reviewed-by: Tom Rini <trini@ti.com> Acked-by: Igor Grinberg <grinberg@compulab.co.il>
projects / karo-tx-uboot.git / log