Robin Gong [Sat, 11 Aug 2012 09:41:52 +0000 (17:41 +0800)]
ENGR00220154 GPT mx6: move mx6_timer_rate to clock.c
System will report oops as below. To fix it we will move mx6_timer_rate to
clock.c, so that we can avoid use clk_get_sys which cause schedule after
spin_lock.
oops log:
BUG: scheduling while atomic: kinteractiveup/1403/0x00000002
Modules linked in:
(unwind_backtrace+0x0/0xfc) from [<804f05f0>] (__schedule+0x4b8/0x6b0)
(__schedule+0x4b8/0x6b0) from [<804f12ac>] (__mutex_lock_slowpath+0x138/0x208)
(__mutex_lock_slowpath+0x138/0x208) from [<804f13b4>] (mutex_lock+0x38/0x3c)
mutex_lock+0x38/0x3c) from [<803b9134>] (clk_get_sys+0x1c/0xec)
(clk_get_sys+0x1c/0xec) from [<8005f814>] (mx6_timer_rate+0x14/0x7c)
(mx6_timer_rate+0x14/0x7c) from [<80056a20>] (_clk_gpt_get_rate+0x18/0x2c)
(_clk_gpt_get_rate+0x18/0x2c) from [<8005e89c>] (clk_get_rate+0x34/0x40)
(clk_get_rate+0x34/0x40) from [<80055f3c>] (_clk_pll_enable+0xa8/0x1ec)
(_clk_pll_enable+0xa8/0x1ec) from [<80056088>] (_clk_pll1_enable+0x8/0x20)
(_clk_pll1_enable+0x8/0x20) from [<80056998>] (_clk_arm_set_rate+0x278/0x2e8)
(_clk_arm_set_rate+0x278/0x2e8) from [<8005e824>] (clk_set_rate+0x54/0x68)
(clk_set_rate+0x54/0x68) from [<80061660>] (set_cpu_freq+0xb8/0x160)
(set_cpu_freq+0xb8/0x160) from [<800618b4>] (mxc_set_target+0xf0/0x20c)
(mxc_set_target+0xf0/0x20c) from [<80372388>](__cpufreq_driver_target+0x54/0x60) Signed-off-by: Robin Gong <b38343@freescale.com>
Robin Gong [Sat, 11 Aug 2012 08:36:35 +0000 (16:36 +0800)]
ENGR00220153 cpufreq mx6: new cpu set point and add VDDSOC/PU adjust
1.add new cpu setpoint: replace 498Mhz with 672Mhz,and remove 198Mhz.
but now 498Mhz seems not stable enough, comment now, test enough to
add it. Rigel kept unchange now.
2.support adjusting VDDSOC/VDDPU when cpu frequency change.
Steve Cornelius [Thu, 9 Aug 2012 22:26:33 +0000 (15:26 -0700)]
ENGR00216259 caam: improve RNG4 initialization process
Early versions of this driver used a set of entropy generation parameters
inherited from QorIQ devices. Those parameters were a hardcoded set
based upon internally-suggested values, and worked well on QorIQ. However,
for certain mx6 devices, oscillator values were found to be exceeding
the upper limit, and so RNG instantiation was failing in those cases.
This code improves initialization by (a) making sure the oscillator
divider is set to a known value, and (b) converting the parameter selection
to a symbolic compiler-generated form, instead of using embedded
magic number constants.
The calculation is now based on the definition of RNG4_ENT_CLOCKS_SAMPLE,
which defaults to 1600 unless overridden by something. The lower limit
is then set as /4, and the upper limit set to *8.
Tested-by: Minnick Michael-B21710 <b21710@freescale.com> Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com> Signed-off-by: Jason Liu <r64343@freescale.com>
Anson Huang [Thu, 9 Aug 2012 16:35:59 +0000 (00:35 +0800)]
ENGR00220022 [MX6]Add necessary protection to bus freq variables and function
All bus freq related variables and function calls need to be protected by
mutex, or these variables may be wrong and result in triggering bus freq
change by mistake, it will impact many modules function.
Anson Huang [Thu, 9 Aug 2012 12:49:36 +0000 (20:49 +0800)]
ENGR00219870 [MX6]Add interrupt check to idle to minish SMP impact
CPUs may be waked up by SMP broadcast, and for this scenario, CPUs
can enter idle again directly to avoid run a long way to re-enter
idle, adding this interrupt check can minish SMP impact on peripheral
devices' performance.
Fugang Duan [Thu, 9 Aug 2012 09:59:44 +0000 (17:59 +0800)]
ENGR00180288 - FEC : Fix kernel dump about eth0
Kernel dump when do wifi stress test with suspend and resume as below:
eth0: tx queue full!.
remove wake up source irq 103
PM: resume of devices complete after 348.934 msecs
Restarting tasks ... done.
------------[ cut here ]------------
WARNING: at net/sched/sch_generic.c:255 dev_watchdog+0x284/0x2a8()
NETDEV WATCHDOG: eth0 (fec): transmit queue 0 timed out
Modules linked in: ar6000
[<8004482c>] (unwind_backtrace+0x0/0xf8) from
[<80068cd0>] (warn_slowpath_common+0x4c/0x64)
[<80068cd0>] (warn_slowpath_common+0x4c/0x64)from
[<80068d7c>] (warn_slowpath_fmt+0x30/0x40)
[<80068d7c>] (warn_slowpath_fmt+0x30/0x40) from
[<803f0c50>] (dev_watchdog+0x284/0x2a8)
[<803f0c50>] (dev_watchdog+0x284/0x2a8) from
[<80074430>] (run_timer_softirq+0xec/0x214)
[<80074430>] (run_timer_softirq+0xec/0x214) from
[<8006e524>] (__do_softirq+0xac/0x140)
[<8006e524>] (__do_softirq+0xac/0x140) from
[<8006ea60>] (irq_exit+0x94/0x9c)
[<8006ea60>] (irq_exit+0x94/0x9c) from
[<80039240>] (do_local_timer+0x54/0x70)
[<80039240>] (do_local_timer+0x54/0x70) from
[<8003ea0c>] (__irq_svc+0x4c/0xe8)
Exception stack(0x80a2bf68 to 0x80a2bfb0)
bf60: 0000001f80a3babc80a2bfb00000000080a2a00080a7b8e4
bf80: 804befcc80a3ee7c1000406a412fc09a000000000000000080a8144080a2bfb0
bfa0: 8003fa648003fa6860000013ffffffff
[<8003ea0c>] (__irq_svc+0x4c/0xe8) from [<8003fa68>] (default_idle+0x24/0x28)
[<8003fa68>] (default_idle+0x24/0x28) from [<8003fc60>] (cpu_idle+0xbc/0xfc)
[<8003fc60>] (cpu_idle+0xbc/0xfc) from [<80008878>] (start_kernel+0x258/0x29c)
[<80008878>] (start_kernel+0x258/0x29c) from [<10008040>] (0x10008040)
---[ end trace 30671ac42e272c2d ]---
But ethernet and system still be alive. In sometime,the issue
will cause system hang like "nfs: server 10.192.242.179 not
responding, still trying".
The root cause is tx buffer descriptors are not cleaned when
ethernet resume back.
Wayne Zou [Tue, 7 Aug 2012 11:23:13 +0000 (19:23 +0800)]
ENGR00220011-1 Revert ENGR00212529 show video to fb0, the color space incorrect
Revert ENGR00212529 MX6x show video to fb0 when bootup,
the color space incorrect.
Update IPU DP CSC setting should not change the DP FG window's position setting,
it can be update when enabling IPU DP channel.
Otherwise, it will appear NFB4EOF_ERR and flip irq timeout errors.
the original low memory killer only take care of system memory accounting,
but for so large shared memory occupy by GPU, and each process memory
killer account become unfair, very large 3D game will not killed firstly
if it going to background.
Add this account to let real large memory user get killed if going to background
eg, the "angry bird Space" will acquire 68,215,360 GPU memory for 1-6 toll-gate.
The test show it can quicker recovery from memory shortage situation,
since it's very like to be killed after add so much GPU memory for such 3D game.
Yuxi Sun [Mon, 6 Aug 2012 06:30:41 +0000 (14:30 +0800)]
ENGR00219397-1 v4l2 overlay: Add foreground overlay support based on ipu device
Replace CSI_PRP_VF_MEM channel with CSI_MEM, then using ipu device
to do the processing or directly send to framebuffer if no processing
need to be perform.
Add the foreground overlay driver file name ipu_fg_overlay_sdc.c correspondding
to the former ipu_prp_vf_sdc.c
Discard the cam->vf_rotation parametter when uing the ipu device for processing
in the overlay, share the cam->rotation parametter with pp.
Chen Liangjun [Wed, 8 Aug 2012 12:54:19 +0000 (20:54 +0800)]
ENGR00219837-1 HDMI: Add HDMI_SDMA support for RIGEL TO1.1
In RIGEL TO1.1, the same HDMI_SDMA fix is introduced as ARIK TO1.2. Add
support for RIGEL TO1.1 for HDMI_SDMA functionality.
In this patch:
1.Add hdmi_SDMA_check() interface to judge whether MX6 chip
support HDMI_SDMA.
2.Replace mx6q_version() check with hdmi_SDMA_check() to support
both ARIK To1.2 and RIGEL TO1.1.
Hongzhang Yang [Thu, 9 Aug 2012 03:00:56 +0000 (11:00 +0800)]
ENGR00217946 VPU kernel driver: fix suspend/resume i.MX6DL hang issue
Bug: VPU easily hang during suspend/resume standby mode i.MX6Q/i.MX6DL
Fix: standby mode doesn't power off/on PU but changes voltage instead, thus
VPU requires a reset cause there's always chance some cell is on
unstable state after voltage change
suspend/resume DSM is OK because it power off/on PU and probably there is a
power-on-reset sequence embedded in SOC
Signed-off-by: Hongzhang Yang <Hongzhang.Yang@freescale.com>
Fugang Duan [Mon, 6 Aug 2012 08:34:17 +0000 (16:34 +0800)]
ENGR00219501 - FEC : Enable puase frame flow
ENET pause frame has two issues (ticket TKT116501):
1. RX status fifo full.
2. XOFF has higher priority than XON when both XOFF and
XON have pending request.
Both of the issues can cause RX FIFO overruns when RX bandwidth
is over 120Mbps.
The issue has been fixed on Rigel TO1.1 and Arik TO1.2. Pause
frame has been enabled to avoid the overrun issue.
Anson Huang [Fri, 3 Aug 2012 11:28:33 +0000 (19:28 +0800)]
ENGR00219024 [EPDC]Fix EPDC resume failure.
Need to enable both axi and pix clock before doing EPDC reset,
or the hardware reset will fail, which will result in dead loop
of EPDC resume function, and block system resume.
Dong Aisheng [Fri, 3 Aug 2012 14:33:08 +0000 (22:33 +0800)]
ENGR00217318-3 flexcan: only enter stop mode when device is up
The flexcan is still in disable mode during suspend if it's still
not up. We do not need to enter stop mode if find the device is not
up since the stop mode does not work well in disable mode(remote wakeup
does not work).
Simon Glass [Thu, 19 Jan 2012 19:28:56 +0000 (11:28 -0800)]
serial: Fix wakeup init logic to speed up startup
The synchronize_rcu() call resulting from making every serial driver
wake-up capable (commit b3b708fa) slows boot down on my Tegra2x system
(with CONFIG_PREEMPT disabled).
But this is avoidable since it is the device_set_wakeup_enable() and then
subsequence disable which causes the delay. We might as well just make
the device wakeup capable but not actually enable it for wakeup until
needed.
Before this change my boot log says:
[ 0.227062] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
[ 0.702928] serial8250.0: ttyS0 at MMIO 0x70006040 (irq = 69) is a Tegra
after:
[ 0.227264] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
[ 0.227983] serial8250.0: ttyS0 at MMIO 0x70006040 (irq = 69) is a Tegra
for saving of 450ms.
Suggested-by: Rafael J. Wysocki <rjw@sisk.pl> Acked-by: Rafael J. Wysocki <rjw@sisk.pl> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> Signed-off-by: Huang Shijie <b32955@freescale.com>
Chen Liangjun [Thu, 2 Aug 2012 07:59:35 +0000 (15:59 +0800)]
ENGR00219184 HDMI AUDIO: set HDMI audio's SDMA priority to high
HDMI use SDMA for buffer switch. Set HDMI audio's SDMA priority to the
same level as other audio device. This adjust can avoid noise due to
SDMA cpu race failing.
Anson Huang [Thu, 2 Aug 2012 15:17:43 +0000 (23:17 +0800)]
ENGR00219178 [MX6]Need to avoid using GPIO_1 on latest B4 sabresd board
For the latest B4 sabresd board, GPIO_1 is connected to PRO_B, we
use this pin as battery charge_done led control, need to avoid using
this pin as GPIO for B4 board, or system will reboot when this pin's
level is changed.
Chen Liangjun [Thu, 2 Aug 2012 04:34:30 +0000 (12:34 +0800)]
ENGR00219160 SDMA: replace SDMA LOOP/NORMAL type with enum struct
For common DMA enguine, only slave_sg mode and cyclic mode is support.
However, SDMA can meet more kinds of DMA operation mode requirement. The
origin flags NORMAL and LOOP can no longer satisfy SDMA user's need.
In this patch,
1 Construct a new enum sdma_mode to declare more kind of SDMA
modes. This new variable would replace the old flags.
2 Init sdma_mode to unvalid every time allocating a SDMA channel
to avoid last SDMA channel configuration's impact.
Sandor Yu [Thu, 2 Aug 2012 03:11:31 +0000 (11:11 +0800)]
ENGR00219153 HDMI: Remove enable/disable_pins in blank/unblank function
HDMI enable/disable_pins setting HDMI DDC enable, but the pins confilct
with I2C2 bus on board design, so only HDCP function is enable
the function can been called.
Remove enable/disable_pins in blank/unblank function to make sure
I2C2 bus can work when HDCP disable.
ENGR00218810-2 [Thermal]Add thermal alarm function
1. Current thermal framework use delayed work to update
temperature, but delayed work may be blocked if system is
busy with the high priority task, which will cause the thermal
protect function not working in time, so we need to add alarm
function, when temperature reach the critical point, the alarm
function will generate an interrupt to reboot system.
2. No need to read 5 times of sensor value, read once is enough.
Chen Liangjun [Wed, 1 Aug 2012 02:42:44 +0000 (10:42 +0800)]
ENGR00218958 ESAI ASRC: fix system hang cause by accessing ASRC with no clock
In ESAI_ASRC, to use ASRC for p2p playback, ESAI driver would maintain
an variable to keep track of ASRC pair number allocated. So every time
ESAI driver want to use ASRC, he would first init the variable to a value
(0 in ESAI driver)stand for unvalid pair number and then request an valid
pair number. At last, open the ASRC clock for ASRC register access.
However, ASRC driver treat 0 as an valid pair number. Thus, if an ESAI ASRC
playback is failed, ESAI driver would check whether the pair number is valid.
If the pair number is valid, ESAI driver would access ASRC register to do some
clean work. Thus, the init 0 value would be treat as an valid pair number and
ASRC register would be access without ASRC clock. In the case, an system
hang happens.
In this patch, init pair number variable to -1 after its allocation.
ENGR00218747 - MX6Q/MX6DL: WAIT mode support for MX6QTO1.2/MX6DLTO1.1
Add the new WAIT mode workaround added for MX6Q1.2 and MX6DLTO1.1.
A new bit is added to CCM_CGPR (bit 17). This bit needs to be
enabled for the WAIT mode fix to be active and needs to be disabled
before the system enters STOP mode with power gating enabled.
Fix WAIT mode bug when system is in low power IDLE mode:
In low power IDLE mode (AHB @ 24MHz), switch ARM to run from 24MHz
on MX6QTO1.1 and MX6DLTO1.0 chips when ARM core enters WAIT mode.
We still need to use the ARM:IPG_CLK ratio of 12:5. Since IPG_CLK
is at 12MHz, we need to run ARM below 28.8MHz.
Robin Gong [Mon, 30 Jul 2012 11:21:18 +0000 (19:21 +0800)]
ENGR00218824 VPU: revert ENGR00217123 about VPU regulator
Two reason:
1. VPU regulator is not enough stable,sometimes will cause system hang
2. GPU regulator is not ready, because GPU/VPU share PU LDO, so revert
the patch firstly.
ENGR00218807 ESAI: fix bootup issue cause by accessing unexist address
To support p2p playback, ESAI driver would copy platform data to
esai_asrc struct. The platform data only exist on boards that supports
ESAI. However, for ARM2 board, it supports ESAI but not necessary
get the codec CS42888. Thus the probe() in ESAI driver would also try to
copy the platform data from board init file.
The p2p playback now only support ARD board, so the ESAI probe() for
ARM2 would access unexisted address and cause an kernel dump.
In the patch, check the platform data address before copy.
make shi [Mon, 30 Jul 2012 07:35:11 +0000 (15:35 +0800)]
ENGR00218771 mx6 USB:USB disconnect issue verification on MX6QTO1.2/MX6DLTO1.1
- for Rigel1.1/Arik1.2, bit 17 of HW_USBPHY_IP will be set, it will fix the
issue that no wakeup between SUSP/PHCD. And the usb_platform_rh_suspend/
usb_platform_rh_resume do not need do complex software workaround, only
need set/clear the workaround bit.
- for Megrez , bit 17 and bit 18 of HW_USBPHY_IP will be set, it will fix the
issue that no wakeup between SUSP/PHCD and disconnect after resume. No need
do any software workaround.
ENGR00218421-2 ESAI_ASRC:Add support for p2p virtual device playback
In the origin code, ESAI driver supoprt audio p2p playback by setting
input PCM data's sample rate thought amixer interface.It is ugly and
request user application call amixer control interface everytime before
and playback.
In this patch, user can call the audio p2p playback by writing data to
an special virtual device. Driver would automatically get the params of
input PCM. At the same time, driver would get the output sample rate and
word data. With the data abover, driver can set ASRC properly and audio
p2p palyback is support.
This patch mainly focus on:
1 clean old p2p playback way for ESAI.
2 Setup the output sample rate and word width to virtual
device's substream_runtime's private data. Everytime the virtual
device is called, the data abover is used for config ASRC, ESAI,
and codec.
ENGR00218421-1 ESAI: Setup virtual device under ESAI sound card
For ESAI sound card, ESAI driver setup device 0 for raw ESAI playback
and capture.
In this patch, add ESAI virtual device 1 under ESAI sound card. Device 1
is for ESAI audio p2p playback. Every time user use device 1 for
playback, ASRC would be called defaultly. Thus for device 1, it can
support all sample rate between 8k ~ 192k.
ENGR00218013-5 HDMI: Add SDMA to help HDMI audio support multi buffer
For chip version easily than TO1.1, HDMI use internel DMA enginue for
audio tranfer. Due to capability of HDMI module, FIFO underrun is
unavoidable.
For chip TO 1.2, introducing SDMA to help HDMI audio DMA. With the help
of SDMA, HDMI audio can use ping-pong buffer mechanism and FIFO underrun
can be avoid.
In this path: Add SDMA support for i.MX6Q later than TO1.2.
ENGR00218013-4 MX6Q ARM2: Set HDMI event as event 2 of SDMA event
Select external SDMA request as SDMA event 2 for MX6Q ARM2 board.
SDMA event 2 can be configured HDMI or IPU. Signed-off-by: Chen Liangjun <b36089@freescale.com>
ENGR00218624 ASRC: set dma_data to 0 before config SDMA
To allocate an SDMA channel, imx_dma_data struct is need. However,
if the member dma_request_p2p is not set to 0 before configuration,
SDMA driver would treat the channel as p2p(periphal to periphal) DMA and
set SDMA channel context in p2p way. In the worst case, SDMA would
access some unexisted address cause of mis configuration above and thus
cause kernel panic or hang.
In this patch, set imx_dma_data struct to 0 once it is allocated from
stack.
Robin Gong [Thu, 26 Jul 2012 09:00:48 +0000 (17:00 +0800)]
ENGR00172083 SPI-NOR mx6: fix failed erase uboot ENV on SPI-NOR by MFG tool
In MFG tool will use "flash_eraseall /dev/mtd0" command to erase whole mtd0
partition, but u-boot environment params are stored in offset 0xc0000 which
exceed the u-boot patition 0x40000, it means the "flash_eraseall" command only
erase u-boot partition, but not environment area. So we need increase the size
of u-boot partition to 0x100000 as what we remain 1MB for u-boot. Signed-off-by: Robin Gong <B38343@freescale.com>
make shi [Wed, 25 Jul 2012 02:10:45 +0000 (10:10 +0800)]
ENGR00215520-03 Mx6:USB host: USB Host1 modulization
- remove mx6_usb_h1_init() in board specific initialization files
- Add module_init(mx6_usb_h1_init) and module_exit(mx6_usb_h1_exit) in usb_h1.c
to support the usb_h1 modulization
- Export necessary function which is used in usb_h1.c
make shi [Fri, 20 Jul 2012 02:43:09 +0000 (10:43 +0800)]
ENGR00215520-01 Mx6:USB host: USB Host1 modulization
- Add USB_EHCI_ARC_H1 configuration to imx6_defconfig and imx6s_defconfig,
the default configuration is selected as "y"
- add related USB_EHCI_ARC_H1 configuration to Makefile
- add related USB_EHCI_ARC_H1 configuration to Kconfig
* wifi downlink throughput is tested by iperf in open air.
** writing performance for SDMA is much slower than ADMA, it might
be an issue which needs further investigation.
ENGR00216848 MX6 DL dual display failed on HDMI and LVDS
HDMI output video mode is 1080p, LVDS output is XGA.
The IPU bandwidth is not enough to support the two display output
when IPU HSP clock setting to 200MHz,
increase the IPU HSP clock to 270MHz and dual display can work.
When system not boot up all cores, such as adding max_cpus=n,
n<NR_CPUS, then the conservative governor will increase the cpu
frequncy to the highest freq and never get to down.
Signed-off-by: Lin Fuzhen <fuzhen.lin@freescale.com>
Liu Ying [Tue, 24 Jul 2012 10:01:35 +0000 (18:01 +0800)]
ENGR00182061-3 MX6 SabreSD:Correct camera pwdn function
This patch adds 2ms sleep after camera power down signal
is set to high or to low to ensure power down or up
is successful. OV5640/OV5642 camera specs say that they
require this condtion to be true - for PWDN to go low,
power must first become stable(DVDD to PWDN>=1ms), so
this patch simply use 2ms which should be enough.
Rong Dian [Tue, 24 Jul 2012 02:34:15 +0000 (10:34 +0800)]
ENGR00218070 imx6 battery: fix charger led first wrong indication status
because boot time gap between led framwork and battery driver init,when system
boots with charger attatched, charger led framwork loses the first charger
online event,add once extra power_supply_changed can fix this issure
Robin Gong [Tue, 24 Jul 2012 01:56:28 +0000 (09:56 +0800)]
ENGR00218067 mx6sl LDO_BYPASS: enable LDO BYPASS in mx6sl by default
To validate LDO bypass function fully, enable CONFIG_MX6_INTER_LDO_BYPASS
on u-boot and kernel, only for mx6sl. Signed-off-by: Robin Gong <b38343@freescale.com>
Yuxi Sun [Tue, 17 Jul 2012 09:24:51 +0000 (17:24 +0800)]
ENGR00182271-3 V4L2 OVERLAY: Add IPU2 overaly support for fore ground
When vf_rotation > IPU_ROTATE_VERT_FLIP, canncel the MEM_ROT_VF_MEM
- MEM_FG_SYNC channel link and using IPU_IRQ_PRP_VF_ROT_OUT_EOF irq
to trigger double buffer switch.
When vf_rotation <= IPU_ROTATE_VERT_FLIP,cannel the CSI_PRP_VF_MEM
- MEM_FG_SYNC channel link, and using IPU_IRQ_PRP_VF_OUT_EOF to
trigger double buffer switch.
Alejandro Sierra [Fri, 20 Jul 2012 18:51:41 +0000 (13:51 -0500)]
ENGR00217857: Changed iomux ID pin
Changed iomux MX6Q ID pin to MX6Q_PAD_ENET_RX_ER__ANATOP_USBOTG_ID
This fix was already implemented on CR ENGR00180424. Somehow this
was not included on newer releases.
Signed-off-by: Alejandro Sierra <b18039@freescale.com>
Tony LIU [Fri, 20 Jul 2012 09:54:35 +0000 (17:54 +0800)]
ENGR00217721-5 usb gadget random transfer fail
usb driver part
- After USB driver prime a bulk transfer(whatever IN or OUT, take
OUT for example) on ep1, only one dTD is primed, an USB Interrupt
(bit 0 of USBSTS) will be issued, and find that endptcomplete
register is 0x2 which means an OUT transfer on ep1 is completed,
at this time the ep1 out queue head status is 0x1e18000, and next
dtd pointer is 0x1 which means transfer is done and everything is
OK, while the dTD token status is 0x2008080 which means this dTD
is still active, not completed yet.
- Audio SDMA and Ethernet have the similar issue
- root cause is not found yet
- work around:
change the non-cacheable bufferable memory to non-cacheable
non-bufferable memory to make this issue disappear.
Signed-off-by: Tony LIU <junjie.liu@freescale.com>
- After USB driver prime a bulk transfer(whatever IN or OUT, take
OUT for example) on ep1, only one dTD is primed, an USB Interrupt
(bit 0 of USBSTS) will be issued, and find that endptcomplete
register is 0x2 which means an OUT transfer on ep1 is completed,
at this time the ep1 out queue head status is 0x1e18000, and next
dtd pointer is 0x1 which means transfer is done and everything is
OK, while the dTD token status is 0x2008080 which means this dTD
is still active, not completed yet.
- Audio SDMA and Ethernet have the similar issue
- root cause is not found yet
- work around:
change the non-cacheable bufferable memory to non-cacheable
non-bufferable memory to make this issue disappear.
Signed-off-by: Tony LIU <junjie.liu@freescale.com>
- After USB driver prime a bulk transfer(whatever IN or OUT, take
OUT for example) on ep1, only one dTD is primed, an USB Interrupt
(bit 0 of USBSTS) will be issued, and find that endptcomplete
register is 0x2 which means an OUT transfer on ep1 is completed,
at this time the ep1 out queue head status is 0x1e18000, and next
dtd pointer is 0x1 which means transfer is done and everything is
OK, while the dTD token status is 0x2008080 which means this dTD
is still active, not completed yet.
- Audio SDMA and Ethernet have the similar issue
- root cause is not found yet
- work around:
change the non-cacheable bufferable memory to non-cacheable
non-bufferable memory to make this issue disappear.
Signed-off-by: Tony LIU <junjie.liu@freescale.com>
- After USB driver prime a bulk transfer(whatever IN or OUT, take
OUT for example) on ep1, only one dTD is primed, an USB Interrupt
(bit 0 of USBSTS) will be issued, and find that endptcomplete
register is 0x2 which means an OUT transfer on ep1 is completed,
at this time the ep1 out queue head status is 0x1e18000, and next
dtd pointer is 0x1 which means transfer is done and everything is
OK, while the dTD token status is 0x2008080 which means this dTD
is still active, not completed yet.
- Audio SDMA and Ethernet have the similar issue
- root cause is not found yet
- work around:
change the non-cacheable bufferable memory to non-cacheable
non-bufferable memory to make this issue disappear.
Signed-off-by: Tony LIU <junjie.liu@freescale.com>
- After USB driver prime a bulk transfer(whatever IN or OUT, take
OUT for example) on ep1, only one dTD is primed, an USB Interrupt
(bit 0 of USBSTS) will be issued, and find that endptcomplete
register is 0x2 which means an OUT transfer on ep1 is completed,
at this time the ep1 out queue head status is 0x1e18000, and next
dtd pointer is 0x1 which means transfer is done and everything is
OK, while the dTD token status is 0x2008080 which means this dTD
is still active, not completed yet.
- Audio SDMA and Ethernet have the similar issue
- root cause is not found yet
- work around:
change the non-cacheable bufferable memory to non-cacheable
non-bufferable memory to make this issue disappear.
Signed-off-by: Tony LIU <junjie.liu@freescale.com>
projects / karo-tx-linux.git / log