Marek Vasut [Fri, 21 Feb 2014 17:13:26 +0000 (18:13 +0100)]
mtd: spi: Fix page size for S25FL032P,S25FL064P
The commit 6af8dc3ebccb3b1e4b2e479315e49545e7f53150 broke support for
S25FL032P and S25FL064P by carelessly removing the code handling special
page size for these two SPI NOR flashes and unifying the code under the
assumption that Extended JEDEC ID of 0x4d00 always implies 512b page size.
Add special case handling for these two SPI NOR flashes.
Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Marek Vasut [Wed, 15 Jan 2014 14:29:43 +0000 (15:29 +0100)]
sf: Fix entries for S25FL256S_256K and S25FL512S_256K
Both of these chips have 256kB big sectors, thus the _256K suffix,
compared to their _64K counterparts, which have 64kB sectors. Also,
they have four times less sectors than their _64K counterparts.
Signed-off-by: Marek Vasut <marex@denx.de> Tested-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Pull out "$(SRCTREE)/" from CONFIG_SYS_KWD_CONFIG
and push it into the top Makefile.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Michael Walle <michael@walle.cc> Cc: Simon Guinot <simon.guinot@sequanux.org> Cc: Dave Purdy <david.c.purdy@gmail.com> Cc: Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net> Cc: Luka Perkov <luka@openwrt.org> Cc: Valentin Longchamp <valentin.longchamp@keymile.com> Cc: Jason Cooper <u-boot@lakedaemon.net> Cc: Siddarth Gore <gores@marvell.com> Cc: Prafulla Wadaskar <prafulla@marvell.com> Cc: Eric Cooper <ecc@cmu.edu> Cc: Suriyan Ramasami <suriyan.r@gmail.com>
Gerhard Sittig [Sat, 8 Mar 2014 18:46:18 +0000 (19:46 +0100)]
usb: net: update README.usb to list all USB ethernet options
- extend the discussion of USB network related config options such that
all available adapter drivers are listed, and that the 'usb' command
for the interactive prompt and scripting becomes available
- suggest to *not* put individual IP configuration parameters into the
exectuable, but instead to put them into external environment or fetch
them from network
Signed-off-by: Gerhard Sittig <gsi@denx.de> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Marek Vasut <marex@denx.de>
Gerhard Sittig [Sat, 8 Mar 2014 18:46:16 +0000 (19:46 +0100)]
tegra: imx: omap: enable Moschip USB ethernet support for several boards
enable support for the Moschip USB ethernet adapter for those boards
which previously had support for "all other" USB ethernet adapters
(that's Asix _and_ SMSC) enabled -- which applies to harmony, m53evk,
mx53loco, nitrogen6x, omap3_beagle
Signed-off-by: Gerhard Sittig <gsi@denx.de> Acked-by: Marek Vasut <marex@denx.de>
Gerhard Sittig [Sat, 8 Mar 2014 18:46:14 +0000 (19:46 +0100)]
usb: net: introduce support for Moschip USB ethernet
introduce an 'mcs7830' driver for Moschip MCS7830 based (7730/7830/7832)
USB 2.0 Ethernet Devices
see "MCS7830 -- USB 2.0 to 10/100M Fast Ethernet Controller" at
http://www.asix.com.tw/products.php?op=pItemdetail&PItemID=109;74;109
the driver was implemented based on the U-Boot Asix driver with
additional information gathered from the Moschip Linux driver,
development was done on "Delock 61147" and "Logilink UA0025C" dongles
Signed-off-by: Gerhard Sittig <gsi@denx.de> Acked-by: Marek Vasut <marex@denx.de>
Dustin Byford [Fri, 7 Mar 2014 04:48:23 +0000 (20:48 -0800)]
fw_env: correct writes to devices with small erase blocks
Some NOR flash devices have a small erase block size. For example, the
Micron N25Q512 can erase in 4K blocks. These devices expose a bug in
fw_env.c where flash_write_buf() incorrectly calculates bytes written
and attempts to write past the environment sectors. Luckily, a range
check prevents any real damage, but this does cause fw_setenv to fail
with an error.
This change corrects the write length calculation.
The bug was introduced with commit 56086921 from 2008 and only affects
configurations where the erase block size is smaller than the total
environment data size.
Dustin Byford [Fri, 7 Mar 2014 04:48:22 +0000 (20:48 -0800)]
fw_env: calculate default number of env sectors
The assumed number of environment sectors (always 1) leads to an
incorrect top_of_range calculation in fw.env.c when a flash device has
an erase block size smaller than the environment data size (number of
environment sectors > 1).
This change updates the default number of environment sectors to at
least cover the size of the environment.
Also corrected a false statement about the number of sectors column in
fw_env.config.
Masahiro Yamada [Tue, 11 Mar 2014 03:19:12 +0000 (12:19 +0900)]
boards.cfg: move boards with invalid emails to Orphan
When I cc board maintainers, some of them result in
bounce mails.
It turned out the following do not work any more:
Yuli Barcohen <yuli@arabellasw.com>
Travis Sawyer <travis.sawyer@sandburst.com>
Yusdi Santoso <yusdi_santoso@adaptec.com>
David Updegraff <dave@cray.com>
Sangmoon Kim <dogoil@etinsys.com>
Anton Vorontsov <avorontsov@ru.mvista.com>
Blackfin Team <u-boot-devel@blackfin.uclinux.org>
Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
Andre Schwarz <andre.schwarz@matrix-vision.de>
For the blackfin boards where Sonic Zhang is also listed
as a maintainer, dead addresses should be simply dropped.
For all of the others, the status should be changed to "Orphan".
We have adopted the definition of "Orphan" as:
board is not actively maintained any more but still builds, and any
address associated with it is that of the last known maintainer(s)
Even though the emails do not work any more, they carry information.
We want to keep them.
Besides, Orphan boards have been collected at the bottom of boards.cfg.
(This is done when we run "tools/reformat.py")
Add separators to distinguish them from those which
were moved to Orphan 6 months ago.
I believe it will be helpful in future to find which boards are
old enough to be removed from the code base.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Detlev Zundel <dzu@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Stephen Warren [Fri, 14 Feb 2014 04:15:18 +0000 (21:15 -0700)]
usb: create common header virtual root hub descriptors
Many USB host controller drivers contain almost identical copies of the
same virtual root hub descriptors. Put these into a common file to avoid
duplication.
Note that there were some very minor differences between the descriptors
in the various files, such as:
- USB 1.0 vs. USB 1.1
- Manufacturer/Device ID
- Max packet size
- String content
I assume these aren't relevant.
Cc: Thomas Lange <thomas@corelatus.se> Cc: Shinya Kuribayashi <skuribay@pobox.com> Cc: Gary Jennejohn <garyj@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Eric Millbrandt <emillbrandt@coldhaus.com> Cc: Pierre Aubert <p.aubert@staubli.com> Cc: Stefan Roese <sr@denx.de> Cc: Daniel Hellstrom <daniel@gaisler.com> Cc: Denis Peter <d.peter@mpl.ch> Cc: Rodolfo Giometti <giometti@linux.it> Cc: Zhang Wei <wei.zhang@freescale.com> Cc: Mateusz Zalega <m.zalega@samsung.com> Cc: Remy Bohmer <linux@bohmer.net> Cc: Markus Klotzbuecher <mk@denx.de> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Gary Jennejohn <garyj@denx.de> Cc: C Nauman <cnauman@diagraph.com> Cc: David Müller <d.mueller@elsoft.ch> Cc: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Thomas Abraham <t-abraham@ti.com> Cc: Tom Rini <trini@ti.com> Cc: Andrew Murray <amurray@embedded-bits.co.uk> Cc: Matej Frančeškin <matej.franceskin@comtrade.com> Cc: Cliff Cai <cliff.cai@analog.com> Cc: Bryan Wu <cooloney@gmail.com> Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Stephen Warren [Thu, 6 Feb 2014 20:13:06 +0000 (13:13 -0700)]
usb: ehci: fully align interrupt QHs/QTDs
These data structures are passed to cache-flushing routines, and hence
must be conform to both the USB the cache-flusing alignment requirements.
That means aligning to USB_DMA_MINALIGN. This is important on systems
where cache lines are >32 bytes.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Stephen Warren [Fri, 7 Feb 2014 16:53:50 +0000 (09:53 -0700)]
ush: ehci: initialize altnext pointers in QH
Section 4.10.2 "Advance Queue" of ehci-specification-for-usb.pdf
specifies how an EHCI controller loads a new QTD for processing if the
QH is not already marked as active. It states:
=====
If the field Bytes to Transfer is not zero and the T-bit in the Alternate
Next qTD Pointer is set to zero, then the host controller uses the
Alternate Next qTD Pointer. Otherwise, the host controller uses the Next
qTD Pointer. If Next qTD Pointer’s T-bit is set to a one, then the host
controller exits this state and uses the horizontal pointer to the next
schedule data structure.
=====
Hence, we must ensure that the alternate next QTD pointer's T-bit
(TERMINATE) is set, so the EHCI controller knows to use the next QTD
pointer.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Eric Nelson [Sat, 8 Mar 2014 14:55:52 +0000 (07:55 -0700)]
cfb_console: align fields in gzipped .bmp files
.bmp files contain 32-bit integers aligned at offsets of +2, +6,
et cetera within the bmp_header structure (see include/bmp_layout.h).
Support for gzip-compressed .bmp files is present in the cfb_console
display subsystem by uncompressing them prior to use.
This patch forces the in-memory header to be aligned properly
for these compressed images by extracting them to a 2-byte
offset in the memory returned by malloc. Since malloc will always
return a 4-byte aligned value, this forces the .bmp header
fields to be naturally aligned on 4-byte addresses.
Refer to these files for more details:
doc/README.displaying-bmps
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Ian Campbell [Fri, 7 Mar 2014 01:20:58 +0000 (01:20 +0000)]
ahci: wait longer for link.
I have observed timeouts on a cubietruck.
The increase to 40ms is completely arbitrary and Works For Me(tm). I
couldn't find a good reference for how long you are supposed to wait,
although googling around it seems like tens of ms rather than single
digits is more common. I don't think there is any harm in waiting a bit
longer.
Bo Shen [Mon, 3 Mar 2014 06:47:16 +0000 (14:47 +0800)]
mtd: nand: atmel: prepare for nand spl boot support
Prepare for nand spl boot support. It supports nand software ECC and
hardware PMECC.
This patch is take <drivers/mtd/nand/nand_spl_simple.c> as reference.
Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Bo Shen [Sun, 9 Feb 2014 07:52:39 +0000 (15:52 +0800)]
ARM: atmel: add sama5d3 Xplained board support
Add sama5d3 Xplained board support which use Atmel SAMA5D36 SoC.
Now it supports boot from NAND flash and SD/MMC card.
Features support:
- NAND flash
- SD/MMC card
- Two USB hosts
- Ethernet (one GMAC, one EMAC)
Signed-off-by: Bo Shen <voice.shen@atmel.com>
[reorder boards.cfg] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
It's called _pio_ in the version that was added to git.
Apparently it got renamed without updating the macros before it was
applied, c.f.
http://u-boot.10912.n7.nabble.com/U-Boot-PATCH-3-9-V3-add-a-new-AT91-GPIO-driver-td75922.html
Signed-off-by: Andreas Henriksson <andreas.henriksson@endian.se> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Add support for using the Atmel MCI driver on at91sam9263ek.
This change is modeled after the existing at91sam9260ek support.
Please note that this hooks up slot1 (MCI1) for SD. Not both.
Tested with at91bootstrap and u-boot on dataflash in slot 0
and fat-formatted 8GB SDHC in slot 1 on first revision
at91sam9263ek (which must use dataflash in slot0 to boot).
CONFIG_ATMEL_MCI_PORTB not tested.
Signed-off-by: Andreas Henriksson <andreas.henriksson@endian.se>
[remove empty line] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Priyanka Jain [Wed, 26 Feb 2014 04:08:37 +0000 (09:38 +0530)]
powerpc/t104xrdb: Update DDR initialization related settings
Update following DDR related settings for T1040RDB, T1042RDB_PI
-Correct number of chip selects to two as t1040 supports
two Chip selects.
-Update board_specific_parameters udimm structure with settings
derived via calibration.
-Update ddr_raw_timing sructure corresponding to DIMM.
-Set ODT to off. Typically on FSL board, ODT is set to 75 ohm,
but on T104xRDB, on setting this , DDR instability is observed.
Board-level debugging is in progress.
Verified the updated settings to be working fine with dual-ranked
Micron, MT18KSF51272AZ-1G6 DIMM at data rate 1600MT/s.
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
Priyanka Jain [Wed, 26 Feb 2014 10:41:53 +0000 (16:11 +0530)]
powerpc/t1040qds: Add Video - HDMI support
T1040 has internal display interface unit (DIU) for driving video.
T1040QDS supports video mode via
-LCD using TI enconder
-HDMI type interface via HDMI encoder
Chrontel, CH7301C encoder which is I2C programmable is used as
HDMI connector on T1040QDS.
This patch add support to
-enable Video interface for T1040QDS
-route qixis multiplexing to enable DIU-HDMI interface on board
-program DIU pixel clock gerenartor for T1040
-program HDMI encoder via I2C on board
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Priyanka Jain [Thu, 30 Jan 2014 10:09:58 +0000 (15:39 +0530)]
powerpc/mpc85xx: Add SCFG_PIXCLKCR register support for T1040
T1040 SoC has SCFG (Supplement Configuration) Block which provides
chip specific configuration and status support. The base address of
SCFG block in T1040 is 0xfc000.
SCFG contains SCFG_PIXCLKCR (DIU pixel clock control register)
at offset 0x28.
Add definition of
-SCFG block
-SCFG_PIXCLKCR register
-Bits definition of SCFG_PIXCLK register
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Mela Custodio [Wed, 19 Feb 2014 15:16:57 +0000 (00:16 +0900)]
bootstage: powerpc: support fdt stash and reporting
This implements stashing of bootstage timing data to FDT and automatic
timing reporting. To enable define CONFIG_BOOTSTAGE_FDT and
CONFIG_BOOTSTAGE_REPORT respectively.
Signed-off-by: Rommel G Custodio <sessyargc+u-boot@gmail.com> Reviewed-by: York Sun <yorksun@freescale.com>
USB spec says that the minimum disconnect threshold should be
over 525 mV. However, internal USB PHY threshold value is below
this specified value. Due to this some devices disconnect at
run-time. Hence, phy settings are tweaked to increased disconnect
threshold to be above 525mV by using this workaround.
Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Shaveta Leekha [Wed, 26 Feb 2014 10:38:22 +0000 (16:08 +0530)]
powerpc/b4860: Add workaround for errata A006384 and A006475
SerDes PLLs may not lock reliably at 5 G VCO configuration(A006384)
and at cold temperatures(A006475), workaround recalibrate the
PLLs with some SerDes configuration
Both these errata are only applicable for b4 rev1.
So, make workaround for these errata conditional,
depending upon soc version.
Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Shaveta Leekha [Wed, 26 Feb 2014 10:37:51 +0000 (16:07 +0530)]
B4860qds: Set SerDes2 refclk2 at to 156.25MHz for XFI to work
Change setting of SerDes2 refclk2 to have the default value as it is
coming on board that is 156.25MHz, for XFI to work.
Also change PLL_NUM variable to the one defined in config_mpc85xx.h
for B4860 and B4420.
Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Shaveta Leekha [Wed, 26 Feb 2014 10:36:56 +0000 (16:06 +0530)]
board/b4860qds: Add support to make PCIe SATA work on B4860QDS
1) SerDes2 Refclks have been set properly to make
PCIe SATA to work as it work on SerDes refclk of 100MHz
2) Mask the SerDes's device reset request before changing
the Refclks for SerDes1 and SerDes2 for PLL locks to
happen properly, device reset request bit unmasked
after SerDes refclks configuration
Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Shaveta Leekha [Wed, 26 Feb 2014 10:36:30 +0000 (16:06 +0530)]
board/b4860qds: Add support to make Aurora work on B4860QDS
1) Add new SerDes1 protocols having Aurora in them
2) Add VSC cross point connections for Aurora to work with
CPRI and SGMIIs
3) Configure VSC crossbar switch to connect SerDes1
lanes to aurora on board, by checking SerDes1 protocols
4) SerDes1 Refclks have been set properly to make
Aurora, CPRI and SGMIIs to work together properly
Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Masahiro Yamada [Wed, 5 Mar 2014 08:40:10 +0000 (17:40 +0900)]
powerpc: mpc8260: consolidate CONFIG_MPC8260 and CONFIG_8260
Before this commit, CONFIG_MPC8260 and CONFIG_8260
were used mixed-up.
All boards with mpc8260 cpu defined both of them:
- CONFIG_MPC8260 was defined in board config headers
and include/common.h
- CONFIG_8260 was defined arch/powerpc/cpu/mpc8260/config.mk
We do not need to have both of them.
This commit keeps only CONFIG_MPC8260.
This commit does:
- Delete CONFIG_8260 and CONFIG_MPC8260 definition
in config headers and include/common.h
- Rename CONFIG_8260 to CONFIG_MPC8260
in arch/powerpc/cpu/mpc8260/config.mk.
- Rename #ifdef CONFIG_8260 to #ifdef CONFIG_MPC8260
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Wolfgang Denk <wd@denx.de>
Masahiro Yamada [Wed, 5 Mar 2014 08:25:37 +0000 (17:25 +0900)]
mips: move CONFIG_MIPS{32, 64} definition to config.mk
All mips32 boards define CONFIG_MIPS32 in config headers
except malta boards which define it in boards.cfg.
We can consolidate them by defining it in
arch/mips/cpu/mips32/config.mk.
CONFIG_MIPS64 definition can be moved to
arch/mips/cpu/mips64/config.mk as well.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Acked-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Masahiro Yamada [Wed, 5 Mar 2014 07:59:40 +0000 (16:59 +0900)]
kbuild: improve Kbuild speed
Kbuild brought about many advantages for us but a significant
performance regression was reported by Simon Glass.
After some discussions and analysis, it turned out
its main cause is in $(call cc-option,...).
Historically, U-Boot parses all config.mk
(arch/*/config.mk and board/*/config.mk)
every time descending into subdirectories.
That means cc-options are evaluated over and over again.
$(call cc-option,...) is useful but costly.
So we want to evaluate them only in ./Makefile
and spl/Makefile and export compiler flags.
This commit changes the build system as follows:
- Modify scripts/Makefile.build to not include config.mk
Instead, add $(PLATFORM_CPPFLAGS) to asflags-y, ccflags-y,
cppflags-y.
- Export many variables
Going forward, Kbuild will not parse config.mk files
when it descends into subdirectories.
If we want to set variables in config.mk and use them
in subdirectories, they must be exported.
This is the list of variables to get exported:
PLATFORM_CPPFLAGS
CPUDIR
BOARDDIR
OBJCOPYFLAGS
LDFLAGS
LDFLAGS_FINAL
(used in nand_spl/board/*/*/Makefile)
CONFIG_STANDALONE_LOAD_ADDR
(used in examples/standalone/Makefile)
SYM_PREFIX
(used in examples/standalone/Makefile)
RELFLAGS
(used in examples/standalone/Makefile)
- Delete CPPFLAGS
This variable has been replaced with PLATFORM_CPPFLAGS
- Copy gcclibdir from example/standalone/Makefile
to arch/sparc/config.mk
The reference in CONFIG_STANDALONE_LOAD_ADDR must be
resolved before it is exported.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Reported-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> [on Sandbox] Tested-by: Stephen Warren <swarren@nvidia.com> [on Tegra]
Masahiro Yamada [Wed, 5 Mar 2014 07:59:38 +0000 (16:59 +0900)]
kbuild: add CONFIG_ prefix to USE_PRIVATE_LIBGCC
Before this commit, USE_PRIVATE_LIBGCC was defined in
arch-specific config.mk and referenced in
arch/$(ARCH)/lib/Makefile.
We are not happy about parsing config.mk again and again.
We have to keep the same behavior with a different way.
By adding "CONFIG_" prefix, this macro appears
in include/autoconf.mk, include/spl-autoconf.mk.
(And treating USE_PRIVATE_LIBGCC as CONFIG macro
is reasonable enough.)
Tegra SoC family defined USE_PRIVATE_LIBGCC as "yes"
in arch/arm/cpu/arm720t/tegra*/config.mk,
whereas did not define it in arch/arm/cpu/armv7/tegra*/config.mk.
It means Tegra enables PRIVATE_LIBGCC only for SPL.
We can describe the same behavior by adding
Many (but not all) of Blackfin boards give -O2 option
to compile under lib/ directory.
That means lib/ should be speed-optimized,
whereas other parts should be size-optimized.
We want to keep the same behavior,
but do not want to parse board/*/config.mk again and again.
We've got no choice but to invent a new method.
CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED, if it is enabled,
gives -O2 flag only for building under lib/ directory.
Dirty codes which I had marked as "FIX ME"
in board/${BOARD}/config.mk have been deleted.
Instead, CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED has been
defined in include/configs/${BOARD}.h.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Sonic Zhang <sonic.zhang@analog.com>
Tom Rini [Tue, 4 Mar 2014 20:52:35 +0000 (15:52 -0500)]
cmd_nvedit: Make 'env import -c' require size parameter
When importing a checksummed area we need to be told how big the area in
question is so that we know that will match the size of the area which
the checksum is generated against.
Reported-by: Pierre AUBERT <p.aubert@staubli.com> Signed-off-by: Tom Rini <trini@ti.com>
Stefan Roese [Tue, 4 Mar 2014 14:34:35 +0000 (15:34 +0100)]
ppc4xx: Remove 4xx NAND booting support
As ppc4xx currently only supports the deprecated nand_spl infrastructure
and nobody seems to have time / resources to port this over to the newer
SPL infrastructure, lets remove NAND booting completely.
This should not affect the "normal", non NAND-booting ppc4xx platforms
that are currently supported.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Tirumala Marri <tmarri@apm.com> Cc: Matthias Fuchs <matthias.fuchs@esd.eu> Cc: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Tom Rini <trini@ti.com> Tested-by: Matthias Fuchs <matthias.fuchs@esd.eu>
Stephen Warren [Sun, 2 Mar 2014 05:18:00 +0000 (22:18 -0700)]
unit-test: make "test -e" test independent of $CWD
The unit-test for hush's "test -e" currently relies upon being run in
the U-Boot build directory, because it tests for the existence of a file
that exists in that directory.
Fix this by explicitly creating the file we use for the existence test,
and deleting it afterwards so that multiple successive unit-test
invocations succeed. This required adding an os.c function to erase
files.
Reported-by: Simon Glass <sjg@chromium.org> Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Stephen Warren [Sun, 2 Mar 2014 05:16:10 +0000 (22:16 -0700)]
hush: fix some quoted variable expansion issues
The following shell command fails:
if test -z "$x"; then echo "zero"; else echo "non-zero"; fi
(assuming $x does not exist, it prints "non-zero" rather than "zero").
... since "$x" expands to nothing, and the argument is completely
dropped, causing too few to be passed to -z, causing cmd_test() to
error out early.
This is because when variable expansions are processed by make_string(),
the expanded results are concatenated back into a new string. However,
no quoting is applied when doing so, so any empty variables simply don't
generate any parameter when the combined string is parsed again.
Fix this by explicitly replacing quoting any argument that was originally
quoted when re-generating a string from the already-parsed argument list.
This also fixes loss of whitespace in commands such as:
setenv space " "
setenv var " 1${space}${space} 2 "
echo ">>${var}<<"
Reported-by: Russell King <linux@arm.linux.org.uk> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Stephen Warren [Fri, 28 Feb 2014 05:01:28 +0000 (22:01 -0700)]
unit-test: clean up evironment after Hush tests
Delete the temporary variables that are used to save unit-test results
from the environment after running the test. This prevents polluting
the environment, or growing it too much.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Acked-by: Simon Glass <sjg@chromium.org>
Stephen Warren [Thu, 27 Feb 2014 20:27:02 +0000 (13:27 -0700)]
net: asix: don't pad odd-length TX packets
For Ethernet/USB RX packets, the ASIX HW pads odd-sized packets so that
they have an even size. Currently, asix_recv() does remove this padding,
and asic_send() adds equivalent padding in the TX path. However, the HW
does not appear to need this packing for TX packets in practical testing
with "ASIX Elec. Corp. AX88x72A 000001" Vendor: 0x0b95 Product 0x7720
Version 0.1. The Linux kernel does no such padding for the TX path.
Remove the padding from the TX path:
* For consistency with the Linux kernel.
* NVIDIA has a Tegra simulator which validates that the length of USB
packets sent to an ASIX device matches the packet length value inside
the packet data. Having U-Boot and the kernel do the same thing when
creating the TX packets simplifies the simulator's validation.
Cc: Lucas Stach <dev@lynxeye.de> Cc: Marek Vasut <marex@denx.de> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Marek Vasut <marex@denx.de> Tested-by: Marek Vasut <marex@denx.de> Tested-by: Gerhard Sittig <gsi@denx.de>
OMAP3: igep00x0: Enable required clocks for GPIO that are used.
Enable required clocks for GPIO to fix a boot issue introduced by commit f33b9bd3984fb11e1d8566a866adc5957b1e1c9d (arm: omap3: Enable clocks for
peripherals only if they are used).
Without this patch the u-boot freezes after the following messages
To avoid this we just need enable the clocks for GPIOs that are used, but it
would be interesting implement a mechanism to protect these situations and
make sure that the clock is enabled when we request a GPIO.
Signed-off-by: Enric Balletbo i Serra <eballetbo@gmail.com>
B&R boards are using Phy Addresses 'one' and 'two', prior this was
defined through #define PHYADDR 1 within a header file.
Now this is addresses are given with device-driver structure.
Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
Stephen Warren [Wed, 5 Feb 2014 16:24:59 +0000 (09:24 -0700)]
ARM: tegra: implement bootcmd_pxe
This retrieves a PXE config file over the network, and executes it. This
allows an extlinux config file to be retrieved over the network and
executed, whereas the existing bootcmd_dhcp retrieves a U-Boot script.
Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
Stephen Warren [Wed, 5 Feb 2014 16:24:58 +0000 (09:24 -0700)]
ARM: tegra: rework boot scripts
Update the common Tegra boot scripts in the default environment to
a) Make use of the new "test -e" shell command to avoid some error
messages.
b) Allow booting using the sysboot command and extlinux.conf. This
allows easy creation of boot menus, and provides a simple interface
for distros to parameterize/configure the boot process.
Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
Stephen Warren [Wed, 5 Feb 2014 16:24:57 +0000 (09:24 -0700)]
ARM: tegra: convert tegra to use distro defaults
Modify all Tegra boards to include the "distro defaults" header, so that
all the config options distros expect are enabled. Remove any #defines
that enable the same options from the Tegra files.
Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
Stephen Warren [Mon, 10 Feb 2014 20:11:53 +0000 (13:11 -0700)]
ARM: tegra: set CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS
Tegra's EHCI controllers only have a single PORTSC register. Configure
U-Boot to know this. This prevents e.g. ehci_shutdown() from touching
non-existent registers.
Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
Stephen Warren [Mon, 3 Feb 2014 21:03:27 +0000 (14:03 -0700)]
ARM: tegra: simplify halt_avp()
In order to completely halt the AVP processor, we should simply write
FLOW_MODE_STOP without any extra options that allow wakeup. Amend the
code to do this.
I believe that enabling FIQ_1 and IRQ_1 allow the CPU to be awoken by
interrupts. We don't want this; if later SW wishes to use the AVP, it
should be reset and booted from scratch.
Related, the bits that were previously IRQ_1 and FIQ_1 have a slightly
different definition starting with Tegra114, so the values we're
writing don't entirely make sense there anyway.
Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
Register pmc_pwrgate_timer_mult has a different layout on Tegra114 and
Tegra124. Reflect this in pmc.h.
Also, simply write the whole of the register in start_cpu() rather than
doing a read-modify-write; the register is simple enough that the code
can easily construct the entire desired value.
Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
Stephen Warren [Mon, 3 Feb 2014 21:03:24 +0000 (14:03 -0700)]
ARM: tegra: move CONFIG_TEGRAnn
<asm/arch-tegra/tegra.h> needs to use CONFIG_TEGRA* to conditionalize
some definitions, since some modules moved between generations. Move
the definition of CONFIG_TEGRAnn to a header that's included earlier,
so that it's set by the time tegra.h needs to use it.
Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
pekon gupta [Fri, 22 Nov 2013 11:23:30 +0000 (16:53 +0530)]
mtd: nand: omap: move omap_elm.h from arch/arm/include/asm to drivers/mtd/nand
omap_elm.h is a generic header used by OMAP ELM driver for all TI platfoms.
Hence this file should be present in generic folder instead of architecture
specific include folder.
Build tested using: ./MAKEALL -s am33xx -s omap3 -s omap4 -s omap5
pekon gupta [Fri, 22 Nov 2013 11:23:29 +0000 (16:53 +0530)]
mtd: nand: omap: move omap_gpmc.h from arch/arm/include/asm to drivers/mtd/nand
omap_gpmc.h is a generic header used by OMAP NAND driver for all TI platfoms.
Hence this file should be present in generic folder instead of architecture
specific include folder.
Build tested using: ./MAKEALL -s am33xx -s omap3 -s omap4 -s omap5
pekon gupta [Fri, 22 Nov 2013 11:23:28 +0000 (16:53 +0530)]
mtd: nand: omap: merge duplicate GPMC data from different arch-xx headers into common omap_gpmc.h
Each SoC platform (AM33xx, OMAP3, OMAP4, OMAP5) has its own copy of GPMC related
defines and declarations scattered in SoC platform specific header files
like include/asm/arch-xx/cpu.h
However, GPMC hardware remains same across all platforms thus this patch merges
GPMC data scattered across different arch-xx specific header files into single
header file include/asm/arch/omap_gpmc.h
pekon gupta [Fri, 22 Nov 2013 11:23:27 +0000 (16:53 +0530)]
mtd: nand: omap: remove unused #defines from common omap_gpmc.h
OMAP NAND driver can detect Page-size and OOB-size of NAND device from ONFI
params or nand_id[] table. And based on that it defines ECC layout.
This patch
1) removes following board configs used for defining NAND ECC layout
- GPMC_NAND_ECC_LP_x16_LAYOUT (for large page x16 NAND)
- GPMC_NAND_ECC_LP_x8_LAYOUT (for large page x8 NAND)
- GPMC_NAND_ECC_SP_x16_LAYOUT (for small page x16 NAND)
- GPMC_NAND_ECC_SP_x8_LAYOUT (for small page x8 NAND)
2) removes unused #defines in common omap_gpmc.h depending on above configs
pekon gupta [Fri, 22 Nov 2013 11:23:26 +0000 (16:53 +0530)]
mtd: nand: omap: remove redundant platform specific header: arch-xx/omap_gpmc.h
Currently there are two sets of omap_gpmc.h header files
(a) arch/arm/include/asm/omap_gpmc.h
common header file for all platforms, containing defines and declarations used
by GPMC NAND driver.
(b) arch/arm/include/asm/arch-xx/omap_gpmc.h
SoC platform specific header file containing defines like ECC layout.
This patch removes platform specific arch-xx/omap_gpmc.c because:
- GPMC hardware engine is common for all SoC platforms hence only (a) is enough
- ECC layout is now defined in omap_nand.c driver itself based on ecc-scheme
selected. Hence all ECC layout declarations in (b) are redundant.
projects / karo-tx-uboot.git / log