The Meson6 SoC is produced by Amlogic inc. and it is based on 2 Cortex
A9 and an ARM Mali-400 GPU.
This patch adds two basic DTSI for the preliminary support of Meson and
Meson6 SoCs. Another DTS is also added for supporting the atv1200 board,
produced by Geniatech inc.
Signed-off-by: Carlo Caione <carlo@caione.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Olof Johansson [Wed, 24 Sep 2014 18:29:31 +0000 (11:29 -0700)]
Merge tag 'imx-dt-3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt
Merge "ARM: imx: device tree changes for 3.18" from Shawn Guo:
The i.MX device tree changes for 3.18:
- Device tree support for i.MX ADS and Armadeus APF9328 boards
- Enable thermal sensor support for i.MX6SL
- Add LCD support for i.MX6SL EVK board
- Fix display duplicate name for a bunch of board dts files
- Configure imx6qdl-sabresd board pins locally to remove the dependency
on bootloader
- A set of imx28-tx28 board dts updates from Lothar
- Add pci config space as platform resource
- Enable devices RTC, I2C and HDMI for nitrogen6x board
- Split HummingBoard DT to support s/dl and d/q
- mSATA and IR input support for HummingBoard
- Add SSI baud clock for i.MX6 device trees
- Add USB support for vf610-colibri and vf610-twr boards
- A set of cleanup and updates on Gateworks boards
* tag 'imx-dt-3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (86 commits)
ARM: dts: imx6: make gpt per clock can be from OSC
ARM: dts: imx: ventana: add canbus support for GW52xx
ARM: dts: imx: ventana: cleanup pinctrl groups
ARM: dts: imx: ventana: configure padconf for all pins
ARM: dts: imx: ventana: use gpio constants
ARM: dts: imx: ventana: remove unused aliases
ARM: dts: imx: ventana: remove unsupported dt nodes
ARM: dts: imx28-tx28: add alias for CAN XCVR regulator
ARM: dts: imx28-tx28: add spi-gpio as alternative for spi-mxs
ARM: dts: imx28-tx28: use GPIO flags
ARM: dts: imx28-tx28: remove spidev labels and add third instance of spidev
ARM: dts: imx6sl: add baud clock and clock-names for ssi
ARM: dts: imx6qdl: add baud clock and clock-names for ssi
ARM: dts: imx6qdl-sabresd: Configure the pins locally
ARM: dts: imx28-m28evk: Fix display duplicate name warning
ARM: dts: imx28-tx28: Fix display duplicate name warning
ARM: dts: imx28-m28cu: Fix display duplicate name warning
ARM: dts: imx28-cfa100: Fix display duplicate name warning
ARM: dts: imx28-apf28dev: Fix display duplicate name warning
ARM: dts: imx28-apx4devkit: Fix display duplicate name warning
...
Olof Johansson [Wed, 24 Sep 2014 17:38:57 +0000 (10:38 -0700)]
Merge tag 'mvebu-dt-3.18' of git://git.infradead.org/linux-mvebu into next/dt
Merge "ARM: mvebu: DT changes for v3.18" from Jason Cooper:
mvebu DT changes for v3.18
- Armada 375
- Add RTC support
- Armada 370
- Add proper pinmuxing
- Add SSCG
- Add gpio-fan
- Add LED support
- change Intersil vendor prefix to isil
- use improved Armada SPI compatible string
* tag 'mvebu-dt-3.18' of git://git.infradead.org/linux-mvebu:
ARM: mvebu: add user LED support of Armada 370 RD
ARM: mvebu: add gpio fan support to Armada 370 RD
ARM: mvebu: Change vendor prefix for Intersil Corporation to isil
ARM: mvebu: use improved armada spi device tree compatible name
ARM: mvebu: add SSCG to Armada 370 Device Tree
ARM: mvebu: Add proper pin muxing on Armada 370 RD board
ARM: mvebu: Add proper pin muxing on Netgear ReadyNAS 104
ARM: mvebu: Add proper pin muxing on Netgear ReadyNAS 102
ARM: mvebu: Add proper pin muxing on the Armada 370 DB board
ARM: mvebu: Add proper pin muxing on Globalscale Mirabox board
ARM: mvebu: Add network pin mux configuration for the Armada 370 SoC
ARM: mvebu: Add RTC support for Armada 375
Olof Johansson [Wed, 24 Sep 2014 05:25:39 +0000 (22:25 -0700)]
Merge tag 'qcom-dt-for-3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom into next/dt
Merge "qcom DT changes for v3.18" from Kumar Gala:
Qualcomm ARM Based Device Tree Updates for v3.18
* Added APQ8084 dt support for clocks, serial, pinctrl, and IFC6540 board
* Added IPQ8064 dt support for basic SoC and AP148 board
* Added APQ8064 dt support for pinctrl, reset, SDHC, and multimedia clocks
* Added PMIC 8058 dt support on MSM8660, enables PMIC based power key,
keypad, rtc, and vibrator
* Added PMIC 8921 dt support on MSM8960, enables PMIC based power key,
keypad, and rtc
* tag 'qcom-dt-for-3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom:
ARM: DT: QCOM: apq8064: Add dma support for sdcc node
ARM: DT: apq8064: Add sdcc support via mcci driver.
ARM: dts: qcom: Add 8064 multimedia clock controller node
ARM: DT: APQ8064: Add node for ps_hold function in pinctrl
ARM: DT: APQ8064: Add pinctrl support
ARM: dts: qcom: Add TLMM DT node for APQ8084
ARM: dts: qcom: Add initial IFC6540 board device tree
ARM: dts: msm: Add 8058 PMIC to ssbi bus
ARM: dts: msm: Add 8921 PMIC to ssbi bus
ARM: qcom: Add initial IPQ8064 SoC and AP148 device trees
ARM: dts: qcom: Add APQ8084 serial port DT node
ARM: dts: qcom: Add APQ8084 Global Clock Controller DT node
Olof Johansson [Wed, 24 Sep 2014 05:11:05 +0000 (22:11 -0700)]
Merge tag 'dt-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/dt
Merge "omap dts changes for v3.18 merge window" from Tony Lindgren:
Changes for .dts files for omaps for v3.18 merge window:
- Updates for gta04 to add gta04a3 model
- Add support for Tehnexion TAO3530 boards
- Regulator names for beaglebone
- Pinctrl related updates for omap5, dra7 and am437
- Model name fix for sbc-t54
- Enable mailbox for various omaps
* tag 'dt-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (291 commits)
ARM: dts: OMAP2+: Add sub mailboxes device node information
ARM: dts: dra7-evm: Mark uart1 rxd as wakeup capable
ARM: dts: OMAP5 / DRA7: switch over to interrupts-extended property for UART
ARM: dts: AM437x: switch to compatible pinctrl
ARM: dts: DRA7: switch to compatible pinctrl
ARM: dts: OMAP5: switch to compatible pinctrl
ARM: dts: am335x-boneblack: Add names for remaining regulators
ARM: dts: sbc-t54: fix model property
ARM: dts: omap5.dtsi: add DSS RFBI node
ARM: dts: omap3: Add HEAD acoustics omap3-ha.dts and omap3-ha-lcd.dts (TAO3530 based)
ARM: dts: omap3: Add Technexion Thunder support (TAO3530 SOM based)
ARM: dts: omap3: Add Technexion TAO3530 SOM omap3-tao3530.dtsi
ARM: OMAP2+: tao3530: Add pdata-quirk for the mmc2 internal clock
ARM: OMAP2+: board-generic: add support for AM57xx family
ARM: dts: dra72-evm: Add tps65917 PMIC node
ARM: dts: dra72-evm: Enable I2C1 node
Linux 3.17-rc3
unicore32: Fix build error
vexpress/spc: fix a build warning on array bounds
spi: sh-msiof: Fix transmit-only DMA transfers
...
Stephen Boyd [Fri, 19 Sep 2014 23:50:51 +0000 (16:50 -0700)]
ARM: DT: msm8960: Add sdcc nodes
Add the sdcc nodes to support the SD card controller using pl180
mmci driver. We also add a temporary fixed regulator until the
regulator driver is mainlined.
Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kumar Gala <galak@codeaurora.org>
Stephen Boyd [Fri, 19 Sep 2014 23:50:50 +0000 (16:50 -0700)]
ARM: DT: msm8660: Add sdcc nodes
Add the sdcc nodes to support the SD card controller using pl180
mmci driver. We also add a temporary fixed regulator until the
regulator driver is mainlined.
Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kumar Gala <galak@codeaurora.org>
ARM: dts: rockchip: Remove "regulator-always-on" in vcc_rmii for Radxa Rock
On Rockchip RK3188 SoCs the platform driver emac_rockchip is used. This variant driver
enables this regulator when the device driver is loaded. The phy no longer needs
to be always on.
ARM: dts: rockchip: fix swapped Radxa Rock pinctrl references
The host and otg regulator pinctrl settings got swapped, making the host
reference the otg pinctrl and the other way round. The actual pins are
correct (gpio0-3 for host and gpio2-31 for otg).
ARM: dts: imx6: make gpt per clock can be from OSC
Original gpt per clk parent is from ipg_per clk which
may be scaled when system enter low bus mode, as ipg
clk will be lower in low bus mode, to keep system clk
NOT drift, select gpt per clk parent from OSC which
is at fixed freq always.
On i.mx6qdl, add a osc_per clk source for i.mx6q
TO > 1.0 and all i.MX6dl SoC.
Tim Harvey [Tue, 9 Sep 2014 06:07:30 +0000 (23:07 -0700)]
ARM: dts: imx: ventana: cleanup pinctrl groups
Follow the conventions for pinctrl:
- grouping pinctrl in logical alphabatized groups
- remove any pinctrl not being used by a driver or needed by user
- move iomuxc to bottom of file for readability
Signed-off-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
The general device-tree rule is to not include nodes that do not have a driver
or bindings in a dts/dtsi. Remove the place-holder nodes from the Gateworks
Ventana boards until a time that a driver with proper bindings exists.
Signed-off-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
ARM: dts: imx28-tx28: remove spidev labels and add third instance of spidev
The labels on the spidev nodes are not used and not required, so
remove them. The TX28 supports 3 chipselects on the SPI
interface. Make all those chipselects available to the user.
ARM: dts: imx6qdl-sabresd: Configure the pins locally
Passing '0x80000000' to the pin configuration means that kernel will skip the
IOMUXC_SW_PAD_CTL configuration and will use whathever values come from the
bootloader.
Instead of relying on the bootloader setup, let's configure it in the kernel to
have predictable settings.
'0x1b0b0' is the default POR value for all these pins and has also been verified
that the pins are using this value by manually inspecting the IOMUXC_SW_PAD_CTL
registers, so no functional change has been made.
Rabeeh Khoury [Sat, 23 Aug 2014 09:11:47 +0000 (10:11 +0100)]
ARM: dts: hummingboard: gpio-ir on gpio 3,5
HummingBoard after rev 2.0 and the production one starting rev 3.0 uses
gpio 3,5 (EIM_DA5 pad) as the gpio infra red receiver input.
Since the original Carrier1 board is obsolete and we are retiring it,
update the DT file for this. This will mean IR reception will not
work on Carrier1 with this DT file.
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Stefan Agner [Mon, 18 Aug 2014 20:07:17 +0000 (22:07 +0200)]
ARM: dts: vf610-twr: Add USB support
Add USB support for Freescale Vybrid tower. The USB hosts over-current
protection signal is not connected to the PHY's over- current
protection, hence we need to disable it.
Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Stefan Agner [Mon, 18 Aug 2014 20:07:16 +0000 (22:07 +0200)]
ARM: dts: vf610-colibri: Add USB support
Add USB support for Colibri VF61 modules. The Colibri standard pinout
defines a pin for USB over-current. However, due to lack of pinmux
options, the USB hosts over-current protection signal of the Colibri
standard could not be connected to the PHY's over-current protection.
Hence we need to disable the over-current functionality of the USB
controller.
Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Stefan Agner [Mon, 18 Aug 2014 20:07:14 +0000 (22:07 +0200)]
ARM: dts: vf610: Add usbmisc for non-core registers
Add device tree node for usbmisc which controls the non-core USB
registers. This is required to use the property to disable the over-
current detection.
Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Stefan Agner [Mon, 18 Aug 2014 20:07:11 +0000 (22:07 +0200)]
ARM: dts: vf610: Add USB PHY and controller
This adds USB PHY and USB controller nodes. Vybrid SoCs have two
independent USB cores which each supports DR (dual role). However,
real OTG is not supported since the OTG ID pin is not available.
The PHYs are located within the anadig register range, hence we need
to change the length of the anadig registers.
Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
[ukl: rebase from ancient kernel version] Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Lucas Stach [Wed, 23 Jul 2014 17:29:11 +0000 (19:29 +0200)]
ARM: dts: imx6qdl-sabresd: add always on pcie regulator
Everything in the PCI specification assumes devices to be
enumerable on startup. This is only possible if they have
power available.
A future improvement may allow this regulator to be switched
off for D3hot and D3cold power states, but there is a lot
of work to do the pcie host controller side for this to work.
To keep things simple always enable the regulator for now.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Stefan Agner [Fri, 18 Jul 2014 14:25:18 +0000 (16:25 +0200)]
ARM: dts: vf610-colibri: split device tree for carrier boards
The Colibri VF61 is a module which needs a carrier board to actually
run. Different carrier board have different hardware support, hence
we should reflect this in the device tree files. This patch adds the
Colibri Evaluation Board, which supports almost all peripherals
defined in the Colibri standard.
Also align the compatible naming, file splitting and file naming with
the scheme which was choosen for the Tegra based modules.
Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
The imx weim driver is used by some mx27/mx1 boards, so let's enable it by
default.
Generated this patch by doing:
- make imx_v4_v5_defconfig
- make menuconfig and manually select CONFIG_IMX_WEIM
- make savedefconfig
- cp defconfig arch/arm/configs/imx_v4_v5_defconfig
ARM: imx: source gpt per clk from OSC for system timer
On i.MX6Q TO > 1.0, i.MX6DL and i.MX6SX, gpt per clock
can be from OSC instead of ipg_per, as ipg_per's rate
may be scaled when system enter low bus mode, to keep
system timer NOT drift, better to make gpt per clock
at fixed rate, here add support for gpt per clock to
be from OSC which is at fixed rate always.
There are some difference on this implementation of
gpt per clock source, see below for details:
i.MX6Q TO > 1.0: GPT_CR_CLKSRC, b'101 selects fix clock
of OSC / 8 for gpt per clk;
i.MX6DL and i.MX6SX: GPT_CR_CLKSRC, b'101 selects OSC
for gpt per clk, and we must enable GPT_CR_24MEM to
enable OSC clk source for gpt per, GPT_PR_PRESCALER24M
is for pre-scaling of this OSC clk, here set it to 8
to make gpt per clk is 3MHz;
i.MX6SL: ipg_per can be from OSC directly, so no need to
implement this new clk source for gpt per.
Add gpt_3m clock for i.mx6qdl, as gpt can source clock
from OSC, some i.MX6 series SOCs has fixed divider of
8 for gpt clock, so here add a fix clk of gpt_3m.
i.MX6Q TO1.0 has no gpt_3m option, so force it to be
from ipg_per.
ARM: imx: fix register offset of pll7_usb_host gate clock
There is a copy&paste error on register offset of pll7_usb_host gate
clock introduced by i.MX6 PLL bypass support patches. The error breaks
the ENET function, because it overwrites the pll6_enet gate bit.
Correct the offset for all i.MX6 clock drivers.
Thanks to Fugang Duan <B38611@freescale.com> for spotting the error.
Shawn Guo [Tue, 26 Aug 2014 15:06:33 +0000 (23:06 +0800)]
ARM: imx: remove ENABLE and BYPASS bits from clk-pllv3 driver
Since ENABLE and BYPASS bits of PLLs are now implemented as separate
gate and mux clocks by clock drivers, the code handling these two bits
can be removed from clk-pllv3 driver.
This is the same change for imx6sx clock driver as "ARM: imx6q: add BYPASS
support for PLL clocks" for imx6q. The difference is that only anaclk1
is available on imx6sx.
This is the same change for imx6sl clock driver as "ARM: imx6q: add BYPASS
support for PLL clocks" for imx6q. The difference is that only anaclk1
is available on imx6sl.
The imx6q clock driver currently hard-codes all PLL clocks to source
from OSC24M without BYPASS support. The patch adds the missing lvds_in
clock which is mutually exclusive with lvds_gate, and implements BYPASS
and BYPASS_CLK_SRC selection for PLL clocks as per Figure 10-3. Primary
Clock Generation in IMX6DQRM, i.e. both BYPASS_CLK_SRC and BYPASS bits
are implemented as mux clocks, and ENABLE bit of PLL clocks is
implemented as a gate clock after BYPASS mux.
Shawn Guo [Tue, 26 Aug 2014 07:06:33 +0000 (15:06 +0800)]
ARM: imx: add an exclusive gate clock type
There are a couple of gate clocks are mutually exclusive on i.MX6, i.e.
LVDSCLK1_IBEN and LVDSCLK1_OBEN. They cannot be enabled simultaneously.
This patches adds an exclusive gate clock type specifically for such
case. The clock driver will need to call imx_clk_gate_exclusive() to
register a gate clock with parameter exclusive_mask indicating the mask
of gate bits which are mutually exclusive to this gate clock.
Right now, it only handles the exclusive gate clocks which are defined
in a single hardware register, which is the case we're running into
today. But it can be extended to handle exclusive gate clocks defined
in different registers later if needed.
ARM: clk-imx6sl: correct the pxp and epdc axi clock selections
The parent clocks of IMX6SL_CLK_PXP_AXI_SEL and IMX6SL_CLK_EPDC_AXI_SEL
clocks are not the same. So split the epdc_pxp_sels into two different
clock selections 'pxp_axi_sels' and 'epdc_axi_sels'.
Shengjiu Wang [Fri, 8 Aug 2014 07:02:47 +0000 (15:02 +0800)]
ARM: clk-imx6q: refine clock tree for ESAI
There are three clock for ESAI, esai_extal, esai_ipg, esai_mem. Rename
'esai' to 'esai_extal', 'esai_ahb' to 'esai_mem', and add 'esai_ipg'.
Make the clock for ESAI more clear and align them with imx6sx.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Stefan Agner [Tue, 29 Jul 2014 14:20:28 +0000 (16:20 +0200)]
ARM: imx: clk-vf610: introduce clks_init_on
At the end of the boot process, the clock framework might disable
required main PLL's. So far, this was no issue since drivers
requested clocks, which are descended of the main PLL's (e.g.
pll1_pfd1, which provides the system clock).
To archive the full 500MHz system clock, DDR clock need to be a
descendant of PLL2 rather than PLL1 (DDRC_CLK_SEL set to 0). The
bootloader sets up the clocks accordingly before making use of
DDR at all. However, in Linux, there is no driver using PLL2,
which lead to PLL2 being disabled by the clock framework.
With this patch, we make sure that the main system clock and the
DDR clock are initially enabled and are kept enabled.
Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Jason Liu [Tue, 5 Nov 2013 04:03:18 +0000 (12:03 +0800)]
ARM: i.MX6: add more chip revision support
Add more revision support for the new i.MX6DQ tape-out (TO1.5). This
TO1.5 is the Rev 1.3 as documented in i.MX6DQ data sheet, because TO1.3
and TO1.4 are never revealed.
Signed-off-by: Jason Liu <r64343@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com> Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
projects / karo-tx-linux.git / log