Peter Chen [Mon, 4 Jul 2011 07:58:39 +0000 (15:58 +0800)]
ENGR00152493-1 mx6q: add usb function
Changes at MSL
- Add usb code for mx6q
- Usb host functions (keyboard and u-disk) are verified
- USB host low power mode and wakeup are supported
- defconfig for otg port is for host port
- Using upstream platform device register method
- Delete some useless code, and fix the warning during building
Signed-off-by: Peter Chen <peter.chen@freescale.com>
ENGR00152528-1 MX6Q, ENET: add enet support for mx6q
Add enet driver support for mx6q sabreauto board.
Since ENET reset lost it mac address, we have to generate
mac address in random.
The prefer way to set mac address is pass from kernel command line
by "fec_mac=${ethaddr}" for sabreauto.
Currently only support basic temperature reading,
after the tester write the calibration value into
fuse, we will need to improve the accuracy of this
thermal sensor, also, the cooling device will be
added later.
Currently only support temperature reading, and
since the chip need calibration, and they will
write the calibration parameter into fuse later,
we need to wait for it and improve this thermal
sensor's accuracy. Also, cooling device will be
added later.
ENGR00151891: MX50-Fix bug in exit from LPAPM mode.
When exiting from LPAPM mode, ARM clock is run at 266.67MHZ for
a few instructions while the voltage is still at 0.85V.
Fix this issue by setting the ARM-PODF divider before
switching the parent.
Zeng Zhaoming [Tue, 28 Jun 2011 02:23:16 +0000 (10:23 +0800)]
ENGR00139229-2 MX6: Bring up i.MX6 sabreauto with Quad cores
MSL code for bring up MX6 sabreauto board with Quad core.
Enable cpu core local timer, add reset and enable cpu core control,
and enable it in default config.
Merged from testbuild:imx6_bringup branch.
Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Jason Liu <r64343@freescale.com> Signed-off-by: Zeng Zhaoming <b32542@freescale.com> Merged-by: Zeng Zhaoming <b32542@freescale.com>
- With FB_POWERDOWN_DISABLE is set as the powerdown delay (disabling the EPDC
driver from powering down), the EPDC driver was having problems going into
suspend. Any request to blank the EPDC driver would result in a timeout
and an error status. And subsequent attempts to send updates to the driver
would fail, as the driver's power state was incorrect. This patch prompts
the EPDC driver to be disabled when the blanking state is changed to
FB_BLANK_POWERDOWN and FB_POWERDOWN_DISABLE is set. Resultingly, the correct
driver power state is maintained and suspend/resume works correctly.
Signed-off-by: Danny Nold <dannynold@freescale.com>
Danny Nold [Tue, 21 Jun 2011 02:51:03 +0000 (21:51 -0500)]
ENGR00151822 - EPDC fb: Prevent endless collision by managing FULL mode updates
When using SNAPSHOT update scheme, submitting FULL mode updates can easily
lead to an endlessly looping sequence of collisions if any updates are active
when the new FULL mode update is submitted. Thus, we must first flush any
updates out before submitting a new FULL mode update.
Signed-off-by: Danny Nold <dannynold@freescale.com>
Sammy He [Tue, 21 Jun 2011 16:08:22 +0000 (00:08 +0800)]
ENGR00151762 vpu: Fix system hang due to long time video playback on mx51
Fix system hang due to long time video playback. This issue is only
on i.MX51 platfrom due to changing vpu clock parent in vpu_enable/
disable. Set vpu clock parent to axi_a forever to fix it.
Danny Nold [Wed, 15 Jun 2011 14:11:51 +0000 (09:11 -0500)]
ENGR00151639 - EPDC fb: Memory for PxP workaround buffers may be reduced
- This patch changes the way that buffers are allocated and used for the
case where PxP alignment limitations are not met (a copy from the
update source buffer into a temporary buffer before initiating the
PxP processing task is required). Previously, a buffer was allocated
on a per-update basis, resulting in a large number of copy buffers. Now,
we allocate just one copy buffer that can be reused any time the PxP
alignment workaround is required. This is okay because it is assured
that only one PxP transaction can be prepared at a time.
Signed-off-by: Danny Nold <dannynold@freescale.com>
- When the powerdown delay is set to FB_POWERDOWN_DISABLE, the
mxc_epdc_fb_flush_updates() function does not execute correctly, always
resulting in a time out while waiting to receive a completion that signals
that all updates have completed. This causes long delays when changing the FB
mode, since a mode change will always result in a call to
mxc_epdc_fb_flush_updates().
Fixed this bug by creating a new mxc_epdc_fb_data variable to track whether
all active updates have completed. mxc_epdc_fb_flush_updates() now
keys off of this variable to determine whether to wait for all
active updates to complete.
Signed-off-by: Danny Nold <dannynold@freescale.com>
Danny Nold [Tue, 31 May 2011 21:23:48 +0000 (16:23 -0500)]
ENGR00144358 - EPDC fb: Fix race condition in how EPDC status is captured in IST
- Capture EPDC status registers up front in IST, rather than when-needed
during IST, to prevent potential race conditions where the status changes
mid-IST.
Signed-off-by: Danny Nold <dannynold@freescale.com>
- When synching update submission to EPDC end of frame (when tce_prevent is
defined), we should wait using wait_for_completion_timeout to prevent
hang/deadlock in case we don't receive completion.
- Added call in IST to disable end of frame interrupt upon receiving the
interrupt.
Signed-off-by: Danny Nold <dannynold@freescale.com>
Sammy He [Tue, 31 May 2011 09:49:24 +0000 (17:49 +0800)]
ENGR00144306-2 vpu: Add iram info to vpu platform data for each platform
Add iram info to vpu platform data for each platform in linux/arch folder.
Disable iram on MX51 and enable iram on MX53 platform.
And remove VPU_IRAM_SIZE usage.
Sammy He [Tue, 31 May 2011 09:48:12 +0000 (17:48 +0800)]
ENGR00144306-1 VPU: remove VPU IRAM config and add iram info to plat data.
One kernel image is requested, however, we need to enable iram
for performance improvement on mx53, and disable it on mx51 due
to known issue. So use platform data to pass vpu iram disable/enable
flag. And considering requested iram size also can be different per
requirement, iram size is also set in platform data.
Liu Ying [Tue, 24 May 2011 02:06:03 +0000 (10:06 +0800)]
ENGR00142551-3 MXC V4L2:Change IPU interface for triple buffer
This patch changes IPU interface for MXC V4L2 to align with
IPUv3 triple buffer support.
When V4L2 is used, we'll change to use double buffer for
display channel via internal framebuffer interface.
Liu Ying [Tue, 24 May 2011 02:04:02 +0000 (10:04 +0800)]
ENGR00142551-2 IPUv3 FB:Support HW triple buffer
This patch supports HW triple buffer for IPUv3
framebuffer.
1) Remove buf ready check in EOF irq handler, as we
think the swap logic will not fail for HW triple
buffer case.
2) When V4L2 output/overlay are used, switch to double
buffer mode.
3) Changes IPU interface for IPUv1 framebuffer to pass
building.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com> Signed-off-by: Jason Chen <b02280@freescale.com>
(cherry picked from commit 4ada3031e13207902f8c90b33c082759889cb22a)
Liu Ying [Tue, 24 May 2011 01:58:49 +0000 (09:58 +0800)]
ENGR00142551-1 IPUv3:Support triple buffer
This patch supports IPUv3 triple buffer.
Only channel 23, 27 and 28 are tested.
Test was done on MX51 BBG and MX53 SMD.
IPUv1 interface is changed accordingly
to pass building.
Liu Ying [Tue, 24 May 2011 01:57:46 +0000 (09:57 +0800)]
ENGR00143575 IPUv3:Align IDMAC BS with DMFC FIFO BS
This patch aligns IDMAC burst size and DMFC FIFO burst
size to get better performance and workarounds black
flash issue when playing video on DP-FG with full
screen mode at 1024x768M@60.
Anish Trivedi [Fri, 20 May 2011 16:51:01 +0000 (11:51 -0500)]
ENGR00143799 Add SCC RAM clock to dependency list for SAHARA clock tree
When ARM is in WAIT mode, the SCC RAM clock is disabled since
1 is written to the CCGR register by default. At that point, if SAHARA
tries to access a key or some other piece of data stored in the SCC RAM,
then it might hang.
To prevent this scenario, SCC RAM is added to dependency list
for SCC clock, and SCC clock is added to dependency list for SAHARA.
Yuxi Sun [Wed, 18 May 2011 06:02:45 +0000 (14:02 +0800)]
ENGR00143550 camera: change camera platform data name and remove unused function
Change camera platform data name from mxc_camera_platform_data to
fsl_mxc_camera_platform_data in accordence with include/linux/fsl_devices.h
and remove unused function gpio_sensor_active(),gpio_sensor_inactive().
- Removed __initdata from regulator_init_data structure declaration. This
protects the MAX17135 regulator from having its structure overwritten, which
was causing a bug when writing large chunks of memory.
Signed-off-by: Danny Nold <dannynold@freescale.com>
Liu Ying [Thu, 12 May 2011 12:18:25 +0000 (20:18 +0800)]
ENGR00143309 IPUv3fb:Set default yres_virtual to be 3*yres
This patch sets framebuffer yres_virtual to be 3*yres defaultly.
Before this patch is applied, the yres_virtual will be changed
to yres when hdmi cable is hot plugged out and in, which
reduces yres_virtual to yres and pan display mechanism cannot
work well.
In set_voltage function, all voltages are not in microvolts.
Hence set_voltage function was failing. Change all voltages in
the function to be in microvolts.
Liu Ying [Thu, 12 May 2011 09:59:34 +0000 (17:59 +0800)]
ENGR00142683 IPUv3:Increase IDMAC BS for RGBP and DMFC BS
This patch increases IDMAC burst size from 16 pixels to
32 pixels for RGBP pixel format and increases DMFC burst
size to 128 pixels to workaround 1080P60 display video
black flash issue.
Danny Nold [Tue, 3 May 2011 18:00:55 +0000 (13:00 -0500)]
ENGR00142950-3 - MSL: Port EPDC/PxP driver support to 2.6.38
- Ported EPDC driver MSL layer code to 2.6.38
- Ported PxP driver MSL layer code to 2.6.38
- Ported Maxim 17135 EPD PMIC driver MSL layer code to 2.6.38
Signed-off-by: Danny Nold <dannynold@freescale.com>
Danny Nold [Tue, 3 May 2011 16:12:19 +0000 (11:12 -0500)]
ENGR00142950-1 - EPDC fb: Add support for 2.6.38
- Bring EPDC driver up-to-date
- Add mxcfb_epdc_kernel.h
- Change structure definitions from mxc_ to imx_ where needed to
match platform structure names
Signed-off-by: Danny Nold <dannynold@freescale.com>
ENGR00142679 SCC2 and SAHARA: changes to support loadable modules
To allow SCC2 and SAHARA drivers to work as loadable modules, needed
to add GPL license to SAHARA driver, export a couple of functions
from SCC2 driver, and the following data buffer mapping change in
SAHARA driver:
When compiled as a loadable module, a data buffer to be DMA'ed in the
SAHARA driver may not be in the kernel direct-mapped region but in
the "Kernel module space" between TASK_SIZE and high_memory-1
(see http://www.arm.linux.org.uk/developer/memory.txt). In this
scenario, the driver canno simply use the __pa macro to obtain
the physical address. It must walk the page tables to find the
page and use the page_to_phys function to find the physical
address that corresponds to the data buffer.
Jason Chen [Thu, 28 Apr 2011 03:23:36 +0000 (11:23 +0800)]
ENGR00141552 ipuv3: fix display pin's power leak
If you disable display, the display port's pin may keep high voltage which
may cause power leakage. Fix this issue by make all pin go into low level
after display disable.
Jason Chen [Tue, 19 Apr 2011 08:33:28 +0000 (16:33 +0800)]
ENGR00141152-1 header file: make default display option
After this patch, default display for below platforms:
mx51 bbg: DVI-XGA on DI0
mx53 ard: LVDS-XGA on DI0
mx53 evk: CLAA-WVGA on DI0
mx53 loco: VGA-XGA on DI1
mx53 smd: LVDS-XGA on DI1
The default options will work if you do not enter other video cmdline options.
For platform need enable other drivers, it will enable it automatically.
For example, under default option, mx53 loco will enable tve-vga driver
automatically; before this patch, it need add 'vga' to cmdline to enable it.
And 'di1_primary' option also will be enabled automatically if need.
If you want to overwrite the default option, please refer to below:
Zhou, Jie [Wed, 2 Mar 2011 17:02:40 +0000 (01:02 +0800)]
ENGR00140050 GPU: workaround hang with heavy bus loading
The GPU hang when run two cubes together with one video playback.
According to the suggestion from AMD, we'd better not read register
when GPU active, especially for CP block.
ENGR00142296-2 SRTC: Upgrade driver to kernel version 2.6.38
RTC-DEV ioctl interface changed, which required a definition
of new callback mxc_rtc_alarm_irq_enable in SRTC driver.
Also, added a sync call to mxc_rtc_interrupt after a write to
LP domain register to make sure we wait 3 clock cycles in order
for the write to complete, as required by the hardware.
projects / karo-tx-linux.git / log