Robert Jarzmik [Tue, 6 Jan 2015 20:45:38 +0000 (21:45 +0100)]
clk: pxa: add pxa3xx clock driver
Move pxa25x clock drivers from arch/arm/mach-pxa to driver/clk.
In the move :
- convert to new clock framework legacy clocks
- provide clocks as before for platform data based boards
- provide clocks through devicetree with clk-pxa-dt
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Michael Turquette <mturquette@linaro.org>
Soren Brinkmann [Tue, 27 Jan 2015 19:05:27 +0000 (11:05 -0800)]
clk: zynq: Force CPU_2X clock to be ungated
The CPU_2X clock does not have a classical in-kernel user, but is,
amongst other things, required for OCM and debug access. Make sure this
clock is not mistakenly disabled during boot up by enabling it in the
platform's clock driver.
Merge tag 'sunxi-clocks-for-3.20' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-next
Allwinner clock changes for 3.20
The set of clock changes for the 3.20 merge window, with mostly:
- Some PLL fixes for the A80 and A31
- The MMC custom phase functions are removed, and moved over to the generic
phase API.
- Add the A80 MMC clocks
Some DT changes slipped here as well, to preserve bisectability.
Merge tag 'v3.20-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next
The two big changes are the additional of the watchdog clock, which
we currently only "fake" as the clock gate control is living in a
very strange place, but the watchdog driver needs to read the clock
rate from it and the setting of rk3288 plls to slow mode upon suspend.
Other than that some more exported clocks and a CLK_SET_RATE_PARENT
flag for the uart clocks.
Stephen Boyd [Thu, 22 Jan 2015 23:40:20 +0000 (15:40 -0800)]
clk: ti: Drop use of clk-private.h
These modules don't need to include clk-private.h. Replace the
include with clk.h because these modules are clock consumers and
also include clk-provider.h in clk/ti.h because struct
clk_hw_omap has a struct clk_hw embedded in it.
Cc: Tero Kristo <t-kristo@ti.com> Cc: Tony Lindgren <tony@atomide.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Reviewed-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
Maxime Ripard [Tue, 20 Jan 2015 21:23:43 +0000 (22:23 +0100)]
clk: Export phase functions
The phase setter and getter were not exported until now, which was causing
build breakages when callers were compiled as module. Export these two
functions.
Reported-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
Rajendra Nayak [Tue, 20 Jan 2015 02:05:32 +0000 (18:05 -0800)]
dt-bindings: Add #defines for IPQ806x lpass clock control
Add defines to make more human readable numbers for the lpass
clock controller found on IPQ806x SoCs. Also remove the PLL4
define in gcc to avoid #define conflicts because that clock
doesn't exist in gcc, instead it lives in lcc.
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
[sboyd@codeaurora.org: Split off into separate patch] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Tested-by: Kenneth Westfield <kwestfie@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
Stephen Boyd [Tue, 20 Jan 2015 02:05:31 +0000 (18:05 -0800)]
clk: qcom: Add simple regmap based muxes
Add support for muxes that use regmap instead of readl/writel
directly. We don't support as many features as clk-mux.c, but
this is good enough to support getting and setting parents.
Adding a table based lookup can be added in the future if needed.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Tested-by: Kenneth Westfield <kwestfie@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
Stephen Boyd [Tue, 20 Jan 2015 02:05:29 +0000 (18:05 -0800)]
clk: divider: Make generic for usage elsewhere
Some devices don't use mmio to interact with dividers. Split out the
logic from the register read/write parts so that we can reuse the
division logic elsewhere.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Tested-by: Kenneth Westfield <kwestfie@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
Stephen Boyd [Tue, 20 Jan 2015 02:05:28 +0000 (18:05 -0800)]
clk: Add __clk_mux_determine_rate_closest
Some clock drivers want to find the closest rate on the input of
a mux instead of a rate that's less than or equal to the desired
rate. Add a generic mux function to support this.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Tested-by: Kenneth Westfield <kwestfie@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
Some of the clks can be registered & unregistered before the clk related debugfs
entries are initialized at late_initcall. In the unregister path checking for only
dentry before clk_debug_init() would lead dangling pointers in the debug clk list,
because the list is already populated in register path and the clk pointer freed in
unregister path.
The side effect of not removing it from the list is either a null pointer
dereference or if lucky to boot the system, the number of clk entries in
debugfs disappear.
We could add more checks like if (inited && !clk->dentry) but just removing
the check for dentry made more sense as debugfs_remove_recursive() seems to be
safe with null pointers. This will ensure that the unregistering clk would be
removed from the debug list in all the code paths.
Hans de Goede [Sat, 24 Jan 2015 11:56:32 +0000 (12:56 +0100)]
sunxi: clk: Set sun6i-pll1 n_start = 1
For all pll-s on sun6i n == 0 means use a multiplier of 1, rather then 0 as
it means on sun4i / sun5i / sun7i. n_start = 1 is already correctly set
for sun6i pll6, but was missing for pll1, this commit fixes this.
Cc: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Hans de Goede [Sat, 24 Jan 2015 11:56:31 +0000 (12:56 +0100)]
clk: sunxi: rewrite sun9i_a80_get_pll4_factors()
The old implementation of sun9i_a80_get_pll4_factors() has several issues,
it checks against 256 / 512 in various places where it should use 255 / 511,
it does the wrong thing for low frequencies which are an even multiple of
6 MHz, e.g. if you ask it for 72 MHz it will result in 144 Mhz, and it does
not take into account that n must be at least 12. Moreover it is quite hard
to read / follow it.
This commit rewrites it to be correct in all cases, and makes it much easier
to follow the code / to read.
Cc: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Thierry Reding [Wed, 21 Jan 2015 16:13:00 +0000 (17:13 +0100)]
clk: Introduce clk_has_parent()
This new function is similar to clk_set_parent(), except that it doesn't
actually change the parent. It merely checks that the given parent clock
can be a parent for the given clock.
A situation where this is useful is to check that a particular setup is
valid before switching to it. One specific use-case for this is atomic
modesetting in the DRM framework where setting a mode is divided into a
check phase where a given configuration is validated before applying
changes to the hardware.
Cc: Russell King <linux@arm.linux.org.uk> Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
Heiko Stuebner [Tue, 20 Jan 2015 20:06:55 +0000 (21:06 +0100)]
clk: rockchip: add a dummy clock for the watchdog pclk on rk3288
The pclk supplying the watchdog is controlled via the SGRF register area.
Currently we don't have any clock-type handling external clock bits like
this one. Additionally the SGRF isn't even writable in every boot mode.
But still the clock control is available and in the future someone might
want to use it. Therefore define a simple clock for the time being so
that the watchdog driver can read its rate.
Peter Griffin [Tue, 20 Jan 2015 15:32:41 +0000 (15:32 +0000)]
clk: st: STiH410: Fix pdiv and fdiv divisor when setting rate
Debugging eMMC on upstream kernels it has been noticed that when the
targetpack configures MMC0 clock to 200Mhz (required to switch to
HS200) then everything works OK. However if the kernel sets the
clock rate using clk_set_rate, then the eMMC card initialisation
fails with timeouts. Lower clock speeds (the default being 50Mhz)
work ok, but they we fail to get good eMMC transfer rates.
Looking through the vendor kernel clock driver reveals Giuseppe
had already fixed this issue, but the patch hasn't made its way
upstream.
The issue is fixed by changing the logic to manage the pdiv and
fdiv divisors used for setting the rate inside the flexgen driver code.
Pdiv is mainly targeted for low freq results, while fdiv should be
used for divs =< 64. The other way can lead to 'duty cycle'
issues.
I have changed the original patch to keep the original behaviour
in cases where the div is >64 which matches the original comment
and patch description more closely. Although no clocks appear to hit
this case currently when booting an upstream kernel.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
Tang Yuantian [Thu, 15 Jan 2015 06:03:41 +0000 (14:03 +0800)]
clk: ppc-corenet: rename driver to clk-qoriq
Freescale introduced new ARM-based socs which using the compatible
clock IP block with PowerPC-based socs'. So this driver can be used
on both platforms.
Updated relevant descriptions and renamed this driver to better
represent its meaning and keep the function of driver untouched.
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
Tony Lindgren [Tue, 13 Jan 2015 22:51:28 +0000 (14:51 -0800)]
clk: ti: Initialize clocks for dm816x
The clocks on ti81xx are not compatible with omap3. On dm816x
the clock source is a FAPLL (Flying Adder PLL), and on dm814x
there seems to be an APLL (All Digital PLL).
Let's fix up things for dm816x in preparation for adding the
FAPLL support. As we already have a dummy ti81xx_dt_clk_init()
in place, let's use that for now to avoid adding a dependency
to the omap patches.
Later on if somebody adds dm814x support we can split the
ti81xx_dt_clk_init() clock init function as needed.
Cc: Brian Hutchinson <b.hutchman@gmail.com> Cc: Paul Walmsley <paul@pwsan.com> Cc: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
Tony Lindgren [Tue, 13 Jan 2015 22:51:27 +0000 (14:51 -0800)]
clk: ti: Add support for FAPLL on dm816x
On dm816x the clocks are sourced from a FAPLL (Flying Adder PLL)
that does not seem to be used on the other omap variants.
There are four instances of the FAPLL on dm816x that each have three
to seven child synthesizers.
I've set up the FAPLL as a single fapll.c driver. Later on we could
potentially have the PLL code generic. To do that, we would have to
consider the following:
1. Setting the PLL to bypass mode also sets the child synthesizers
into bypass mode. As the bypass rate can also be generated by
the PLL in regular mode, there's no way for the child synthesizers
to detect the bypass mode based on the parent clock rate.
2. The PLL registers control the power for each of the child
syntheriser.
Note that the clocks are currently still missing the set_rate
implementation so things are still running based on the bootloader
values. That's OK for now as most of the outputs have dividers and
those can be set using the existing TI component clock code.
I have verified that the extclk rates are correct for a few clocks,
so adding the set_rate support should be fairly trivial later on.
This code is partially based on the TI81XX-LINUX-PSP-04.04.00.02
patches published at:
Cc: Brian Hutchinson <b.hutchman@gmail.com> Cc: Paul Walmsley <paul@pwsan.com> Cc: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
Sergei Shtylyov [Wed, 24 Dec 2014 14:43:27 +0000 (17:43 +0300)]
clk-gate: fix bit # check in clk_register_gate()
In case CLK_GATE_HIWORD_MASK flag is passed to clk_register_gate(), the bit #
should be no higher than 15, however the corresponding check is obviously off-
by-one.
Fixes: 045779942c04 ("clk: gate: add CLK_GATE_HIWORD_MASK") Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
Kevin Hao [Wed, 3 Dec 2014 08:53:53 +0000 (16:53 +0800)]
clk: ppc-corenet: fix section mismatch warning
In order to fix the following section mismatch warning:
WARNING: drivers/clk/built-in.o(.data+0xe4): Section mismatch in reference from the variable ppc_corenet_clk_driver to the function .init.text:ppc_corenet_clk_probe()
The variable ppc_corenet_clk_driver references
the function __init ppc_corenet_clk_probe()
If the reference is valid then annotate the
variable with __init* or __refdata (see linux/init.h) or name the variable:
*_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console
WARNING: drivers/clk/built-in.o(.data+0x10c): Section mismatch in reference from the variable ppc_corenet_clk_driver to the variable .init.rodata:ppc_clk_ids
The variable ppc_corenet_clk_driver references
the variable __initconst ppc_clk_ids
If the reference is valid then annotate the
variable with __init* or __refdata (see linux/init.h) or name the variable:
*_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console
We can't just add the __init annotation to ppc_corenet_clk_driver or
remove the __init from ppc_corenet_clk_probe() and ppc_clk_ids.
So choose to use CLK_OF_DECLARE to scan and init the clock devices.
Signed-off-by: Kevin Hao <haokexin@gmail.com> Acked-by: Scott Wood <scottwood@freescale.com> Acked-by: Michael Turquette <mturquette@linaro.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
Kevin Hao [Wed, 3 Dec 2014 08:53:52 +0000 (16:53 +0800)]
powerpc: call of_clk_init() from time_init()
So the boards which has COMMON_CLK enabled don't have to
invoke this in its board specific file.
Signed-off-by: Kevin Hao <haokexin@gmail.com> Acked-by: Scott Wood <scottwood@freescale.com> Acked-by: Michael Turquette <mturquette@linaro.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
Chen-Yu Tsai [Tue, 20 Jan 2015 15:46:31 +0000 (23:46 +0800)]
clk: sunxi: Add driver for A80 MMC config clocks/resets
On the A80 SoC, the 4 mmc controllers each have a separate register
controlling their register access clocks and reset controls. These
registers in turn share a ahb clock gate and reset control.
This patch adds a platform device driver for these controls. It
requires both clocks and reset controls to be available, so using
CLK_OF_DECLARE might not be the best way.
Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Chen-Yu Tsai [Sat, 17 Jan 2015 05:19:26 +0000 (13:19 +0800)]
clk: sunxi: Add mod0 and mmc module clock support for A80
The module 0 style clocks, or storage module clocks as named in the
official SDK, are almost the same as the module 0 clocks on earlier
Allwinner SoCs. The only difference is wider mux register bits.
As with earlier Allwinner SoCs, mmc module clocks are a special case
of mod0 clocks, with phase controls for 2 child clocks, output and
sample.
This patch adds support for both.
Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
clk: exynos-audss: Fix memory leak on driver unbind or probe failure
The memory allocated by basic clock divider/gate/mux (struct clk_gate,
clk_divider and clk_mux) was leaking. During driver unbind or probe
failure the driver only unregistered the clocks.
Use clk_unregister_{gate,divider,mux} to release all resources.
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
clk: Add clk_unregister_{divider, gate, mux} to close memory leak
The common clk_register_{divider,gate,mux} functions allocated memory
for internal data which wasn't freed anywhere. Drivers using these
helpers could only unregister clocks but the memory would still leak.
Add corresponding unregister functions which will release all resources.
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
The commit 646cafc6 (clk: Change clk_ops->determine_rate to
return a clk_hw as the best parent) opens a possibility for
null pointer dereference, fix this.
Signed-off-by: Stanimir Varbanov <svarbanov@mm-sol.com> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
That commit tried to fix the section mismatch warning by moving the
ppc_corenet_clk_driver struct to init section. This is definitely wrong
because the kernel would free the memories occupied by this struct
after boot while this driver is still registered in the driver core.
The kernel would panic when accessing this driver struct.
Cc: stable@vger.kernel.org # 3.17 Signed-off-by: Kevin Hao <haokexin@gmail.com> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
Chen-Yu Tsai [Tue, 13 Jan 2015 01:37:23 +0000 (09:37 +0800)]
clk: sunxi: Add a common setup function for mmc module clocks
The only difference between module clocks on different platforms is the
width of the mux register bits and the valid values, which are passed in
through struct factors_data. The phase clocks parts are identical.
This patch generalizes the setup function, so most of the code can be
reused when adding sun9i support, which has a wider mux register.
Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Maxime Ripard [Sun, 7 Dec 2014 16:43:04 +0000 (17:43 +0100)]
clk: sunxi: Rework MMC phase clocks
Instead of having three different clocks for the main MMC clock and the two
phase sub-clocks, which involved having three different drivers sharing the
same register, rework it to have the same single driver registering three
different clocks.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Chen-Yu Tsai <wens@csie.org> Tested-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Mike Turquette <mturquette@linaro.org>
The "smemc" clock is removed on BG2Q SoCs. In fact, bit19 of clkenable
register is for nfc. Current code use bit19 for non-exist "smemc"
incorrectly, this prevents eMMC from working due to the sdhci's
"core" clk is still gated.
Boris Brezillon [Tue, 13 Jan 2015 14:44:06 +0000 (15:44 +0100)]
clk: at91: keep slow clk enabled to prevent system hang
All slow clk users are not properly claiming it (get + prepare + enable)
before using it.
If all users properly claiming this clock release it, the clock is
disabled, but faulty users still depends on it, and the system hangs.
This fix prevents the slow clock from being disabled, and should solve the
hanging issue, but offending drivers should be patched to properly claim
this clock.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Reported-by: Bo Shen <voice.shen@atmel.com> Cc: stable@vger.kernel.org Signed-off-by: Michael Turquette <mturquette@linaro.org>
Merge tag 'v3.19-rockhip-clkfixes1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-fixes
- two currently unused clocks that need to stay enabled
- fix the lock bit locations of the rk3066 plls
- fix rk3288 core divider values to the ones actually
specified by the soc vendor
Kever Yang [Thu, 13 Nov 2014 07:22:36 +0000 (15:22 +0800)]
clk: rockchip: add clock ID for usbphy480m_src
There are 3 different parent clock from different usbphy,
all of them are fixed 480MHz, it is not able to auto select
by clock core to the 2nd and the 3rd parent.
For different use case for different board, we may need to
select different usbphy clock out as parent manually.
Add the clock ID for it so that we can use in dts.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Sergei Shtylyov [Tue, 6 Jan 2015 22:39:52 +0000 (01:39 +0300)]
clk: shmobile: Add R-Car Gen2 ADSP clock support
Add the ADSP clock support to the R-Car generation 2 CPG driver. This clock
gets derived from PLL1. The layout of the ADSPCKCR register is similar to
those of the clocks supported by the 'clk-div6' driver but the divider encoding
is non-linear, so can't be supported by that driver...
Based on the original patch by Konstantin Kozhevnikov
<konstantin.kozhevnikov@cogentembedded.com>.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Sergei Shtylyov [Mon, 5 Jan 2015 21:25:08 +0000 (00:25 +0300)]
clk: shmobile: Add R-Car Gen2 RCAN clock support
Add the RCAN clock support to the R-Car generation 2 CPG driver. This clock
gets derived from the USB_EXTAL clock, dividing it by 6. The layout of the
RCANCKCR register is similar to those of the clocks supported by the 'clk-div6'
driver but has no divider field, and so can't be supported by that driver...
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
clk: shmobile: div6: Avoid changing divisor in .disable()
While DIV6 clocks require the divisor field to be non-zero when stopping
the clock, some clocks (e.g. ZB on sh73a0) fail to be re-enabled later
if the divisor field is changed when stopping the clock.
The reason for this is unknown.
To fix this, do not touch the divisor field if it's already non-zero.
On kzm9g, the smsc911x Ethernet controller is connected to the sh73a0
Bus State Controller, which is clocked by the ZB clock. Without this
fix, if the ZB clock is disabled during system suspend, and re-enabled
during resume, the kernel locks up when the smsc911x driver tries to
access the Ethernet registers.
Chen-Yu Tsai [Tue, 6 Jan 2015 02:35:12 +0000 (10:35 +0800)]
clk: sunxi: Propagate rate changes to parent for mux clocks
The cpu clock on sunxi machines is just a mux clock, which is normally
fed by the main PLL, but can be muxed to the main or low power oscillator.
Make the mux clock propagate rate changes to its parent, so we can
change the clock rate of the PLL, and thus actually implement rate
changing on the cpu clock.
This patch also removes the no reparenting limit.
Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Hans de Goede [Sat, 20 Dec 2014 10:36:49 +0000 (11:36 +0100)]
clk: sunxi: Make the mod0 clk driver also a platform driver
With the prcm in sun6i (and some later SoCs) some mod0 clocks are instantiated
through the mfd framework, and as such do not work with of_clk_declare, since
they do not have registers assigned to them yet at of_clk_declare init time.
Silence the error on not finding registers in the of_clk_declare mod0 clk
setup method, and also register mod0-clk support as a platform driver to work
properly with mfd instantiated mod0 clocks.
Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Doug Anderson [Mon, 22 Dec 2014 19:31:48 +0000 (11:31 -0800)]
clk: rockchip: rk3288: Make s2r reliable by switching PLLs to slow mode
We've been seeing some crashes at resume time on rk3288-based systems.
On some machines they simply never wake up from suspend. Symptoms
include:
- System clearly got to sleep OK. Power consumption is low, the PWM
for the PWM regulator has stopped, and the "global_pwroff" output
shows that the system is down.
- When system tries to wake up power consumption goes up.
- No kernel resume code (which was left in PMU SRAM) ran. We added
some basic logging to this code (write to a location in SRAM right
at resume time) and didn't see the logging run.
It appears that we can fix the problem by slowing down APLL before we
suspend. On the system I tested things seemed reliable if I disabled
1.8GHz and 1.7GHz. The Mask ROM itself tries to slow things down
(which is why PLLs are in slow mode by the time we get to the kernel),
but apparently it is crashing before it even gets there.
We'll be super paranoid and not just go down to 1.6GHz but we'll match
what the Mask ROM seems to be doing and go into slow mode. We'll also
be safe and put all PLLs (not just APLL) into slow mode (well, except
DPLL which is needed for SDRAM). We'll even put NPLL into slow mode
which the Mask ROM didn't do (not that it's used for much important
stuff at early resume time).
Note that the old Rockchip reference code did something just like
this, though they jammed it into pm.c instead of putting it in the
syscore ops of the clock driver.
Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Heiko Stuebner [Thu, 18 Dec 2014 19:06:57 +0000 (20:06 +0100)]
clk: rockchip: fix rk3288 cpuclk core dividers
Commit 0e5bdb3f9fa5 (clk: rockchip: switch to using the new cpuclk type
for armclk) didn't take into account that the divider used on rk3288
are of the (n+1) type.
The rk3066 and rk3188 socs use more complex divider types making it
necessary for the list-elements to be the real register-values to write.
Therefore reduce divider values in the table accordingly so that they
really are the values that should be written to the registers and match
the dividers actually specified for the rk3288.
Reported-by: Sonny Rao <sonnyrao@chromium.org> Fixes: 0e5bdb3f9fa5 ("clk: rockchip: switch to using the new cpuclk type for armclk") Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Doug Anderson <dianders@chromium.org> Cc: stable@vger.kernel.org
Heiko Stuebner [Wed, 24 Dec 2014 13:31:06 +0000 (14:31 +0100)]
clk: rockchip: fix rk3066 pll lock bit location
The bit locations indicating the locking status of the plls on rk3066 are
shifted by one to the right when compared to the rk3188, bits [7:4] instead
of [8:5] on the rk3188, thus indicating the locking state of the wrong pll
or a completely different information in case of the gpll.
The recently introduced pll init code exposed that problem on some rk3066
boards when it tried to bring the boot-pll value in line with the value
from the rate table.
Fix this by defining separate pll definitions for rk3066 with the correct
locking indices.
Hans de Goede [Sun, 23 Nov 2014 13:38:07 +0000 (14:38 +0100)]
clk: sunxi: Give sunxi_factors_register a registers parameter
Before this commit sunxi_factors_register uses of_iomap(node, 0) to get
the clk registers. The sun6i prcm has factor clocks, for which we want to
use sunxi_factors_register, but of_iomap(node, 0) does not work for the prcm
factor clocks, because the prcm uses the mfd framework, so the registers
are not part of the dt-node, instead they are added to the platform_device,
as platform_device resources.
This commit makes getting the registers the callers duty, so that
sunxi_factors_register can be used with mfd instantiated platform device too.
While at it also add error checking to the of_iomap calls.
This commit also drops the __init function from sunxi_factors_register since
platform driver probe functions are not __init.
Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Chen-Yu Tsai [Wed, 26 Nov 2014 07:16:52 +0000 (15:16 +0800)]
clk: sunxi: unify sun6i AHB1 clock with proper PLL6 pre-divider
This patch unifies the sun6i AHB1 clock, originally supported
with separate mux and divider clks. It also adds support for
the pre-divider on the PLL6 input, thus allowing the clock to
be muxed to PLL6 with proper clock rate calculation.
Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Chen-Yu Tsai [Mon, 24 Nov 2014 10:05:15 +0000 (18:05 +0800)]
clk: sunxi: Remove ahb1_sdram from sun6i/sun8i protected clocks list
The ahb1_sdram clock gate is only used for accessing the sdram
controller's registers over the bus. It is not used for actually clock
the controller or the dram, hence it does not need to be protected.
This also gets rid of the problem when the protected ahb1_sdram gate
is prepared/enabled while it is still an orphan, and the operation
is not propagated to the correct parent.
This was confirmed on my A23 tablet and my A31 Hummingbird.
Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Romain Perier [Fri, 12 Dec 2014 17:50:39 +0000 (17:50 +0000)]
clk: rockchip: Fix clock gate for rk3188 hclk_emem_peri
Do not disable clock gate "hclk_emem_peri", otherwise EMAC clocks no longer work
and it breaks ethernet on RK3066 and RK3188. It fixes a regression introduced by
commit 78eaf6095cc7 ("clk: rockchip: disable unused clocks").
Julien CHAUVEAU [Fri, 12 Dec 2014 21:05:52 +0000 (22:05 +0100)]
clk: rockchip: add CLK_IGNORE_UNUSED flag to fix rk3066/rk3188 USB Host
This patch adds CLK_IGNORE_UNUSED flag to hclk_usb_peri, hclk_usbotg0
and hclk_usbotg1 because these clocks must remain enabled to use the
USB controllers in host mode.
This fixes a regression introduced by commit 78eaf6095cc7
("clk: rockchip: disable unused clocks").
Doug Anderson [Thu, 4 Dec 2014 21:33:05 +0000 (13:33 -0800)]
clk: rockchip: Add CLK_SET_RATE_PARENT to sclk_uart clocks
We'd like to be able to set the clock rate of the sclk_uart clocks and
actually be able to achieve clock rates greater than 24MHz. To do
this we need to be able to pass rate changes upward.
Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Linus Torvalds [Sun, 21 Dec 2014 00:48:59 +0000 (16:48 -0800)]
Merge tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/borntraeger/linux
Pull ACCESS_ONCE cleanup preparation from Christian Borntraeger:
"kernel: Provide READ_ONCE and ASSIGN_ONCE
As discussed on LKML http://marc.info/?i=54611D86.4040306%40de.ibm.com
ACCESS_ONCE might fail with specific compilers for non-scalar
accesses.
Here is a set of patches to tackle that problem.
The first patch introduce READ_ONCE and ASSIGN_ONCE. If the data
structure is larger than the machine word size memcpy is used and a
warning is emitted. The next patches fix up several in-tree users of
ACCESS_ONCE on non-scalar types.
This does not yet contain a patch that forces ACCESS_ONCE to work only
on scalar types. This is targetted for the next merge window as Linux
next already contains new offenders regarding ACCESS_ONCE vs.
non-scalar types"
* tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/borntraeger/linux:
s390/kvm: REPLACE barrier fixup with READ_ONCE
arm/spinlock: Replace ACCESS_ONCE with READ_ONCE
arm64/spinlock: Replace ACCESS_ONCE READ_ONCE
mips/gup: Replace ACCESS_ONCE with READ_ONCE
x86/gup: Replace ACCESS_ONCE with READ_ONCE
x86/spinlock: Replace ACCESS_ONCE with READ_ONCE
mm: replace ACCESS_ONCE with READ_ONCE or barriers
kernel: Provide READ_ONCE and ASSIGN_ONCE
Linus Torvalds [Sun, 21 Dec 2014 00:42:36 +0000 (16:42 -0800)]
Merge tag 'clk-for-linus-3.19' of git://git.linaro.org/people/mike.turquette/linux
Pull clk framework updates from Mike Turquette:
"This is much later than usual due to several last minute bugs that had
to be addressed. As usual the majority of changes are new drivers and
modifications to existing drivers. The core recieved many fixes along
with the groundwork for several large changes coming in the future
which will better parition clock providers from clock consumers"
* tag 'clk-for-linus-3.19' of git://git.linaro.org/people/mike.turquette/linux: (86 commits)
clk: samsung: Fix Exynos 5420 pinctrl setup and clock disable failure due to domain being gated
ARM: OMAP3: clock: fix boot breakage in legacy mode
ARM: OMAP2+: clock: fix DPLL code to use new determine rate APIs
clk: Really fix deadlock with mmap_sem
clk: mmp: fix sparse non static symbol warning
clk: Change clk_ops->determine_rate to return a clk_hw as the best parent
clk: change clk_debugfs_add_file to take a struct clk_hw
clk: Don't expose __clk_get_accuracy
clk: Don't try to use a struct clk* after it could have been freed
clk: Remove unused function __clk_get_prepare_count
clk: samsung: Fix double add of syscore ops after driver rebind
clk: samsung: exynos4: set parent of sclk_hdmiphy to hdmi
clk: samsung: exynos4415: Fix build with PM_SLEEP disabled
clk: samsung: remove unnecessary inclusion of header files from clk.h
clk: samsung: remove unnecessary CONFIG_OF from clk.c
clk: samsung: Spelling s/bwtween/between/
clk: rockchip: Add support for the mmc clock phases using the framework
clk: rockchip: add bindings for the mmc clocks
clk: rockchip: rk3288 export i2s0_clkout for use in DT
clk: rockchip: use clock ID for DMC (memory controller) on rk3288
...
Linus Torvalds [Sat, 20 Dec 2014 21:52:52 +0000 (13:52 -0800)]
Merge branch 'i2c/for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux
Pull more i2c updates from Wolfram Sang:
"Included are two bugfixes needing some bigger refactoring (sh_mobile:
deferred probe with DMA, mv64xxx: fix offload support) and one
deprecated driver removal I thought would go in via ppc but I
misunderstood. It has a proper ack from BenH"
* 'i2c/for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux:
i2c: sh_mobile: fix uninitialized var when debug is enabled
macintosh: therm_pm72: delete deprecated driver
i2c: sh_mobile: I2C_SH_MOBILE should depend on HAS_DMA
i2c: sh_mobile: rework deferred probing
i2c: sh_mobile: refactor DMA setup
i2c: mv64xxx: rework offload support to fix several problems
i2c: mv64xxx: use BIT() macro for register value definitions
Linus Torvalds [Sat, 20 Dec 2014 21:42:57 +0000 (13:42 -0800)]
Merge tag 'scsi-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi
Pull SCSI update from James Bottomley:
"This is a much shorter set of patches that were on the go but didn't
make it in to the early pull request for the merge window. It's
really a set of bug fixes plus some final cleanup work on the new tag
queue API"
* tag 'scsi-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi:
storvsc: ring buffer failures may result in I/O freeze
ipr: set scsi_level correctly for disk arrays
ipr: add support for async scanning to speed up boot
scsi_debug: fix missing "break;" in SDEBUG_UA_CAPACITY_CHANGED case
scsi_debug: take sdebug_host_list_lock when changing capacity
scsi_debug: improve driver description in Kconfig
scsi_debug: fix compare and write errors
qla2xxx: fix race in handling rport deletion during recovery causes panic
scsi: blacklist RSOC for Microsoft iSCSI target devices
scsi: fix random memory corruption with scsi-mq + T10 PI
Revert "[SCSI] mpt3sas: Remove phys on topology change"
Revert "[SCSI] mpt2sas: Remove phys on topology change."
esas2r: Correct typos of "validate" in a comment
fc: FCP_PTA_SIMPLE is 0
ibmvfc: remove unused tag variable
scsi: remove MSG_*_TAG defines
scsi: remove scsi_set_tag_type
scsi: remove scsi_get_tag_type
scsi: never drop to untagged mode during queue ramp down
scsi: remove ->change_queue_type method
Linus Torvalds [Sat, 20 Dec 2014 21:37:44 +0000 (13:37 -0800)]
Merge tag 'pm-config-3.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm
Pull CONFIG_PM_RUNTIME elimination from Rafael Wysocki:
"This removes the last few uses of CONFIG_PM_RUNTIME introduced
recently and makes that config option finally go away.
CONFIG_PM will be available directly from the menu now and also it
will be selected automatically if CONFIG_SUSPEND or CONFIG_HIBERNATION
is set"
* tag 'pm-config-3.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm:
PM: Eliminate CONFIG_PM_RUNTIME
tty: 8250_omap: Replace CONFIG_PM_RUNTIME with CONFIG_PM
sound: sst-haswell-pcm: Replace CONFIG_PM_RUNTIME with CONFIG_PM
spi: Replace CONFIG_PM_RUNTIME with CONFIG_PM
Linus Torvalds [Sat, 20 Dec 2014 21:33:03 +0000 (13:33 -0800)]
Merge branch 'misc' of git://git.kernel.org/pub/scm/linux/kernel/git/mmarek/kbuild
Pull misc kbuild changes from Michal Marek:
"There are only a few things in the misc branch:
- Fix for bugon.cocci semantic patch
- Kdevelop4 files are .gitignored
- Put make binrpm-pkg on diet"
* 'misc' of git://git.kernel.org/pub/scm/linux/kernel/git/mmarek/kbuild:
scripts/package: binrpm-pkg do not create source and devel package
.gitignore: Add Kdevelop4 project files
bugon.cocci: fix Options at the macro
Linus Torvalds [Sat, 20 Dec 2014 21:31:14 +0000 (13:31 -0800)]
Merge branch 'kbuild' of git://git.kernel.org/pub/scm/linux/kernel/git/mmarek/kbuild
Pull kbuild updates from Michal Marek:
"Here are the kbuild changes for v3.19-rc1:
- Cleanups and deduplication in the main Makefile and
scripts/Makefile.*
- Sort the output of *config targets in make help
- Old <linux/version.h> is always removed to avoid a surprise during
bisecting
- Warning fix in kconfig"
* 'kbuild' of git://git.kernel.org/pub/scm/linux/kernel/git/mmarek/kbuild:
kbuild: remove redundant -rR flag of hdr-inst
kbuild: Fix make help-<board series> on powerpc
kbuild: Automatically remove stale <linux/version.h> file
kconfig: Fix warning "‘jump’ may be used uninitialized"
Makefile: sort list of defconfig targets in make help output
kbuild: Remove duplicate $(cmd) definition in Makefile.clean
kbuild: collect shorthands into scripts/Kbuild.include
Linus Torvalds [Sat, 20 Dec 2014 02:19:19 +0000 (18:19 -0800)]
Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs
Pull vfs pile #3 from Al Viro:
"Assorted fixes and patches from the last cycle"
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs:
[regression] chunk lost from bd9b51
vfs: make mounts and mountstats honor root dir like mountinfo does
vfs: cleanup show_mountinfo
init: fix read-write root mount
unfuck binfmt_misc.c (broken by commit e6084d4)
vm_area_operations: kill ->migrate()
new helper: iter_is_iovec()
move_extent_per_page(): get rid of unused w_flags
lustre: get rid of playing with ->fs
btrfs: filp_open() returns ERR_PTR() on failure, not NULL...
Linus Torvalds [Sat, 20 Dec 2014 02:15:12 +0000 (18:15 -0800)]
Merge tag 'ecryptfs-3.19-rc1-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tyhicks/ecryptfs
Pull eCryptfs fixes from Tyler Hicks:
"Fixes for filename decryption and encrypted view plus a cleanup
- The filename decryption routines were, at times, writing a zero
byte one character past the end of the filename buffer
- The encrypted view feature attempted, and failed, to roll its own
form of enforcing a read-only mount instead of letting the VFS
enforce it"
* tag 'ecryptfs-3.19-rc1-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tyhicks/ecryptfs:
eCryptfs: Remove buggy and unnecessary write in file name decode routine
eCryptfs: Remove unnecessary casts when parsing packet lengths
eCryptfs: Force RO mount when encrypted view is enabled
Linus Torvalds [Sat, 20 Dec 2014 02:10:42 +0000 (18:10 -0800)]
Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mason/linux-btrfs
Pull more btrfs updates from Chris Mason:
"This is part two of our merge window patches.
These are all from Filipe, and fix some really hard to find races that
can cause corruptions. Most of them involved block group removal
(balance) or discard"
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mason/linux-btrfs:
Btrfs: remove non-sense btrfs_error_discard_extent() function
Btrfs: fix fs corruption on transaction abort if device supports discard
Btrfs: always clear a block group node when removing it from the tree
Btrfs: ensure deletion from pinned_chunks list is protected
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