For 32-bit address spaces randomize within a
16MB space, for 64-bit within a 256MB space.
Test Results:
------------
Without Patch (VDSO is not randomized)
---------------------------------------
root@Maleo:~# ./aslr vdso
FAIL: ASLR not functional (vdso always at 0x7fff7000)
Fix the issue with the ISA bit being lost in fixups that jump to labels
placed just before a section switch. Such a switch leads to the ISA bit
being lost, because GAS concludes there is no code that follows and
therefore the label refers to data. Use the `.insn' pseudo-op to
convince the tool this is not the case.
This lack of label annotation leads to microMIPS compilation errors
like:
mips-linux-gnu-ld: arch/mips/built-in.o: .fixup+0x3b8: Unsupported jump between ISA modes; consider recompiling with interlinking enabled.
mips-linux-gnu-ld: final link failed: Bad value
Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8483/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
In the microMIPS encoding some memory access instructions have their
immediate offset reduced to 12 bits only. That does not match the GCC
`R' constraint we use in some places to satisfy the requirement,
resulting in build failures like this:
{standard input}: Assembler messages:
{standard input}:720: Error: macro used $at after ".set noat"
{standard input}:720: Warning: macro instruction expanded into multiple instructions
Fix the problem by defining a macro, `GCC_OFF12_ASM', that expands to
the right constraint depending on whether microMIPS or standard MIPS
code is produced. Also apply the fix to where `m' is used as in the
worst case this change does nothing, e.g. where the pointer was already
in a register such as a function argument and no further offset was
requested, and in the best case it avoids an extraneous sequence of up
to two instructions to load the high 20 bits of the address in the LL/SC
loop. This reduces the risk of lock contention that is the higher the
more instructions there are in the critical section between LL and SC.
Strictly speaking we could just bulk-replace `R' with `ZC' as the latter
constraint adjusts automatically depending on the ISA selected.
However it was only introduced with GCC 4.9 and we keep supporing older
compilers for the standard MIPS configuration, hence the slightly more
complicated approach I chose.
The choice of a zero-argument function-like rather than an object-like
macro was made so that it does not look like a function call taking the
C expression used for the constraint as an argument. This is so as not
to confuse the reader or formatting checkers like `checkpatch.pl' and
follows previous practice.
Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8482/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Only allow 32-bit microMIPS builds, we're not ready yet for 64-bit
microMIPS support.
QEMU does have support for the 64-bit microMIPS ISA and with minor
tweaks it is possible to have a 64-bit processor emulated there that
runs microMIPS code, so despite the lack of actual 64-bit microMIPS
hardware there is a way to run 64-bit microMIPS Linux, but it can all be
considered early development and we are not there yet. Userland tools
are lacking too, e.g. GCC produces bad code:
{standard input}: Assembler messages:
{standard input}:380: Warning: wrong size instruction in a 16-bit branch delay slot
And our build fails early on, so disable the configuration, for the sake
of automatic random config checkers if nothing else. Whoever needs to
experiment with 64-bit microMIPS support can revert this change easily.
Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8481/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
MIPS: signal.c: Fix an invalid cast in ISA mode bit handling
Fix:
arch/mips/kernel/signal.c: In function 'handle_signal':
arch/mips/kernel/signal.c:533:21: error: cast from pointer to integer of different size [-Werror=pointer-to-int-cast]
unsigned int tmp = (unsigned int)current->mm->context.vdso;
^
arch/mips/kernel/signal.c:536:9: error: cast to pointer from integer of different size [-Werror=int-to-pointer-cast]
vdso = (void *)tmp;
^
cc1: all warnings being treated as errors
when building a 64-bit kernel.
This is not really a supported configuration, but the cast is wrong
either way, Linux makes the assumption that sizeof(void *) equals
sizeof(unsigned long) and therefore the latter type is expected to be
used where integer operations have to be applied to pointers for some
reason.
Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8480/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
MIPS: mm: Only build one microassembler that is suitable
The microMIPS microassembler is only suitable for configurations where
the kernel itself is built to microMIPS machine code and not where only
user microMIPS software is supported. The former is controlled with the
CPU_MICROMIPS configuration setting, whereas SYS_SUPPORTS_MICROMIPS is
used for the latter.
Not only that, but with a given microMIPS vs standard MIPS kernel
configuration only one microassembler is needed, that matches the ISA
selected -- CP0.Config3.ISAOnExc is mandatory on microMIPS processors,
so there is never a need to mix microMIPS and standard MIPS code.
Consequently build only the microassembler that matches the ISA selected
for the kernel.
Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8479/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Add missing microMIPS support to Malta. Currently the kernel only
enables support for the instruction set for the SEAD-3 board despite the
fact processor features have nothing to do with the board a processor is
installed in.
In this case there is no way to run microMIPS software in a fully
supported way under Linux on QEMU. QEMU supports the emulation of a
Malta board, but does not emulate SEAD-3. Linux supports running
microMIPS code on a SEAD-3 board, but hardcodes such support to off on
an emulated Malta board even if the processor selected has the microMIPS
instruction set implemented.
Adding support for the SEAD-3 to QEMU is a major project. Flipping a
bit in the kernel that shouldn't have been cleared in the first place is
a trivial effort. Thus the answer is plain...
Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8478/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Aaro Koskinen [Wed, 19 Nov 2014 21:52:51 +0000 (23:52 +0200)]
MIPS: loongson: common: rtc: make loongson_rtc_resources static
Make loongson_rtc_resources static to eliminate the following
sparse warning:
warning: symbol 'loongson_rtc_resources' was not declared. Should it be static?
Aaro Koskinen [Wed, 19 Nov 2014 21:52:50 +0000 (23:52 +0200)]
MIPS: loongson: common: init: Add a missing include
Add a missing include to eliminate the following sparse warnings:
warning: symbol 'prom_init' was not declared. Should it be static?
warning: symbol 'prom_free_prom_memory' was not declared. Should it be static?
Aaro Koskinen [Wed, 19 Nov 2014 21:52:48 +0000 (23:52 +0200)]
MIPS: loongson: lemote-2f: irq: Make internal data static
Make internal static to eliminate the following sparse warnings:
warning: symbol 'ip6_irqaction' was not declared. Should it be static?
warning: symbol 'cascade_irqaction' was not declared. Should it be static?
Aaro Koskinen [Wed, 19 Nov 2014 21:52:46 +0000 (23:52 +0200)]
MIPS: Loongson: cs5536_pci: Add a missing include
Add a missing include to get rid of the following sparse warnings:
warning: symbol 'cs5536_pci_conf_write4' was not declared. Should it be static?
warning: symbol 'cs5536_pci_conf_read4' was not declared. Should it be static?
Joshua Kinard [Wed, 8 Oct 2014 01:33:04 +0000 (21:33 -0400)]
MIPS: IP22/IP32: Add line to arch/mips/Makefile archhelp about vmlinux.32
Building a 64bit kernel for the SGI O2 (IP32) and the SGI Indy (IP22) uses
the 'vmlinux.32' target, which converts the output 64-bit 'vmlinux' image
into a 32-bit wrapped image. This is needed for certain revisions of the
IP22 and IP32 ARCS PROMs to boot correctly, but this target is missing
from the 'archhelp' info that is emitted by 'make help'.
Signed-off-by: Joshua Kinard <kumba@gentoo.org> Cc: Linux MIPS List <linux-mips@linux-mips.org>
Patchwork: https://patchwork.linux-mips.org/patch/7991/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Having #ifdefs just to guard comments is not really helpful
so drop them. Moreover, the code wasn't really reached anyway
since there is a #ifndef CONFIG_CPU_MIPSR2 on the top of the file.
We should not need to read fuses during normal operation, also the current
code has issues with that (not safe for concurrent access). Since there
are no in-kernel users for these, just delete them. Drivers should
not need such OCTEON_HAS_FEATURE mechanism in any case, instead the
information should be passed via device tree.
Signed-off-by: Aaro Koskinen <aaro.koskinen@nsn.com> Cc: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/7665/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Aaro Koskinen [Fri, 17 Oct 2014 15:10:26 +0000 (18:10 +0300)]
MIPS: oprofile: Backtrace: don't fail on leaf functions
Continue the backtrace if we cannot find SP adjustment and RA save. In
that case, just assume the current RA. This allows us to get samples of
frequent callers of e.g. GLIBC memset().
Aaro Koskinen [Fri, 17 Oct 2014 15:10:25 +0000 (18:10 +0300)]
MIPS: oprofile: Enable backtrace on timer-based profiling
Allow unsupported CPU types to use backtrace with timer-based profiling.
Some CPUs (notably OCTEON) lack architecture-specific oprofile driver. In
such case oprofile can fallback to timer-based mode, and arch code can
still provide the backtrace functionality. So just set up the backtrace
hook always.
Add device-tree support for the MIPS GIC. Update the GIC irqdomain's
xlate() callback to handle the three-cell specifier described in the
MIPS GIC binding document.
Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Jason Cooper <jason@lakedaemon.net> Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: John Crispin <blogic@openwrt.org> Cc: David Daney <ddaney.cavm@gmail.com> Cc: Qais Yousef <qais.yousef@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8422/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
The Global Interrupt Controller (GIC) present on certain MIPS systems
can be used to route external interrupts to individual VPEs and CPU
interrupt vectors. It also supports a timer and software-generated
interrupts.
Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Acked-by: Arnd Bergmann <arnd@arndb.de> Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: John Crispin <blogic@openwrt.org> Cc: David Daney <ddaney.cavm@gmail.com> Cc: Qais Yousef <qais.yousef@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8420/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Alban Bedel [Fri, 7 Nov 2014 11:44:35 +0000 (12:44 +0100)]
MIPS: ath79: Use the firmware lib to parse the kernel command line
No need to duplicate code that is available in the firmware library.
It also give us access to the firmware environment which is needed
to read the initrd address and size.
Sergey Ryazanov [Tue, 28 Oct 2014 23:18:49 +0000 (03:18 +0400)]
ath5k: update dependencies
- Use config symbol defined in the driver instead of arch specific one for
conditional compilation.
- Rename the ATHEROS_AR231X config symbol to ATH25.
- Fix include (ar231x_platform.h -> ath25_platform.h).
- Some of AR231x SoCs (e.g. AR2315) have PCI bus support, so remove !PCI
dependency, which block AHB support build.
Signed-off-by: Sergey Ryazanov <ryazanov.s.a@gmail.com> Acked-by: John W. Linville <linville@tuxdriver.com> Cc: Jiri Slaby <jirislaby@gmail.com> Cc: Nick Kossifidis <mickflemm@gmail.com> Cc: "Luis R. Rodriguez" <mcgrof@do-not-panic.com> Cc: linux-wireless@vger.kernel.org Cc: ath5k-devel@lists.ath5k.org Cc: Linux MIPS <linux-mips@linux-mips.org>
Patchwork: https://patchwork.linux-mips.org/patch/8248/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
AHB bus code has been removed, since we did not have support Atheros
AR231x SoC, required for building the AHB version of ath5k. Now that
support WiSoC chips added we can restore functionality back.
Signed-off-by: Sergey Ryazanov <ryazanov.s.a@gmail.com> Acked-by: John W. Linville <linville@tuxdriver.com> Cc: Jiri Slaby <jirislaby@gmail.com> Cc: Nick Kossifidis <mickflemm@gmail.com> Cc: "Luis R. Rodriguez" <mcgrof@do-not-panic.com> Cc: linux-wireless@vger.kernel.org Cc: ath5k-devel@lists.ath5k.org Cc: Linux MIPS <linux-mips@linux-mips.org>
Patchwork: https://patchwork.linux-mips.org/patch/8247/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Sergey Ryazanov [Tue, 28 Oct 2014 23:18:46 +0000 (03:18 +0400)]
MIPS: ath25: register AR5312 flash controller
AR5312 SoC flash controller maps the flash content to memory and
translates the memory access operations to the flash access operations.
Such controller is fully supported by the physmap-flash driver.
Sergey Ryazanov [Tue, 28 Oct 2014 23:18:44 +0000 (03:18 +0400)]
MIPS: ath25: add board configuration detection
All boards based on AR5312/AR2315 SoC have a special structure located
at the end of flash. This structure contains board-specific data such as
Ethernet and Wireless MAC addresses. The flash is mapped to the memmory
at predefined location.
Rewrite TURBOchannel error handling to use a common failure path, making
sure put_device is called for devices that failed initialization. While
at it update printk calls to use pr_err rather than KERN_ERR.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6701/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
John Crispin [Thu, 9 Oct 2014 02:02:53 +0000 (04:02 +0200)]
MIPS: ralink: cleanup the soc specific pinmux data
Before we had a pinctrl driver we used a custom OF api. This patch converts the
soc specific pinmux data to a new set of structs. We also add some new pinmux
setings.
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/8009/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
John Crispin [Wed, 8 Oct 2014 21:28:51 +0000 (23:28 +0200)]
MIPS: ralink: copy the commandline from the devicetree
This is a regression caused by:
commit afb46f7996e91aeb36e07bc92cf96e8045bec00e
Author: Rob Herring <robh@kernel.org>
Date: Wed Apr 2 19:07:24 2014 -0500
mips: ralink: convert to use unflatten_and_copy_device_tree
Make the of init code reuse the cmdline defined inside the dts.
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/8008/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
John Crispin [Wed, 8 Oct 2014 20:40:02 +0000 (22:40 +0200)]
MIPS: ralink: allow manual memory override
RT5350 relies on the bootloader setting up the memc correctly. On some boards
the setup is incorrect leading to 32 MB being available but only 16 MB being
recognized. Allow these boards to manually override the memory range.
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/8004/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
John Crispin [Fri, 10 Oct 2014 21:14:29 +0000 (23:14 +0200)]
MIPS: lantiq: copy the commandline from the devicetree
This is a regression caused by:
commit afb46f7996e91aeb36e07bc92cf96e8045bec00e
Author: Rob Herring <robh@kernel.org>
Date: Wed Apr 2 19:07:24 2014 -0500
mips: ralink: convert to use unflatten_and_copy_device_tree
Make the of init code reuse the cmdline defined inside the dts.
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/8048/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
John Crispin [Wed, 10 Sep 2014 20:39:19 +0000 (22:39 +0200)]
MIPS: lantiq: add support for xrx200 firmware depending on soc type
VR9 needs different firmware files for the various phy/soc revisions. Some
boards are ship with older and newer SoC revisions. To be able to boot a single
image on all versions we need to define both firmware files inside the
devicetree.
John Crispin [Wed, 13 Mar 2013 09:04:01 +0000 (10:04 +0100)]
MIPS: lantiq: handle vmmc memory reservation
The Lantiq SoCs have a 2nd mips core called "voice mips macro core (vmmc)"
which is used to run the voice firmware. This driver allows us to register
a chunk of memory that the voice driver can later use for the 2nd core.
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/8042/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
clocksource: mips-gic: Use CPU notifiers to setup the timer
Instead of requiring an explicit call to gic_clockevent_init in the SMP
startup path, use CPU notifiers to register and enable the GIC timer on
CPU startup.
Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Qais Yousef <qais.yousef@imgtec.com> Cc: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8139/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
clocksource: mips-gic: Move gic_frequency to clocksource driver
There's no reason for gic_frequency to be global any more and it
certainly doesn't belong in the GIC irqchip driver, so move it to
the GIC clocksource driver.
Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Qais Yousef <qais.yousef@imgtec.com> Cc: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8137/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
clocksource: mips-gic: Combine with GIC clockevent driver
Combine the GIC clocksource driver with the GIC clockevent driver from
arch/mips/kernel/cevt-gic.c and remove the clockevent driver's separate
Kconfig symbol.
Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Andrew Bresticker <abrestic@chromium.org> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Qais Yousef <qais.yousef@imgtec.com> Cc: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8132/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
There's no reason for the pending and masked interrupt bitmasks
to be global. Just declare them on the stack in gic_get_int()
since they only consume (256*2)/8 = 64 bytes.
Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Qais Yousef <qais.yousef@imgtec.com> Cc: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8131/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Kevin Cernekee [Tue, 21 Oct 2014 04:28:05 +0000 (21:28 -0700)]
MIPS: bcm3384: Initial commit of bcm3384 platform support
This supports SMP Linux running on the BCM3384 Zephyr (BMIPS5000)
application processor, with fully functional UART and USB 1.1/2.0.
Device Tree is used to configure the following items:
- All peripherals
- Early console base address
- SMP or UP mode
- MIPS counter frequency
- Memory size / regions
- DMA offset
- Kernel command line
The DT-enabled bootloader and build instructions are posted at
https://github.com/Broadcom/aeolus
Kevin Cernekee [Tue, 21 Oct 2014 04:28:01 +0000 (21:28 -0700)]
MIPS: BMIPS: Add PRId for BMIPS5200 (Whirlwind)
This is a dual core (quad thread) BMIPS5000. It needs a little extra
code to boot the second core (CPU2/CPU3), but for now we can treat it the
same as a single core BMIPS5000.
Kevin Cernekee [Tue, 21 Oct 2014 04:28:00 +0000 (21:28 -0700)]
MIPS: BMIPS: Add special cache handling in c-r4k.c
BMIPS435x and BMIPS438x have a single shared L1 D$ and load/store unit,
so it isn't necessary to raise IPIs to keep both CPUs coherent.
BMIPS5000 has VIPT L1 caches that handle aliases in hardware, and its I$
fills from D$. But a special sequence with 2 SYNCs and 32 NOPs is needed
to ensure coherency.
Kevin Cernekee [Tue, 21 Oct 2014 04:27:59 +0000 (21:27 -0700)]
MIPS: BMIPS: Let each platform customize the CPU1 IRQ mask
On some chips like bcm3384, "other stuff" gets wired up to CPU1's IE_IRQ1
input, generating spurious IRQs. In this case we want the platform code
to be able to mask it off.
Kevin Cernekee [Tue, 21 Oct 2014 04:27:58 +0000 (21:27 -0700)]
MIPS: BMIPS: Select the appropriate L1_CACHE_SHIFT for 438x and 5000 CPUs
BMIPS438x has a 64-byte D$ line size and BMIPS5000 has a 128-byte L2
line size. If L1_CACHE_SHIFT is undersized, DMA buffers will not be
cacheline-aligned and terrible things will happen.
projects / linux-beck.git / log