Antonio Borneo [Wed, 1 Jul 2015 06:15:02 +0000 (14:15 +0800)]
stm32f4: fix MAINTAINERS file
When "scripts/get_maintainer.pl" parses "board/.../MAINTAINERS",
it uses the line containing board name as delimiter.
Without this line, the script happily mixes the lines from current
board MAINTAINERS file with lines from another file.
Fix it by adding a reasonable board name.
Tested by comparing output of:
cat board/st/stm32f429-discovery/MAINTAINERS
./scripts/get_maintainer.pl -f board/st/stm32f429-discovery
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
To: u-boot@lists.denx.de
To: Kamil Lulko <rev13@wp.pl> Cc: Tom Rini <trini@konsulko.com>
Egli, Samuel [Wed, 1 Jul 2015 15:57:39 +0000 (17:57 +0200)]
siemens,am33x: adjust mtd partition
Use one mtd partition for rootfs and configuration by
means of ubi volumes and get rid of configuration partition.
We can use partition layout for both 256MB and 512MB flash.
Signed-off-by: Samuel Egli <samuel.egli@siemens.com> Cc: Heiko Schocher <hs@denx.de> Cc: Roger Meier <r.meier@siemens.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Heiko Schocher <hs@denx.de>
Roger Quadros [Thu, 25 Jun 2015 07:25:50 +0000 (10:25 +0300)]
ARM: beagle_x15: prevent DCAN1 _wait_target_disable failure in kernel
If board is booted with transitions happening on DCAN1 pins then
the following warning is seen in the kernel at boot when the
hwmod layer initializes.
"omap_hwmod: dcan1: _wait_target_disable failed"
This is because DCAN1 module's SWAKEUP mechanism is broken
and it fails to correctly turn OFF if it sees a transition on the
DCAN1 pins. Suggested workaround is to keep DCAN1 pins in safe mode
while enabling/disabling DCAN1 module.
The hwmod layer enables and disables all modules at boot
and we have no opportunity to put the DCAN1 pins in safe mode
at that point.
DCAN1 is not used by u-boot so it doesn't matter to it if these
pins are in safe mode. The kernel driver correctly configures
the right mode when DCAN1 is active.
Signed-off-by: Roger Quadros <rogerq@ti.com>
[trini: s/PULLUP/PULL_UP/ based on DRA7xx EVM version of this patch] Signed-off-by: Tom Rini <trini@konsulko.com>
Roger Quadros [Wed, 24 Jun 2015 14:00:11 +0000 (17:00 +0300)]
ARM: DRA7-evm: prevent DCAN1 _wait_target_disable failure in kernel
If board is booted with transitions happening on DCAN1 pins then
the following warning is seen in the kernel at boot when the
hwmod layer initializes.
"omap_hwmod: dcan1: _wait_target_disable failed"
This is because DCAN1 module's SWAKEUP mechanism is broken
and it fails to correctly turn OFF if it sees a transition on the
DCAN1 pins. Suggested workaround is to keep DCAN1 pins in safe mode
while enabling/disabling DCAN1 module.
The hwmod layer enables and disables all modules at boot
and we have no opportunity to put the DCAN1 pins in safe mode
at that point.
DCAN1 is not used by u-boot so it doesn't matter to it if these
pins are in safe mode. The kernel driver correctly configures
the right mode when DCAN1 is active.
Makefile:Add GCC flag -fno-delete-null-pointer-checks
-fdelete-null-pointer-checks flag controls global dataflow analyses and
eliminate useless checks for null pointers; It assume that if a pointer is
checked after it has already been dereferenced, it cannot be null.
This flag is enabled by default.
gcc v4.9 has more optimizations added to this option. Hence it is very
aggressive with GCC v4.9 series. Add -fno-delete-null-pointer-checks to
disable the optimization
Joe Hershberger [Mon, 22 Jun 2015 22:57:36 +0000 (17:57 -0500)]
Allow CONFIG_REGEX to be disabled when CONFIG_NET
Instead of selecting REGEX when NET is enabled, make it the default, but
allow boards that are tiny to disable it and lose functionality on all
but the first Ethernet adapter.
cm-bf548, bf538f-ezkit, and bf533-stamp need this. None appear to have
more than one Ethernet interface.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Bin Meng [Mon, 15 Jun 2015 10:40:19 +0000 (18:40 +0800)]
net: designware: Program MAC address to hardware after soft reset
commit f566c99 "net: Update hardware MAC address if it changes in env"
removes writing MAC address to designware controller after soft reset.
This makes designware ethernet port fail to work. Actually the MAC
address should always be programmed after soft reset.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Mugunthan V N [Mon, 22 Jun 2015 09:13:10 +0000 (14:43 +0530)]
ARM: DRA72x: fix io delay calibration for ethernet
we currently use in-development IODelay values for DRA72x which are
proposed in the data sheet, however, DRA72x EVM uses DP83865 ethernet
Phy over RGMII. The PHY characteristics and routing choices made on
the EVM, make the current iodelay values fail ethernet communication.
Instead, we need to choose custom values for DRA72x-evm specifically
designed for the PHY and routing on the platform for ethernet to
function.
Simon Glass [Tue, 2 Jun 2015 17:08:21 +0000 (11:08 -0600)]
Revert "break build if it would produce broken binary"
The root cause of this problem should now be fixed.
This reverts commit a6a4c542d316b3401f0840ac5378743191bca851. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Pavel Machek <pavel@denx.de> Tested-by: Pavel Machek <pavel@denx.de>
Simon Glass [Tue, 2 Jun 2015 17:08:20 +0000 (11:08 -0600)]
arm: Add ENTRY/ENDPROC to private libgcc functions
When CONFIG_SYS_THUMB_BUILD is defined these functions may be called from
Thumb code. Add the required ENTRY and ENDPROC bracketing so that BLX is
used to call these ARM functions, instead of plain BL, which will fail.
Signed-off-by: Simon Glass <sjg@chromium.org> Reported-by: Pavel Machek <pavel@denx.de>
Axel Lin [Tue, 14 Apr 2015 06:55:24 +0000 (14:55 +0800)]
gpio: lpc32xx: Use priv_data instead of platdata
The LPC32XX GPIO driver platdata currently contains GPIO state information,
which should go into priv_data. Thus rename lpc32xx_gpio_platdata to
lpc32xx_gpio_priv and convert to use dev_get_priv() instead.
Signed-off-by: Axel Lin <axel.lin@ingics.com> Tested-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
Guillaume GARDET [Tue, 16 Jun 2015 09:48:48 +0000 (11:48 +0200)]
mx53loco: Use generic 'load' command instead of 'fatload'
This patch uses generic 'load' command instead of 'fatload' for 'loadbootscript', 'loadimage' and 'loadfdt' for mx53loco board.
This allows to use EXT partition instead of FAT, while keeping FAT compatibility.
Signed-off-by: Guillaume GARDET <guillaume.gardet@free.fr> Cc: Jason Liu <r64343@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Jason Liu <r64343@freescale.com>
Chen-Yu Tsai [Tue, 23 Jun 2015 11:57:27 +0000 (19:57 +0800)]
sunxi: Add Sinlinx SinA33 defconfig
Sinlinx SinA33 is a core/daughter board SDK kit from Sinlinx. It has
the A33 SoC, USB host, USB OTG, audio input/output, LCD, camera, SDIO
and GPIO headers.
Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Chen-Yu Tsai [Tue, 23 Jun 2015 11:57:26 +0000 (19:57 +0800)]
sunxi: Sync sun8i dts files with the linux kernel
Copy over all the latest dts changes from mripard/sunxi/dt-for-4.2.
This adds a dts file for Sinlinx SinA33 dev board, and the required
changes in the .dtsi files.
Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Chen-Yu Tsai [Tue, 23 Jun 2015 11:57:24 +0000 (19:57 +0800)]
sunxi: rsb: Enable R_PIO clock before configuring external pins
The original code was configuring the external pins after enabling
the R_PIO clock, which meant the configuration never made it to
the pin controller the first time in SPL.
Why this was working before is uncertain. Maybe the state was left
from a previous boot sequence, or RSB just happened to be the default
configuration. However with some A33 chips, SPL failed to configure
the PMIC. This was seen by me and Maxime on the Sinlinx SinA33 dev
board.
Reordering the calls fixed this.
Signed-off-by: Chen-Yu Tsai <wens@csie.org> Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Tested-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Chen-Yu Tsai [Tue, 23 Jun 2015 11:57:23 +0000 (19:57 +0800)]
sunxi: hardware-feature-specific function index defines for PORT F UART0
Commit 487b327 ("sunxi: GPIO pin mux hardware-feature-specific function
index defines") renamed all GPIO index defines, but missed the PORT F
UART0 setup functions.
Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
sram size could be different on different socs, e.g. on stv0991 it is 256 while
on altera platform it is 128. It is better to receive it from device tree.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Tested-by: Stefan Roese <sr@denx.de> Reviewed-by: Jagannadh Teki <jteki@openedev.com>
spi: cadence_qspi: move the sram partition in init
There is no need to re-configure sram partition for every read/write for
better full use of sram for read or write. This patch divides the half
sram for read & half for write once at initialization.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Tested-by: Stefan Roese <sr@denx.de> Reviewed-by: Jagannadh Teki <jteki@openedev.com>
Sanchayan Maity [Mon, 8 Jun 2015 07:10:41 +0000 (12:40 +0530)]
colibri_vf: Increase console IO buffer size to 1024
Increase console IO buffer size to 1024 from the previous value of 256.
The previous value was too short for editing environment variables like
ubiboot from the console.
Jagan Teki [Sat, 27 Jun 2015 10:37:54 +0000 (16:07 +0530)]
spi: Kconfig: Add TEGRA20_SLINK entry
Added TEGRA20_SLINK entry on Kconfig with help description.
Signed-off-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Tom Warren <twarren@nvidia.com> Cc: Stephen Warren <swarren@nvidia.com>
Jagan Teki [Sat, 27 Jun 2015 10:34:05 +0000 (16:04 +0530)]
spi: Kconfig: Add TEGRA20_SFLASH entry
Added TEGRA20_SFLASH entry on Kconfig with help description.
Signed-off-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Tom Warren <twarren@nvidia.com> Cc: Stephen Warren <swarren@nvidia.com>
Jagan Teki [Sat, 27 Jun 2015 10:27:53 +0000 (15:57 +0530)]
spi: Kconfig: Add TEGRA114_SPI entry
Added TEGRA114_SPI entry on Kconfig with help description.
Signed-off-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Tom Warren <twarren@nvidia.com> Cc: Stephen Warren <swarren@nvidia.com>
Masahiro Yamada [Tue, 30 Jun 2015 09:27:00 +0000 (18:27 +0900)]
ARM: dts: UniPhier: sync device trees with the Linux kernel
This makes code diff much easier.
Device trees describe hardware attributes, which are independent
of software architecture. It generally makes sense to synchronize
them beyond software projects.
Jagan Teki [Fri, 26 Jun 2015 19:21:37 +0000 (00:51 +0530)]
spi: xilinx_spi: Add asm/io.h include file
This patch includes asm/io.h for readl and writel calls.
build errors:
drivers/spi/xilinx_spi.c: In function 'xilinx_spi_probe':
drivers/spi/xilinx_spi.c:119:2: warning: implicit declaration of function 'writel' [-Wimplicit-function-declaration]
drivers/spi/xilinx_spi.c: In function 'xilinx_spi_xfer':
drivers/spi/xilinx_spi.c:193:2: warning: implicit declaration of function 'readl' [-Wimplicit-function-declaration]
Signed-off-by: Jagan Teki <jteki@openedev.com> Cc: Michal Simek <michal.simek@xilinx.com>
Jagan Teki [Fri, 26 Jun 2015 19:21:34 +0000 (00:51 +0530)]
spi: zynq_spi: Add fdt support in driver
Now zynq spi driver platform data is controlled by devicetree,
enable the status by saying "okay" on respective board dts to use
the devicetree generated platdata.
Ex:
&spi1 {
status = "okay";
};
Signed-off-by: Jagan Teki <jteki@openedev.com> Acked-by: Simon Glass <sjg@chromium.org> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Tested-by: Jagan Teki <jteki@openedev.com>
Jagan Teki [Fri, 26 Jun 2015 19:21:31 +0000 (00:51 +0530)]
dm: spi: zynq_spi: Convert to driver model
This converts the zynq spi driver to use the driver model.
Minimal functional changes like using meaningful name on
structure members wrt mainlined dm spi drivers.
- input_hz -> frequency
- req_hz -> freq
- base -> regs
Signed-off-by: Jagan Teki <jteki@openedev.com> Acked-by: Simon Glass <sjg@chromium.org> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Tested-by: Jagan Teki <jteki@openedev.com>
Alexey Brodkin [Mon, 18 May 2015 13:56:26 +0000 (16:56 +0300)]
arc: significant cache rework
[1] Align cache management functions to those in Linux kernel. I.e.:
a) Use the same functions for all cache ops (D$ Inv/Flush)
b) Split cache ops in 3 sub-functions: "before", "lineloop" and
"after". That way we may re-use "before" and "after" functions for
region and full cache ops.
[2] Implement full-functional L2 (SLC) management. Before SLC was
simply disabled early on boot. It's also possible to enable or disable
L2 cache from config utility.
[3] Disable/enable corresponding caches early on boot. So if U-Boot is
configured to use caches they will be used at all times (this is useful
in partucular for speed-up of relocation).
arc: implement slave cores kick-start for Linux kernel
With new SMP-enabled CPUs with ARC HS38 cores and corresponding support
in Linux kernel it's required to add basic SMP support in U-Boot.
Currently we assume the one and only core starts execution after
power-on. So most of things in U-Boot is handled in UP mode.
But when U-Boot is used for loading and starting Linux kernel right
before jumping to kernel's entry point U-Boot:
[1] Sets all slave cores to jump to the same address [kernel's entry
point]
[2] Really starts all slav cores
In ARC's implemetation of SMP in Linux kernel all cores are supposed to
run the same start-up code. But only core with ID 0 (master core)
processes further while others are looping waiting for master core to
complete some initialization.
That means it's safe to un-pause slave cores and let them execute kernel
- they will wait for master anyway.
spi, sf: Use offset and size in sf cmd from mtdpartition
With this patch, it is possible to get the offset and size information
from the mtdpartiton setting in "mtdparts", similiar to the
"nand" commandos.
=> sf
sf - SPI flash sub-system
Usage:
sf probe [[bus:]cs] [hz] [mode] - init flash device on given SPI bus
and chip select
sf read addr offset|partition len - read `len' bytes starting at
`offset' to memory at `addr'
sf write addr offset|partition len - write `len' bytes from memory
at `addr' to flash at `offset'
sf erase offset|partition [+]len - erase `len' bytes from `offset'
`+len' round up `len' to block size
sf update addr offset|partition len - erase and write `len' bytes from memory
at `addr' to flash at `offset'
=>
for example "env" is defined in mtdparts:
=> sf read 13000000 env
device 0 offset 0xd0000, size 0x10000
SF: 65536 bytes @ 0xd0000 Read: OK
zynq-uboot> mtdparts add nor0 0x10000@0x0 env
zynq-uboot> sf erase env 0x10000
SF: 65536 bytes @ 0x0 Erased: OK
zynq-uboot> sf write 0x100 env
device 0 offset 0x0, size 0x10000
SF: 65536 bytes @ 0x0 Written: OK
zynq-uboot> sf read 0x40000 env
device 0 offset 0x0, size 0x10000
SF: 65536 bytes @ 0x0 Read: OK
Signed-off-by: Heiko Schocher <hs@denx.de> Tested-by: Jagannadh Teki <jteki@openedev.com> Reviewed-by: Jagannadh Teki <jteki@openedev.com>
projects / karo-tx-uboot.git / log