David Daney [Thu, 10 Nov 2011 23:25:20 +0000 (15:25 -0800)]
MIPS: Update Octeon model detection code for new chips.
Several newer chips were not covered, update the code to detect them.
This necessitates updating cvmx-mio-defs.h as well, because it has new
and required definitions.
Grant Grundler [Tue, 15 Nov 2011 07:12:42 +0000 (07:12 +0000)]
net-next:asix: V2 more fixes for ax88178 phy init sequence
Now works on Samsung Series 5 (chromebook)
Two fixes here:
o use 0x7F mask for phymode
o read phyid *AFTER* phy is powered up (via GPIOs)
Signed-off-by: Allan Chou <allan@asix.com.tw> Signed-off-by: Grant Grundler <grundler@chromium.org> Signed-off-by: David S. Miller <davem@davemloft.net>
Grant Grundler [Tue, 15 Nov 2011 07:12:41 +0000 (07:12 +0000)]
net-next:asix: reduce AX88772 init time by about 2 seconds
ax88772_reset takes about 2 seconds and is called twice.
Once from ax88772_bind() directly and again indirectly from usbnet_open().
Reset the USB FW/Phy enough to blink the LEDs when inserted.
Signed-off-by: Allan Chou <allan@asix.com.tw> Signed-off-by: Grant Grundler <grundler@chromium.org> Signed-off-by: David S. Miller <davem@davemloft.net>
Grant Grundler [Tue, 15 Nov 2011 07:12:40 +0000 (07:12 +0000)]
net-next:asix:poll in asix_get_phyid in case phy not ready
Sometimes the phy isn't ready after reset...poll and pray it will be soon.
Signed-off-by: Freddy Xin <freddy@asix.com.tw> Signed-off-by: Grant Grundler <grundler@chromium.org> Signed-off-by: David S. Miller <davem@davemloft.net>
Kevin Cernekee [Fri, 11 Nov 2011 06:30:24 +0000 (22:30 -0800)]
MIPS: BMIPS: Fix up Kconfig settings
Factor out common BMIPS options into "CPU_BMIPS". Add L2 cache for
BMIPS5000. Add CPU_MIPS32 to satisfy checks in page.h, r4k_switch.S,
tlb-r4k.c, etc.
Manuel Lauss [Thu, 10 Nov 2011 19:09:38 +0000 (20:09 +0100)]
MIPS: Alchemy: merge Au1000 and Au1300-style IRQ controller code.
With a generic plat_irq_dispatch (for Alchemy at least) code for both
interrupt controller types can coexist in a single kernel image and be
autodetected at runtime.
Manuel Lauss [Thu, 10 Nov 2011 12:06:23 +0000 (12:06 +0000)]
net/irda: convert au1k_ir to platform driver.
Moderate driver cleanup:
convert to platform driver, get rid of board-specific code.
Driver loads and runs on a DB1100 board. But since I have no other
IrDA hardware to exchange data with I can't say whether it really sends
and receives.
Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com> Cc: Samuel Ortiz <samuel@sortiz.org> Cc: netdev@vger.kernel.org
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2877/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Manuel Lauss [Thu, 10 Nov 2011 12:06:23 +0000 (12:06 +0000)]
MTD: nand: make au1550nd.c a platform_driver
Transform the au1550nd.c driver into a platform_driver and hook it
up in the PB1550 board (gen_nand works fine on the DB1550, but since
I don't have a PB1550 to test this driver stays for now).
Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com> Cc: linux-mtd@lists.infradead.org
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2875/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Manuel Lauss [Thu, 10 Nov 2011 12:06:22 +0000 (12:06 +0000)]
MIPS: Alchemy: Add RTC device to all devboards
All Devboards can use the 32kHz counter as a RTC device.
Also delete the custom CMOS RTC header, which can be used for the
DS1693 on the PB1500. But since it doesn't have a buffer battery
it is as useful as the on-chip RTC which I prefer.
Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2874/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Manuel Lauss [Tue, 1 Nov 2011 19:03:30 +0000 (20:03 +0100)]
MIPS: Alchemy: Au1300 SoC support
Add basic support for the Au1300 variant(s):
- New GPIO/Interrupt controller
- DBDMA ids
- USB setup
- MMC support
- enable various PSC drivers
- detection code.
Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2866/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Initially I had to write to both the MASK and ENABLE registers, otherwise
the CPLD would generate tons of spurious interrupts. With the change to
the demux handler to disable the muxed line, it is now sufficient to
disable the interrupt by writing either the enable or mask register.
Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2865/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Manuel Lauss [Tue, 1 Nov 2011 19:03:28 +0000 (20:03 +0100)]
MIPS: Alchemy: Drop MIRAGE/BOSPORUS board support
No test hardware and no (apparent) users. These boards seem very
similar to the DB1500, so if required support can be brought back
again (I have datasheets) but then with dedicated board code, not
tacked on to DB1000 support.
Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2864/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
John Crispin [Thu, 10 Nov 2011 20:33:07 +0000 (21:33 +0100)]
MIPS: lantiq: use export.h in favour of module.h
The code located at arch/mips/lantiq/ included module.h to be able to use
the EXPORT_SYMBOL* macros. These can now be directly included using
export.h.
Maksim Rayskiy [Thu, 10 Nov 2011 17:59:45 +0000 (17:59 +0000)]
MIPS: ASID conflict after CPU hotplug
I am running SMP Linux 2.6.37-rc1 on BMIPS5000 (single core dual thread)
and observe some abnormalities when doing system suspend/resume which I
narrowed down to cpu hotplugging. The suspend brings the second thread
processor down and then restarts it, after which I see memory corruption
in userspace. I started digging and found out that problem occurs because
while doing execve() the child process is getting the same ASID as the
parent, which obviously corrupts parent's address space.
Further digging showed that activate_mm() calls get_new_mmu_context() to
get a new ASID, but at this time ASID field in entryHi is 1, and
asid_cache(cpu) is 0x100 (it was just reset to ASID_FIRST_VERSION when
the secondary TP was booting).
So, get_new_mmu_context() increments the asid_cache(cpu) value to
0x101, and thus puts 0x01 into entryHi. The result - ASID field does
not get changed as it was supposed to.
My solution is very simple - do not reset asid_cache(cpu) on TP warm
restart.
Aaro Koskinen [Thu, 10 Nov 2011 17:59:45 +0000 (17:59 +0000)]
MIPS: errloongson2_clock: Fix build error by including linux/module.h
Fix the following compilation failure with v3.2-rc1 by including module.h:
CC [M] arch/mips/kernel/cpufreq/loongson2_clock.o
arch/mips/kernel/cpufreq/loongson2_clock.c:39:1: error: data definition has no type or storage class [-Werror]
arch/mips/kernel/cpufreq/loongson2_clock.c:39:1: error: type defaults to 'int' in declaration of 'EXPORT_SYMBOL_GPL' [-Werror=implicit-int]
arch/mips/kernel/cpufreq/loongson2_clock.c:39:1: error: parameter names (without types) in function declaration [-Werror]
arch/mips/kernel/cpufreq/loongson2_clock.c:51:1: error: data definition has no type or storage class [-Werror]
arch/mips/kernel/cpufreq/loongson2_clock.c:51:1: error: type defaults to 'int' in declaration of 'EXPORT_SYMBOL' [-Werror=implicit-int]
arch/mips/kernel/cpufreq/loongson2_clock.c:51:1: error: parameter names (without types) in function declaration [-Werror]
arch/mips/kernel/cpufreq/loongson2_clock.c:71:1: error: data definition has no type or storage class [-Werror]
arch/mips/kernel/cpufreq/loongson2_clock.c:71:1: error: type defaults to 'int' in declaration of 'EXPORT_SYMBOL' [-Werror=implicit-int]
arch/mips/kernel/cpufreq/loongson2_clock.c:71:1: error: parameter names (without types) in function declaration [-Werror]
arch/mips/kernel/cpufreq/loongson2_clock.c:76:1: error: data definition has no type or storage class [-Werror]
arch/mips/kernel/cpufreq/loongson2_clock.c:76:1: error: type defaults to 'int' in declaration of 'EXPORT_SYMBOL' [-Werror=implicit-int]
arch/mips/kernel/cpufreq/loongson2_clock.c:76:1: error: parameter names (without types) in function declaration [-Werror]
arch/mips/kernel/cpufreq/loongson2_clock.c:82:1: error: data definition has no type or storage class [-Werror]
arch/mips/kernel/cpufreq/loongson2_clock.c:82:1: error: type defaults to 'int' in declaration of 'EXPORT_SYMBOL' [-Werror=implicit-int]
arch/mips/kernel/cpufreq/loongson2_clock.c:82:1: error: parameter names (without types) in function declaration [-Werror]
arch/mips/kernel/cpufreq/loongson2_clock.c:87:1: error: data definition has no type or storage class [-Werror]
arch/mips/kernel/cpufreq/loongson2_clock.c:87:1: error: type defaults to 'int' in declaration of 'EXPORT_SYMBOL' [-Werror=implicit-int]
arch/mips/kernel/cpufreq/loongson2_clock.c:87:1: error: parameter names (without types) in function declaration [-Werror]
arch/mips/kernel/cpufreq/loongson2_clock.c:93:1: error: data definition has no type or storage class [-Werror]
arch/mips/kernel/cpufreq/loongson2_clock.c:93:1: error: type defaults to 'int' in declaration of 'EXPORT_SYMBOL_GPL' [-Werror=implicit-int]
arch/mips/kernel/cpufreq/loongson2_clock.c:93:1: error: parameter names (without types) in function declaration [-Werror]
arch/mips/kernel/cpufreq/loongson2_clock.c:131:1: error: data definition has no type or storage class [-Werror]
arch/mips/kernel/cpufreq/loongson2_clock.c:131:1: error: type defaults to 'int' in declaration of 'EXPORT_SYMBOL_GPL' [-Werror=implicit-int]
arch/mips/kernel/cpufreq/loongson2_clock.c:131:1: error: parameter names (without types) in function declaration [-Werror]
arch/mips/kernel/cpufreq/loongson2_clock.c:147:1: error: data definition has no type or storage class [-Werror]
arch/mips/kernel/cpufreq/loongson2_clock.c:147:1: error: type defaults to 'int' in declaration of 'EXPORT_SYMBOL_GPL' [-Werror=implicit-int]
arch/mips/kernel/cpufreq/loongson2_clock.c:147:1: error: parameter names (without types) in function declaration [-Werror]
arch/mips/kernel/cpufreq/loongson2_clock.c:166:1: error: data definition has no type or storage class [-Werror]
arch/mips/kernel/cpufreq/loongson2_clock.c:166:1: error: type defaults to 'int' in declaration of 'EXPORT_SYMBOL_GPL' [-Werror=implicit-int]
arch/mips/kernel/cpufreq/loongson2_clock.c:166:1: error: parameter names (without types) in function declaration [-Werror]
arch/mips/kernel/cpufreq/loongson2_clock.c:168:15: error: expected declaration specifiers or '...' before string constant
arch/mips/kernel/cpufreq/loongson2_clock.c:169:20: error: expected declaration specifiers or '...' before string constant
arch/mips/kernel/cpufreq/loongson2_clock.c:170:16: error: expected declaration specifiers or '...' before string constant
Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi>
To: linux-mips@linux-mips.org
To: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/2922/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
David Daney [Mon, 7 Nov 2011 20:49:30 +0000 (12:49 -0800)]
STAGING: octeon-ethernet: Fix compile error caused by skb_frag_struct change
Evidently the definition of struct skb_frag_struct has changed, so we
need to change to match it.
Signed-off-by: David Daney <david.daney@cavium.com>
To: netdev@vger.kernel.org
To: gregkh@suse.de
To: devel@driverdev.osuosl.org
Patchwork: https://patchwork.linux-mips.org/patch/2909/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Al Cooper [Tue, 8 Nov 2011 14:59:01 +0000 (09:59 -0500)]
MIPS: Kernel hangs occasionally during boot.
The Kernel hangs occasionally during boot after "Calibrating delay loop..".
This is caused by the c0_compare_int_usable() routine in cevt-r4k.c
returning false which causes the system to disable the timer and hang later.
The false return happens because the routine is using a series of four calls
to irq_disable_hazard() as a delay while it waits for the timer changes to
propagate to the cp0 cause register. On newer MIPS cores, like the 74K, the
series of irq_disable_hazard() calls turn into ehb instructions and can take
as little as a few clock ticks for all 4 instructions. This is not enough of
a delay, so the routine thinks the timer is not working. This fix uses up
to a max number of cycle counter ticks for the delay and uses
back_to_back_c0_hazard() instead of irq_disable_hazard() to handle the
hazard condition between cp0 writes and cp0 reads.
Signed-off-by: Al Cooper <alcooperx@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/2911/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Venkat Subbiah [Mon, 3 Oct 2011 20:31:10 +0000 (13:31 -0700)]
MIPS: Octeon: Mark SMP-IPI interrupt as IRQF_NO_THREAD
This is to exclude it from force threading to allow RT patch set to work.
And while on this line
* Remove IRQF_DISABLED as as this flag is NOOP
* Add IRQF_PERCPU as this is a per cpu interrupt.
Signed-off-by: Venkat Subbiah <venkat.subbiah@cavium.com> Acked-by: David Daney <david.daney@cavium.com>
To: linux-mips@linux-mips.org
To: linux-rt-users@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/2817/ Acked-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
MIPS: BCM47xx: fix build with GENERIC_GPIO configuration
Since eb9ae7f2 (gpio: fix build error in include/asm-generic/gpio.h)
the generic version of gpio.h calls __gpio_{set,get}_value which we
do not define. Get rid of asm-generic/gpio.h and define the missing
stubs directly for BCM47xx to build.
David S. Miller [Tue, 15 Nov 2011 20:57:00 +0000 (12:57 -0800)]
sparc: Stash orig_i0 into %g6 instead of %g2
As per the comments added by this commit, %g2 turns out to not be a
usable place to save away orig_i0 for syscall restart handling.
In fact all of %g2, %g3, %g4, and %g5 are assumed to be saved across
a system call by various bits of code in glibc.
%g1 can't be used because that holds the syscall number, which would
need to be saved and restored for syscall restart handling too, and
that would only compound our problems :-)
This leaves us with %g6 and %g7 which are for "system use". %g7 is
used as the "thread register" by glibc, but %g6 is used as a compiler
and assembler temporary scratch register. And in no instance is %g6
used to hold a value across a system call.
Therefore %g6 is safe for storing away orig_i0, at least for now.
Signed-off-by: David S. Miller <davem@davemloft.net>
RS485: fix inconsistencies in the meaning of some variables
The crisv10.c and the atmel_serial.c serial drivers intepret the fields of the
serial_rs485 structure in a different way.
In particular, crisv10.c uses SER_RS485_RTS_AFTER_SEND and
SER_RS485_RTS_ON_SEND for the voltage of the RTS pin; atmel_serial.c,
instead, uses these values to know if a delay must be set before and
after sending. This patch makes the usage of these variables consistent
across all drivers and fixes the Documentation as well.
From now on, SER_RS485_RTS_AFTER_SEND and SER_RS485_RTS_ON_SEND will be
used to set the voltage of the RTS pin (as in the crisv10.c driver); the
delay will be understood by looking only at the value of
delay_rts_before_send and delay_rts_after_send.
Signed-off-by: Claudio Scordino <claudio@evidence.eu.com> Signed-off-by: Darron Black <darron@griffin.net> Acked-by: Jesper Nilsson <jesper.nilsson@axis.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Acked-by: Alan Cox <alan@lxorguk.ukuu.org.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
CAUSE:
Changing mode using setserial command, ".startup" function which gets DMA
channel is called before ".verify_port" function which sets
dma-flag(use_dma/use_dma_flag) as 1.
PIO->DMA
.startup: Since dma-flag is 0, DMA channel is not requested.
.verify_port: dma-flag is set as 1.
.shutdown: N/A
DMA->PIO
.startup: Since dma-flag is 1, DMA channel is requested.
.verify_port: dma-flag is set as 0.
.shutdown: Since dma-flag is 0, DMA channel is not released.
This means DMA channel resource leak occurs.
Next time, this driver can't get DMA channel resource forever.
MODIFICATION:
Currently, when release DMA channel resource, this driver checks dma-flag.
However, this specification occurs the above issue.
This driver must check whether dma_request_channel is executed or not.
The values are saved in private data variable "chan_tx/chan_tx".
These variables mean if the value is NULL, DMA channel is not requested,
if not NULL, DMA channel is requested.
Alan Cox [Thu, 10 Nov 2011 13:17:55 +0000 (13:17 +0000)]
serial,mfd: Fix CMSPAR setup
This is referenced the wrong way. Mika Westerberg added some checks to the
tty to support multiple console, but the real problem is simply referencing the
termios object via the wrong path.
Signed-off-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Doug Anderson [Wed, 12 Oct 2011 00:05:43 +0000 (17:05 -0700)]
tty/serial: Prevent drop of DCD on suspend for Tegra UARTs
On Tegra UARTs (except UART1), the DTR / DCD / DSR lines are not
externally accessible. Instead, the DTR line internally appears to be
looped back to be the input to the DCD and DSR lines. The net effect
of this is that when we drop DTR (like when we suspend), we'll see DCD
drop too. ...and when we see DCD drop, we treat that as a hangup.
In order to prevent this hangup from occurring at every sleep, we need
to force DTR to remain high on Tegra UARTs.
This patch uses the mcr_mask / mcr_force fields, which were originally
added for the kludge ALPHA_KLUDGE_MCR. Using these fields does not
prevent us from removing ALPHA_KLUDGE_MCR--we can just remove the "if"
tests I have added and always init mcr_mask / mcr_force from the
serial8250_config.
NOTE: If we have people that are using UARTA on a Tegra and need to
control DTR, we'll need to either add a separate port type for UARTA
or we'll need to add some tegra-specific code to detect whether the
DTR needs to be left high.
Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Stephen Boyd [Wed, 26 Oct 2011 02:19:43 +0000 (19:19 -0700)]
tty: hvc_dcc: Fix duplicate character inputs
Reading from the DCC grabs a character from the buffer and
clears the status bit. Since this is a context-changing
operation, instructions following the character read that rely on
the status bit being accurate need to be synchronized with an
ISB.
In this case, the status bit check needs to execute after the
character read otherwise we run the risk of reading the character
and checking the status bit before the read can clear the status
bit in the first place. When this happens, the user will see the
same character they typed twice, instead of once.
Add an ISB after the read and the write, so that the status check
is synchronized with the read/write operations.
projects / karo-tx-linux.git / log