Masahiro Yamada [Mon, 22 Aug 2016 13:18:22 +0000 (22:18 +0900)]
tools: moveconfig: add --spl option to move options for SPL build
Prior to this commit, the tool could not move options guarded by
CONFIG_SPL_BUILD ifdef conditionals because they do not show up in
include/autoconf.mk. This new option, if given, makes the tool
parse spl/include/autoconf.mk instead of include/autoconf.mk,
which is probably preferred behavior when moving options for SPL.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Masahiro Yamada [Mon, 22 Aug 2016 13:18:21 +0000 (22:18 +0900)]
tools: moveconfig: warn loudly if moved option has no entry in Kconfig
Currently, the tool gives up moving an option quietly if its entry
was not found in Kconfig.
If the option is not defined in the config header in the first
place, it is no problem (as the Kconfig entry may have been hidden
by reasonable "depends on").
However, if the option is defined in the config header, the missing
Kconfig entry is a sign of possible behavior change. It is highly
recommended to manually check if the option has been moved as
expected. In this case, let's add "suspicious" in the log and
change the log color (if --color option is given) to make it stand
out.
pinctrl: generic: scan for "pins" and "groups" properties in sub-nodes
In cases where the pins and groups definitions are in a sub-node, as:
uart_a {
mux {
groups = "uart_tx_a", "uart_rx_a";
function = "uart_a";
};
};
pinctrl_generic_set_state_subnode() returns an error for the top-level
node and pinctrl_generic_set_state() fails. Instead, return success so
that the child nodes are tried.
Alexander Graf [Mon, 15 Aug 2016 15:48:51 +0000 (17:48 +0200)]
serial: bcm283x_mu: Detect disabled serial device
On the raspberry pi, you can disable the serial port to gain dynamic frequency
scaling which can get handy at times.
However, in such a configuration the serial controller gets its rx queue filled
up with zero bytes which then happily get transmitted on to whoever calls
getc() today.
This patch adds detection logic for that case by checking whether the RX pin is
mapped to GPIO15 and disables the mini uart if it is not mapped properly.
That way we can leave the driver enabled in the tree and can determine during
runtime whether serial is usable or not, having a single binary that allows for
uart and non-uart operation.
Signed-off-by: Alexander Graf <agraf@suse.de> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Reviewed-by: Simon Glass <sjg@chromium.org>
Mugunthan V N [Wed, 31 Aug 2016 11:52:19 +0000 (17:22 +0530)]
ARM: dts: dra72-evm: fix broken ethernet
With commit ceec08f50b6, phy is connected to slave 0, but
changing the phy node was missed, fix it by populating the
phy node to proper cpsw slave node.
Fixes: ceec08f50b6 ("ARM: dts: dra72-evm: Add mode-gpios entry for mac node") Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Cc: Vignesh R <vigneshr@ti.com> Tested-by: Tom Rini <trini@konsulko.com>
Andre Przywara [Mon, 5 Sep 2016 00:32:41 +0000 (01:32 +0100)]
sunxi: fix 64-bit compiler warning for SPL header parsing
Casting "int"s to pointers is only valid for 32-bit systems.
Add the appropriate pointer type cast to avoid a compiler warning
when compiling for AArch64.
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Andre Przywara [Mon, 5 Sep 2016 00:32:40 +0000 (01:32 +0100)]
sunxi: Kconfig: rename non-existent SUN50I_A64 config symbol
There is no "CONFIG_MACH_SUN50I_A64" in upstream U-Boot, so fix
the name to prevent the option to be enabled.
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Andre Przywara [Mon, 5 Sep 2016 00:32:38 +0000 (01:32 +0100)]
Revert "sunxi: Move the SPL stack top to 0x1A000 on Allwinner A64/A80"
This commit moved the SPL stack into SRAM C, which worked when the SPL
set the AHB1 clock down to 100 MHz to cope with the flaky SRAM C access
from the CPU.
However booting with boot0 (and thus not using SPL at all) we still run
with a 200 MHz AHB1, so any access to SRAM C is prone to fail.
Since this commit does _not_ only affect the SPL code, but also the
U-Boot proper, we fail when booting with boot0.
As the introduction of tiny-printf reduced the size of the SPL, we
can afford to have the SPL stack in SRAM A1.
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Hans de Goede [Sat, 3 Sep 2016 09:42:31 +0000 (11:42 +0200)]
sunxi: Add defconfig and dts file for the Orange Pi Plus2E SBC
The Orange Pi Plus2E is an extended version of the Orange Pi Pc Plus,
with 2G RAM and an external gbit ethernet phy.
The dts file is identical to the one submitted to the upstream kernel,
except that it has the pending patch to enable the ethernet controller
squashed in, as u-boot already has sun8i-emac support.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Hans de Goede [Sat, 3 Sep 2016 08:21:35 +0000 (10:21 +0200)]
sunxi: Sync h3-orangepi dts files with kernel
This adds an emac node to the orangepi-2 dts (not yet merged upstream,
but in u-boot we already have emac support); fixes the alphetically
sorting of nodes in sun8i-h3-orangepi-plus.dts and disables some
usb controllers in sun8i-h3-orangepi-plus.dts which are only used
on the plus2e, as upstream has decided to do a separate dts files
for the plus2e.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
The sun8i-emac driver follows an old version of the proposed DT
bindings, where the EMAC clock and EPHY control register range is
listed directly, rather than through a syscon phandle.
Add back the syscon register range to avoid an invalid data access.
We should fix the driver once the Linux kernel bindings have been
finalized.
Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
A33-OLinuXino is A33 development board designed by Olimex LTD.
It has AXP223 PMU, 1GB DRAM, a micro SD card, one USB-OTG connector,
headphone and mic jacks, connector for LiPo battery and optional
4GB NAND Flash.
It has two 40-pin headers. One for LCD panel, and one for
additional modules. Also there is CSI/DSI connector.
The dts files are identical to the ones submitted to the upstream kernel.
Signed-off-by: Stefan Mavrodiev <stefan.mavrodiev@gmail.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Icenowy Zheng [Sat, 27 Aug 2016 14:16:13 +0000 (22:16 +0800)]
sunxi: Add iNet D978 rev2 defconfig
The iNet D978 rev2 is a tablet board designed by iNet, which is intended to
use on 10" tablets with a appearance like Apple iPad. It has A33 SoC, 1GB
RAM, 8GB/16GB NAND, SDIO Wi-Fi, a MicroUSB port and a MicroSD slot.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Chris Packham [Mon, 29 Aug 2016 03:20:52 +0000 (15:20 +1200)]
mtd: nand: pxa3xx: use nand_set_controller_data
In commit 17cb4b8f327e ("mtd: nand: Add+use mtd_to/from_nand and
nand_get/set_controller_data") the assignment of mtd->priv was removed
but was not replaced. This adds the required nand_set_controller_data()
call.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Peter Chubb [Tue, 30 Aug 2016 22:54:46 +0000 (22:54 +0000)]
ARM: tegra: Add support for TK1-SOM board from Colorado Engineering
The Colorado TK1 SOM is a small form factor board similar to the
Jetson TK1. The main differences lie in the pinmux, and in that the
PCIe controller is set to use in 4lanes+1lane, rather than 2+2.
The pinmux header here was generated from a spreadsheet provided by
Colorado Engineering using the tegra-pinmux scripts. The spreadsheet
was converted from v09 to v11 by me.
Signed-off-by: Peter Chubb <peter.chubb@data61.csiro.au> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
Stephen Warren [Tue, 30 Aug 2016 16:22:07 +0000 (10:22 -0600)]
ARM: tegra: use numeric versioning for p2771-0000
The board ID EEPROM and board ID stickers on p2771-0000 will use a numeric
versioning scheme, with version numbers such as 000/100/200/300/400/500.
Within NVIDIA, these versions are also known as A00/A01/A02/A03/A04/B00.
However, that numbering scheme is not easily visible outside of NVIDIA,
and so does not make much sense to use. Convert U-Boot to use the readily
visible numeric scheme.
Also, it turns out that the current A02 DT actually applies to board
versions 000/100/200 (A00..A02). Consequently rename this to 000 not 200
so that all U-Boot builds are named after the first version of the HW they
support.
Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
Bin Meng [Thu, 25 Aug 2016 08:47:18 +0000 (01:47 -0700)]
x86: efi: Fix EFI 64-bit payload build warnings
There are lots of warnings when building EFI 64-bit payload.
include/asm-generic/bitops/__fls.h:17:2:
warning: left shift count >= width of type
if (!(word & (~0ul << 32))) {
^
In fact, U-Boot itself as EFI payload is running in 32-bit mode.
So BITS_PER_LONG needs to still be 32, but EFI status codes are
64-bit when booting from 64-bit EFI. Introduce EFI_BITS_PER_LONG
to bridge those status codes with U-Boot's BITS_PER_LONG.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 26 Jul 2016 00:58:58 +0000 (18:58 -0600)]
x86: ivybridge: Allow microcode to be collated
Generally the microcode is combined into a single block only (and removed
from the device tree) when there are multiple blocks. But this is not a
requirement.
Adjust the ivybridge code to avoid assuming this.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Masahiro Yamada [Thu, 25 Aug 2016 08:02:31 +0000 (17:02 +0900)]
ARM: uniphier: display revision of Micro Support Card 3.6.x kindly
The revision of the original support card (rev 3.5, rev 3.6) fits in
the 8 bit width revision register. When it was extended in a weird
way, it was versioned in the format of "3.6.x" (where it should have
been "3.7", of course). What is worse, only the sub-level version
"6.x" was recorded in the 8 bit width register, completely ignoring
the compatibility of the revision register format.
This patch saves madly-versioned support cards by assuming the major
version "3" when the MSB 4 bit of the register is read as "6". With
this, the support card revision that were displayed as "6.10" is now
corrected to "3.6.10".
Masahiro Yamada [Thu, 25 Aug 2016 12:03:41 +0000 (21:03 +0900)]
ARM: uniphier: support system reset functionality for PSCI
This supports the system reset via PSCI for ARMv7 SoCs.
Because the system reset is not supported on PSCI 0.1, let's define
CONFIG_ARMV7_PSCI_1_0. (it is supported since PSCI 0.2, but there
is no CONFIG to enable it in U-Boot for now.)
Masahiro Yamada [Thu, 25 Aug 2016 05:52:37 +0000 (14:52 +0900)]
mmc: uniphier-sd: return error code if unsupported width is given
With the CONFIG_DM_MMC_OPS migration, the .set_ios callback can
return an integer now. Return an appropriate error value rather
than sudden death by BUG().
Tony Lindgren [Wed, 24 Aug 2016 16:46:32 +0000 (09:46 -0700)]
nand: Fix set_dev checks for no device
If we do nand device 0 command in u-boot on a device that has NAND support
enabled but no NAND chip, we can get data abort at least on omaps.
Fix the issue by replacing the check with nand_info[dev] as
suggested by Scott Wood. The check for name existed before because before
the array-to-pointer conversion there was no way to directly test
nand_info[dev] for emptiness.
Stefan Agner [Mon, 15 Aug 2016 04:33:01 +0000 (21:33 -0700)]
arm: cache: always flush cache line size for page table
The page table is maintained by the CPU, hence it is safe to always
align cache flush to a whole cache line size. This allows to use
mmu_page_table_flush for a single page table, e.g. when configure
only small regions through mmu_set_region_dcache_behaviour.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Tested-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de>
Tom Rini [Mon, 22 Aug 2016 12:22:17 +0000 (08:22 -0400)]
ARM: Move SYS_CACHELINE_SIZE over to Kconfig
This series moves the CONFIG_SYS_CACHELINE_SIZE. First, in nearly all
cases we are mirroring the values used by the Linux Kernel here. Also,
so long as (and in this case, it is true) we implement flushes in hunks
that are no larger than the smallest implementation (and given that we
mirror the Linux Kernel, again we are fine) it is OK to align higher.
The biggest changes here are that we always use 64 bytes for CPU_V7 even
if for example the underlying core is only 32 bytes (this mirrors
Linux). Second, we say ARM64 uses 64 bytes not 128 (as found in the
Linux Kernel) as we do not need multi-platform support (to this degree)
and only the Cavium ThunderX 88xx series has a use for such large
alignment.
Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Prafulla Wadaskar <prafulla@marvell.com> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Stefan Roese <sr@denx.de> Cc: Nagendra T S <nagendra@mistralsolutions.com> Cc: Vaibhav Hiremath <hvaibhav@ti.com> Acked-by: Lokesh Vutla <lokeshvutla@ti.com> Cc: Steve Rae <steve.rae@raedomain.com> Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Nikita Kiryanov <nikita@compulab.co.il> Cc: Stefan Agner <stefan.agner@toradex.com> Acked-by: Heiko Schocher <hs@denx.de> Cc: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Cc: Peter Griffin <peter.griffin@linaro.org> Acked-by: Paul Kocialkowski <contact@paulk.fr> Cc: Anatolij Gustschin <agust@denx.de> Acked-by: "Pali Rohár" <pali.rohar@gmail.com> Cc: Adam Ford <aford173@gmail.com> Cc: Steve Sakoman <sakoman@gmail.com> Cc: Grazvydas Ignotas <notasas@gmail.com> Cc: Nishanth Menon <nm@ti.com> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Robert Baldyga <r.baldyga@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Thomas Weber <weber@corscience.de> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: David Feng <fenghua@phytium.com.cn> Cc: Alison Wang <b18965@freescale.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Simon Glass <sjg@chromium.org> Cc: York Sun <york.sun@nxp.com> Cc: Shengzhou Liu <Shengzhou.Liu@nxp.com> Cc: Mingkai Hu <mingkai.hu@nxp.com> Cc: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Cc: Aneesh Bansal <aneesh.bansal@freescale.com> Cc: Saksham Jain <saksham.jain@nxp.com> Cc: Qianyu Gong <qianyu.gong@nxp.com> Cc: Wang Dongsheng <dongsheng.wang@nxp.com> Cc: Alex Porosanu <alexandru.porosanu@freescale.com> Cc: Hongbo Zhang <hongbo.zhang@nxp.com> Cc: tang yuantian <Yuantian.Tang@freescale.com> Cc: Rajesh Bhagat <rajesh.bhagat@nxp.com> Cc: Josh Wu <josh.wu@atmel.com> Cc: Bo Shen <voice.shen@atmel.com> Cc: Viresh Kumar <viresh.kumar@linaro.org> Cc: Hannes Schmelzer <oe5hpm@oevsv.at> Cc: Thomas Chou <thomas@wytron.com.tw> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Sam Protsenko <semen.protsenko@linaro.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Christophe Ricard <christophe-h.ricard@st.com> Cc: Anand Moon <linux.amoon@gmail.com> Cc: Beniamino Galvani <b.galvani@gmail.com> Cc: Carlo Caione <carlo@endlessm.com> Cc: huang lin <hl@rock-chips.com> Cc: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Cc: Xu Ziyuan <xzy.xu@rock-chips.com> Cc: "jk.kernel@gmail.com" <jk.kernel@gmail.com> Cc: "Ariel D'Alessandro" <ariel@vanguardiasur.com.ar> Cc: Kever Yang <kever.yang@rock-chips.com> Cc: Samuel Egli <samuel.egli@siemens.com> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Hans de Goede <hdegoede@redhat.com> Cc: Ian Campbell <ijc@hellion.org.uk> Cc: Siarhei Siamashka <siarhei.siamashka@gmail.com> Cc: Boris Brezillon <boris.brezillon@free-electrons.com> Cc: Andre Przywara <andre.przywara@arm.com> Cc: Bernhard Nortmann <bernhard.nortmann@web.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Ben Whitten <ben.whitten@gmail.com> Cc: Tom Warren <twarren@nvidia.com> Cc: Alexander Graf <agraf@suse.de> Cc: Sekhar Nori <nsekhar@ti.com> Cc: Vitaly Andrianov <vitalya@ti.com> Cc: "Andrew F. Davis" <afd@ti.com> Cc: Murali Karicheri <m-karicheri2@ti.com> Cc: Carlos Hernandez <ceh@ti.com> Cc: Ladislav Michl <ladis@linux-mips.org> Cc: Ash Charles <ashcharles@gmail.com> Cc: Mugunthan V N <mugunthanvnm@ti.com> Cc: Daniel Allred <d-allred@ti.com> Cc: Gong Qianyu <Qianyu.Gong@freescale.com> Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Chin Liang See <clsee@altera.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Paul Kocialkowski <contact@paulk.fr>
Jens Kuske [Fri, 19 Aug 2016 11:40:46 +0000 (13:40 +0200)]
sunxi: Tune H3 DRAM PLL to improve lock time
The H3 PLL5 used for DRAM barely manages to lock to the required
frequency before DRAM controller starts, sometimes leading to wrong
delay-line calibration results.
This patch changes the PLL tuning parameters to the same values as
boot0 used, which speeds up the locking and fixes the problem.
Signed-off-by: Jens Kuske <jenskuske@gmail.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Hans de Goede [Fri, 19 Aug 2016 13:25:41 +0000 (15:25 +0200)]
sunxi: display: Use PWM to drive backlight where applicable
When the backlight's pwm input is connected to a pwm output of the SoC,
actually use pwm to drive the backlight.
The mean reason for doing this is to fix the backlight turning off
for aprox. 1 second while the kernel is booting. This is caused by
the kernel actually using pwm to drive the backlight, so that it
can dim the backlight. First the pwm driver loads and switches the
pinmux for the pin driving the backlight's pwm input to the pwm
controller. Then about 1s later the actual backlight driver loads
and tells the pwm driver to actually update the pwm settings, which
have a power-on-reset value of "off".
An additional advantage is that this allows us to initatiate the
backlight at 80%, which is the kernel default, avoiding a brightness
change while the kernel loads.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed by: Peter Korsgaard <peter@korsgaard.com>
Hans de Goede [Fri, 19 Aug 2016 10:21:49 +0000 (12:21 +0200)]
sun5i: Add defconfig and dts file for the Empire Electronix M712 tablet
Add a defconfig and dts file for the Empire Electronix M712 tablet, this
is a 7" A13 tablet, with micro-usb (otg), headphone and micro-sd slots on
the outside. It uses a Goodix gt811 touchscreen controller, a RTL8188CTV
wifi chip and a DMART06 (1238a4) accelerometer.
The dts file is identical to the one submitted to the upstream kernel.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Hans de Goede [Thu, 18 Aug 2016 18:51:12 +0000 (20:51 +0200)]
sunxi: Sync dts files with upstream kernel
Sync dts files with the current (Aug 18th 2016) state of Maxime's
linux/sunxi/for-next repo.
Note this commit also updates configs/MSI_Primo81_defconfig,
adding: "# CONFIG_REQUIRE_SERIAL_CONSOLE is not set", this is necessary
because the tablet does not have a reachable uart so the dts sync
drops its serial0 alias.
Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
Hans de Goede [Thu, 18 Aug 2016 17:50:42 +0000 (19:50 +0200)]
sun6i: Add defconfig and dts file for tablets using the inet-q972 PCB
Add a defconfig and dts file for tablets using the generic inet-q972 PCB.
Tablets with this PCB feature a mini-hdmi output, micro-usb usb-host,
micro-usb usb-otg, 3.5mm headphone jack, a micro sd slot,
(mini) power-barrel and an usb wifi module.
This has been tested on a 9.7" 1024x768 qware qw tb9718-qhd tablet.
The dts files are identical to the ones submitted to the upstream kernel.
Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
Simon Baatz [Wed, 10 Aug 2016 08:15:42 +0000 (10:15 +0200)]
tools: kwboot: patch destaddr only for SoCs with header version 1
Commit f4db6c976cf ("arm: mvebu: Add runtime detection of UART (xmodem)
boot-mode") added a change to hdr->destaddr when dynamically patching an
image for UART boot mode. With this change, kwboot ceases to work on
Kirkwood.
Thus, let's change hdr->destaddr only when we are patching an image with
header version 1 (Orion and Kirkwood use header version 0).
Signed-off-by: Simon Baatz <gmbnomis@gmail.com> Fixes: f4db6c976cf ("arm: mvebu: Add runtime detection of UART (xmodem) boot-mode") Cc: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Kevin Smith <kevin.smith@elecsyscorp.com> Signed-off-by: Stefan Roese <sr@denx.de>
Chris Packham [Mon, 22 Aug 2016 08:52:49 +0000 (20:52 +1200)]
arm: mvebu: a38x: update serdes error handling
Ensure appropriate error messages are generated. Previously all errors
indicated that the serdes was already in use. Now appropriate error
messages are given.
Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
Chris Packham [Mon, 22 Aug 2016 00:38:39 +0000 (12:38 +1200)]
arm: mvebu: Add support for NAND interface on A-38x
The NAND interface on the Armada-38x series is similar to that on the
Armada-XP. The key difference is that the NAND ECC clock ratio is
provided via the DFX Server registers instead of the Core Clock.
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Dirk Eibach <eibach@gdsys.de> Signed-off-by: Stefan Roese <sr@denx.de>
Stefan Roese [Thu, 25 Aug 2016 13:20:01 +0000 (15:20 +0200)]
i2c: mvtwsi: Fix order of address bytes (high to low)
Patch f8a10ed1 [i2c: mvtwsi: Make address length variable] accidentally
inverted the sequence of address bytes sent to the I2C device. This
patch corrects this by sending the highest byte first and the lowest
byte last again.
Tested on theadorable Armada-XP board.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Mario Six <mario.six@gdsys.cc> Cc: Heiko Schocher <hs@denx.de>
Stephen Warren [Thu, 18 Aug 2016 16:53:33 +0000 (10:53 -0600)]
spi: tegra: fix hang in set_mode()
In tegra20_slink.c, the set_mode() function may be executed before the
SPI bus is claimed the first time, and hence the clocks to the SPI
controller may not be running. If so, any register read/write at this
time will hang the CPU. Fix this by ensuring the clock is running as soon
as the driver is probed. This is observed on the Tegra30 Beaver board.
Apply the same clock initialization fix to all other Tegra SPI drivers so
that if set_mode() is ever implemented there, the same bug will not appear.
Note that tegra114_spi.c already operates in this fashion.
The clock manipulation code is copied from claim_bus() to probe() rather
than moved. This ensures that any calls to set_speed() take effect; the
clock can't be set once during probe and left unchanged.
Fixes: 5cb1b7b395c0 ("spi: tegra20: Add support for mode selection") Cc: Mirza Krak <mirza.krak@hostmobility.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
Stephen Warren [Mon, 22 Aug 2016 22:46:55 +0000 (16:46 -0600)]
ARM: tegra: remove stale nvidia, bpmp I2C DT property
The nvidia,bpmp property is left over from an old BPMP I2C binding, and
shouldn't be present. Remove it from the SoC DT file, and update the
I2C driver not to parse it; the value wasn't used for anything any more
anyway.
Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
Stephen Warren [Thu, 18 Aug 2016 17:08:44 +0000 (11:08 -0600)]
ARM: tegra: fix Tegra186 SDHCI clock/reset names
The Tegra SDHCI binding dictates that the reseet name for the Tegra SDHCI
clock be "sdhci" not "sdmmc", and that the clock is accessed by index
rather than by name. Fix the Tegra186 DT and MMC driver to honor this.
Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
Tom Rini [Mon, 22 Aug 2016 23:37:56 +0000 (19:37 -0400)]
fs-test.sh: Correct check_md5() test with newlines
The fs-test.sh script expected there to be a \n\r style newline at the
end of the output. This is no longer the case, so use 'tr' to remove the
\r that we get.
Fixes: (c5917b4b054d "dm: serial-uclass: Move a carriage return before a
line feed") Signed-off-by: Tom Rini <trini@konsulko.com>
Dongpo Li [Mon, 22 Aug 2016 13:03:29 +0000 (21:03 +0800)]
net: mii: check phy advertising register when geting link status
When phy autoneg on, the link speed and duplex should be
determined by phy advertising register and
phy link partner ability register.
Check phy advertising register when geting phy link speed and
duplex if autoneg on.
Signed-off-by: Dongpo Li <lidongpo@hisilicon.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
karl beldan [Sat, 20 Aug 2016 08:56:53 +0000 (08:56 +0000)]
net: davinci_emac: Restore the internal MDIO accessors return values
The spatch series converting legacy drivers from miiphy_register to
mdio_register changed the return convention of the davinci_emac internal
MDIO accessors, making the internal code relying on it misbehaving:
no mdiodev get registered and U-Boot crashes when using net cmds in the
context of the old legacy net API.
ATM davinci_emac_initialize and cpu_eth_init don't return a proper value
in that case but fixing them would not avoid the crash.
This change is just a follow-up to the spatch pass, the MDIO accessors
of the mdiodev introduced by the spatch pass retain their proper values.
Signed-off-by: Karl Beldan <karl.beldan+oss@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
karl beldan [Mon, 15 Aug 2016 17:23:01 +0000 (17:23 +0000)]
net: davinci_emac: Invalidate only the received portion of a buffer
ATM when receiving a packet the whole buffer is invalidated, this change
optimizes this behaviour.
Signed-off-by: Karl Beldan <karl.beldan+oss@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
karl beldan [Mon, 15 Aug 2016 17:23:00 +0000 (17:23 +0000)]
net: davinci_emac: Round up top tx buffer boundaries for dcache ops
check_cache_range() warns that the top boundaries are not properly
aligned when flushing or invalidating the buffers and make these
operations fail.
This gets rid of the remaining warnings:
CACHE: Misaligned operation at range
Signed-off-by: Karl Beldan <karl.beldan+oss@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
karl beldan [Sun, 14 Aug 2016 15:03:15 +0000 (15:03 +0000)]
net: davinci_emac: Remove useless dcache ops on descriptors
ATM the rx and tx descriptors are handled as cached memory while they
lie in a dedicated RAM of the SoCs, which is an uncached area.
Removing the said dcache ops, while optimizing the logic and clarifying
the code, also gets rid of most of the check_cache_range() incurred
warnings:
CACHE: Misaligned operation at range
Signed-off-by: Karl Beldan <karl.beldan+oss@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Joe Hershberger [Mon, 15 Aug 2016 20:03:26 +0000 (15:03 -0500)]
net: nfs: Use the tx buffer to construct rpc msgs
Instead of always allocating a huge temporary buffer on the stack and
then memcpy()ing the result into the transmit buffer, simply figure out
where in the transmit buffer the bytes will belong and write them there
directly as each message is built.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Joe Hershberger [Mon, 15 Aug 2016 20:03:25 +0000 (15:03 -0500)]
net: nfs: Move some prints to debug statements
Much of the information is verbose and derived directly from the
environment. Only output in debug mode. This also saves about 300 bytes
from the code size.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
This patch enables NFSv3 support.
If NFSv2 is available use it as usual.
If NFSv2 is not available, but NFSv3 is available, use NFSv3.
If NFSv2 and NFSv3 are not available, print an error message since NFSv4 is not supported.
Tested on iMX6 sabrelite with 4 Linux NFS servers:
* NFSv2 + NFSv3 + NFSv4 server: use NFSv2 protocol
* NFSv2 + NFSv3 server: use NFSv2 protocol
* NFSv3 + NFSv4 server: use NFSv3 protocol
* NFSv3 server: use NFSv3 protocol
Signed-off-by: Guillaume GARDET <guillaume.gardet@free.fr> Cc: Tom Rini <trini@konsulko.com> Cc: joe.hershberger@ni.com Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Joe Hershberger [Mon, 15 Aug 2016 19:42:16 +0000 (14:42 -0500)]
net: nfs: Remove separate buffer for default name
There is no reason to store the default filename in a separate buffer
only to immediately copy it to the main name buffer. Just write it there
directly and remove the other buffer.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Alexander Graf [Thu, 18 Aug 2016 21:45:18 +0000 (23:45 +0200)]
efi_loader: Fix relocations above 64kb image size
We were truncating the image offset within the target image to 16 bits
which again meant that we were potentially overwriting random memory
in the lower 16 bits of the image.
This patch casts the offset to a more reasonable 32bits.
With this applied, I can successfully see Shell.efi assert because it
can't find a protocol it expects to be available.