Chen Liangjun [Tue, 21 Aug 2012 09:25:36 +0000 (17:25 +0800)]
ENGR00182456-1 HDMI: Add interface for HDMI audio management
In this patch, add support for:
1. Interface for HDMI audio to register PCM into HDMI core driver.
2. Interface for HDMI video driver to stop HDMI audio
3. Interface for HDMI video driver to inform the state of HDMI cable and
state of HDMI blank.
Anson Huang [Tue, 28 Aug 2012 09:43:01 +0000 (17:43 +0800)]
ENGR00221643 [MX6]Fix race condition of pfd 400 usecount
We can't modify the usecount of pfd 400M clock when ARM freq
is changed, as when the children of pfd 400M do clock enable/disable,
they will also modify this usecount, these two modification is
out of same lock protection. And this wrong usecount may lead to
pfd 400M or pll2 disabled accidently, and it will cause system hang!
Loren HUANG [Fri, 24 Aug 2012 02:05:30 +0000 (10:05 +0800)]
ENGR00221197-2 Update gpu driver to check Soc temperature
-Update gpu driver to check the SoC temperature, if the thermal_hot flag
is set by thermal driver. GPU3D clock will be slown down to the minimum
value, the clock will be recovery when the flag is cleared by thermal driver.
-This patch depends on ENGR00220848, without it, kernel build can't pass.
Sandor Yu [Mon, 27 Aug 2012 02:25:02 +0000 (10:25 +0800)]
ENGR00221444 HDMI: video mode wrong when bootup without HDMI cable
Bootup Android without HDMI cable plugin, then plugin HDMI cable,
video mode in /sys/class/graphics/fb0/mode not same as actually
HDMI work video mode.
The root cause is in video mode point to one of video mode in
original video modelist, but the modelist will be updated when
HDMI cable plug to new monitor.
If HDMI original worked video mode can work on new monitor,
the HDMI and framebuffer will not updated, so HDMI actually
work mode not same as /sys/class/graphics/fb0/mode
Updated fbi mode pointer even if video mode no changed
in case moselist is updated, the issue will fixed.
ENGR00221161 [MX6SL]- Add audio bus freq mode support.
Set DDR to 50MHz in low power audio playback.
AHB/AXI are at 24MHz.
Also fix correct usecount for PLL1 main clock. If not
it causes issues when pll1_sw_clk's parent is changed.
ENGR00221440 MX6x-Fix race-condition in checking bus_freq variables
Checking of the bus_freq variables and changing of the
bus/ddr frequency should be done under one mutex.
Else there is a race-condition that the variable changed
just after it was checked.
Also ensure that the bus freq is always increased before
the cpu freq is set to anything other than the lowest setpoint.
Else there is a possibility that the ARM is set to run from
PLL1 at higher frequency when bus/DDR are still at 24MHz.
This is dangerous since when system enters WAIT mode in
low bus freq state, PLL1 is set to bypass when ARM is being
sourced from it.
Chen Liangjun [Fri, 24 Aug 2012 04:32:36 +0000 (12:32 +0800)]
ENGR00219933 CS42888: abort delay powerdown if codec is on
CS42888 driver own 2 codec_dai for ESAI and ASRC P2P use. Due to the
delay power down mechanism, if a ASRC P2P stream is played right after
a finish of ESAI stream playback, ASRC P2P stream would be stop.
In this patch, do nothing in the delay powerdown flow if CS42888
codec is on.
make shi [Fri, 24 Aug 2012 05:53:49 +0000 (13:53 +0800)]
ENGR00221317-02 Mx6 USB host: set stop_mode_config when any USB host enabled
The Mx6 phy sometimes work abnormally after system suspend/resume if the 1V1
is off. So we should keep the 1V1 active during the system suspend if any USB
host enabled.
- Add stop_mode_config to 1 with refcount
- Add mutex to protect the refcount and HW_ANADIG_ANA_MISC0 register
- If stop_mode_config is set as 1, the otg vbus wakeup system will be supported
Change AXI_CLK to be sourced from PLL3_PFD1_540MHz, so that it
can run at 270MHz on MX6DL/S. This is required for improving
VPU performance.
Change AXI_CLK to be sourced from periph_clk just before the DDR
freq is going to be dropped to 24MHz/50MHz. Change it back
to PLL3_PFD1_540 when the DDR freq is back at 400MHz.
Peter Chen [Thu, 23 Aug 2012 08:29:55 +0000 (16:29 +0800)]
ENGR00221217 usb: device: fix usb_state incorrect problem after pc sends resume
At pc sends suspend/resume case, the udc_controller->usb_state should
keep unchange during the suspend/resume process, at former code, the
fsl_udc_resume set udc_controller->usb_state to USB_STATE_ATTACHED
unconditionally. In fact, USB_STATE_ATTACHED stands for initial state
and should be set when we try to run controller.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
Robin Gong [Thu, 23 Aug 2012 03:45:22 +0000 (11:45 +0800)]
ENGR00221102-2 MX6Q: increase VPU frequence to 352Mhz
Increase VPU frequency to 352Mhz for TV box, use pll2_pfd_400M.To avoid impact
other code which assume ARM clock sourcing from pll2_pfd_400M, change cpu
setpoint of 396M to 352M. and disable bus freq adjust.
add CONFIG_MX6_VPU_352M to choose it, default is disabled. Signed-off-by: Robin Gong <B38343@freescale.com>
Robin Gong [Thu, 23 Aug 2012 03:43:45 +0000 (11:43 +0800)]
ENGR00221102-1 MX6Q: increase VPU frequence to 352Mhz
Increase VPU frequency to 352Mhz for TV box, use pll2_pfd_400M.To avoid impact
other code which assume ARM clock sourcing from pll2_pfd_400M, change cpu
setpoint of 396M to 352M. and disable bus freq adjust.
add CONFIG_MX6_VPU_352M to choose it, default is disabled.
Sandor Yu [Wed, 22 Aug 2012 02:57:50 +0000 (10:57 +0800)]
ENGR00220538 HDMI: Clock mismatch in suspend&resume when video playback
In suspend/resume and HDMI plugin/plugout stress test,
sometimes fbcon will call fb_set_par with
parameter fb_var_screeninfo that xres anfd yres is zero.
MX frame buffer driver can not correct handle this casue,
it will cause IPU pixel clock gating/ungating mismatch.
Check fb_var_screeninfo parameter in mxcfb_check_var and
mxcfb_set_par function, returned if xres,yres zero.
ENGR00220696 [MX6SL]-Reduce IDLE mode power consumption.
When ARM enters WFI in low power IDLE state, float the DDR
IO pins to drop the power on the VDDHIGH rail.
Need to run WFI code from IRAM since DDR needs to be
put into self-refresh before changing the IO pins.
Drop AHB to 8MHz and DDR to 1MHz when ARM is in WFI when
in IDLE state.
Set IPG_PERCLK to run at 3MHz, since we want to maintain a
1:2.5 ratio between PERCLK to AHB_CLK.
Ryan QIAN [Thu, 2 Aug 2012 01:46:53 +0000 (09:46 +0800)]
ENGR00219601-01: mmc: queue: enlarge the size of bounce buffer for SDMA.
- set bounce buffer to 512KB from 64K, which is hw max seg size for
fsl sd host controller
- by enlarging the size of bounce buffer, it will reduce the number
of irq on writing by merging small requests into a large one, which
will improve writing throughput.
- the side effect is that the reading throughput of 512KB bounce buffer
is lower than the one of 64KB bounce buffer, when cpu freq is at 200Mhz.
Test Env:
1. MX6DL SabreSD board
2. On board eMMC (Sandisk: SDIN5C2-8G) running at 8-bit DDR @ 52Mhz
3. Test commands:
3.1 Writing test command:
# dd if=/dev/zero of=/dev/mmcblk0 bs=1M count=100 conv=fsync
3.2 Reading test command:
# echo 1 > /proc/sys/vm/drop_caches
# echo 1 > /proc/sys/vm/drop_caches
# sleep 1
# dd if=/dev/mmcblk0 of=/dev/null bs=1M count=100
Liu Ying [Mon, 20 Aug 2012 05:59:40 +0000 (13:59 +0800)]
ENGR00220734 IPUv3 fb:Rewind eof irq sync mechanism back
This patch changes to use original sync mechanism for eof
irq, which may improve pan-display or alpha buffer update
performance.
1) Initialize flip_completion and alpha_flip_completion
only once when fb is initialized instead of initializing
it every time when pan display is called.
2) Clear and enable eof irq after selecting buffer ready.
In this way, we have no chance to lose an interrupt, as
selecting a new buffer ready doesn't make the eof irq
come(from the newly selected buffer) before we clear the irq
status and enable the irq. Otherwise, if we clear the irq
status and enable the irq before we doing down in pan-display
or alpha buffer update, we have chance(users call pan-display or
alpha buffer update faster than vsync frequency and blocks at
down()) to clear an unhandled irq, which may cause performance
issue.
Robin Gong [Mon, 20 Aug 2012 11:24:28 +0000 (19:24 +0800)]
ENGR00220776 mx6dl_arm2: ECSPI pin config overlaped by epdc
ECSPI pin MX6DL_PAD_EIM_D17__ECSPI1_MISO is configured overlap by epdc
MX6DL_PAD_EIM_D17__GPIO_3_17, so that SPI-NOR flash can't work normally.
From schematic of ARM2 board, epdc and spi share this pin if plug epdc
daughter board. But SPI-NOR is on ARM2 mother board, so it should be config
well firstly. So we make sure SPI-NOR work successfully by default. But if
enable epdc , SPI-NOR on ARM2 will work fail.
make shi [Tue, 21 Aug 2012 09:51:18 +0000 (17:51 +0800)]
ENGR00220833 mx6sl: USB hsic: enable mx6sl hsic function
- Set MX6SL_PAD_HSIC_DAT and MX6SL_PAD_HSIC_STROBE pad DDR attribute as DDR3
- Add imx6sl_add_fsl_ehci_hs and imx6sl_add_fsl_usb2_hs_wakeup in usb_h2.c
Anson Huang [Sat, 18 Aug 2012 17:12:59 +0000 (01:12 +0800)]
ENGR00220370 [MX6]Fix BUS freq suspend/resume fail in low bus mode
1. BUS freq's set low bus setpoint using delat work, which
didn't have mutex lock, so in some scenarios, set high bus
freq function can be called at the same time, we need to move
mutex lock into these two routine;
2. Using pm notify to make sure bus freq set to high setpoint
before supend and restore after resume.
Rong Dian [Mon, 20 Aug 2012 12:23:00 +0000 (20:23 +0800)]
ENGR00220794 imx6 thermal: add suspend and resume for thermal_sys class
1.Avoiding system wrong reboot caused by error temperature without
cancel_delayed_work before entering into suspend,so to cancel
thermal_zone_device temperature polling temperature delayed_work
before entering into suspend, reenable polling temperature delayed_work
after entering into resume.
2.In anatop_thermal_suspend, turn off alarm firstly
make shi [Tue, 14 Aug 2012 07:02:00 +0000 (15:02 +0800)]
ENGR00218789 mx6: clock: keep PLL3 enable and power bit all the time
In order to support USB remote wake up, we should keep the PLL3 enable
and power bit all the time. We use BM_ANADIG_ANA_MISC2_CONTROL0 to control
the PLL3 power off PLL3's power when PLL3 is not used by other module.
PLL3 power design logic as below:
usb1_pll_480_ctrl_power_int=hw_anadig_usb1_pll_480_ctrl_power && ((disable_480_p
ll_n && ~hw_anadig_ana_misc2_control0 )||pwrctl_otg_wakeup || utmi_otg_suspendm)
There are two basic case:
- If USB is active and USB remote wakeup happen , Pll3 will be turn on.
- If USB is not active and no remote wakeup happen, the PLL3 will be controlled
by hw_anadig_ana_misc2_control0 bit.
ENGR00220818 [MX6SL] - Ensure the Enable bit is set for all the PLLs.
The ENABLE bit is not set for all PLLs by default. Ensure
that the pll_enable() function sets this bit for all PLLs.
The pll_disable() function should not clear this bit
for PLL1, PLL2, PLL3 and PLL7. The output of these PLLs
maybe used even if they are bypassed.
Hongzhang Yang [Mon, 20 Aug 2012 08:11:21 +0000 (16:11 +0800)]
ENGR00220732-1 Remove clk_disable in VPU driver interrupt handling
Original design is VPU lib API StartOneFrame() enables clock, and VPU
driver disables clock after codec done interrupt has been received.
However there are known issues of interrupt handling as below:
- VPU interrupt handling callback is not scheduled in time causing work
queue overflow
- JPU done interrupt is not received because JPU issues it while JPU
buffer empty interrupt is still being served
- VPU finishes a frame (!vpu_IsBusy) but VPU done interrupt is not
received
All above will cause clk_disable in interrupt handling not called,
thus VPU clock count increases by 1.
So I plan to resolve clock unbalance issue first by removing
clk_disable from VPU driver interrupt handling. Interrupt problem
will not affect clock issue any longer.
1. Driver: remove clk_disable from vpu_worker_callback
2.1. Lib: remove clk_enable from API GetOutputInfo
2.2. Lib: avoid disabling VPU clock when VPU is busy in SWReset
3. Test: replace GetOutputInfo with SWReset in decoder_close /
encoder_close
Signed-off-by: Hongzhang Yang <Hongzhang.Yang@freescale.com>
Lionel Xu [Fri, 17 Aug 2012 08:06:32 +0000 (16:06 +0800)]
ENGR00220446 ESAI: channel swapped occasionally when playing stereo wav
There is channel swap happened when playing stereo wav. According to the spec,
the initial words should be written to the ETDR register, at least one word
per enabled transmitter slot, to avoid any potential problem.
Yuxi Sun [Sat, 18 Aug 2012 06:43:26 +0000 (14:43 +0800)]
ENGR00220706 IPU Add more timeout when wait for the csi end of frame
If this timeout is too small, it can't meet the require of some large
frame such as 2592x1944 and 1080p, and the IDMAC maybe in a chaotic
state, so at last access some invalid space caused the system hang.
ENGR00220496 MX6SL:Add low power IDLE mode optimizations.
Add support for DDR freq change code in IRAM.
Change PLL2 to bypass mode so that DDR is running off 24MHz OSC
directly.
ARM is now sourced from PLL1 (running at 800MHz) in this mode.
This is required for the next step in IDLE mode optmization
where all PLLs will be disabled when ARM enters WFI.
make shi [Thu, 16 Aug 2012 07:44:11 +0000 (15:44 +0800)]
ENGR00220440 Mx6:USB device: clear OWIE before phy out of low power mode
There is a limitation on mx6 phy low power flow. During phy enter low power mode
and out of low power mode with OWIE bit active,there will be abnormal usb wakeup
interrupt happen. So we should clear OWIE bit before phy out of low power mode.
Chen Liangjun [Thu, 16 Aug 2012 11:31:49 +0000 (19:31 +0800)]
ENGR00219926-2 ASRC: use PAIR B for ASRC ideal ratio convert
When use ASRC ideal ratio mode for convert, PAIR C can't work properly.
However, when use PAIR C for internal ratio mode or non ratio mode
convert, it can work properly.
In this patch, Use PAIR B for 6 channel convert as a workaround.
Chen Liangjun [Thu, 16 Aug 2012 11:20:51 +0000 (19:20 +0800)]
ENGR00219926-1 ESAI ASRC: use ideal ratio for ASRC P2P playback
When use no ideal-ratio mode for ESAI playback, CPU should provide
accurate clock for input clock, which means input clock should be
divided by input sample rate. However, all our clock is from 24M crystal
and if the input sample rate equal to 44.1k or so, CPU can't provide
these clock.
In this patch, use ideal ratio mode thus CPU need not provide accurate
clock which can be divided by 44.1k.
Chen Liangjun [Thu, 16 Aug 2012 13:11:46 +0000 (21:11 +0800)]
ENGR00220595 ESAI ASRC: add support for 'aplay *'
When play audio in the way of aplay *, shutdown function would not be
called and ASRC configuration would not be reconfigured. In this case,
playback would sound noise.
In this patch, put ASRC release operation into hw_free().
Gary Zhang [Thu, 16 Aug 2012 07:36:36 +0000 (15:36 +0800)]
ENGR00220027-1 IOMUX: add api for special pad bits configuration
Original pad configuration does not provide enough bitfield width
to config some bits, such as LVE bit and DDR_SEL bits.
like gpr configuration, add a api to implement these special
bits pad configuration, and user may call this api in board file.
1. To avoid ASRC underflow error, ASRC driver would prefill ASRC input
FIFO with 160 samples. However, 160 can't be divided by 6. In this case,
channel data miss alignment. In this patch, prefill ASRC input
FIFO with 120, which can be divided by 2,4,6,8.
2. While start P2P playback, ESAI driver would first start SDMA, then
ASRC, and last ESAI. While start ESAI, the data is not ready, thus ESAI
underrun would happens and channel data miss alignment. In this patch,
delay 1 ms between ASRC's start and ESAI's start.
Peter Chen [Tue, 14 Aug 2012 07:35:32 +0000 (15:35 +0800)]
ENGR00220341-2 usb: add spin_lock_irqsave protect for pdata->lowpower
pdata->lowpower may be accessed at two drivers together, assumed
the situation that host/device set phy to low power mode but
still not set the flag lowpower, at this time the wakeup occurs, as
the flag lowpower is still not set, the interrupt will be infinite loop
as no one will serve it.
This commit is for driver code and add protect at driver.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
Peter Chen [Tue, 14 Aug 2012 07:16:49 +0000 (15:16 +0800)]
ENGR00220341-1 usb: add spin_lock_irqsave protect for pdata->lowpower
pdata->lowpower may be accessed at two drivers together, assumed
the situation that host/device set phy to low power mode but
still not set the flag lowpower, at this time the wakeup occurs, as
the flag lowpower is still not set, the interrupt will be infinite loop
as no one will serve it.
This commit is for MSL code and add protect at wakeup interrupt.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
Robby Cai [Thu, 16 Aug 2012 07:14:19 +0000 (15:14 +0800)]
ENGR00220512-2: mx6sl evk: keep NVCC_1V8 and NVCC_1.2V always on
Keep the corresponding rail of pfuze: VGEN4 and VGEN1 "always on".
It's required for any IO pad configured as this voltage.
It has to be always on, even in DSM mode.
Anson Huang [Wed, 15 Aug 2012 18:45:11 +0000 (02:45 +0800)]
ENGR00220388 [MX6]Adjust SOC/PU voltage according to datasheet
SOC/PU voltage need to following some rules according to latest
datasheet:
1. SOC/PU CAP voltage must be 1.15V <= SOC/PU <= 1.3V;
2. SOC and PU must be same as they don't have level shift;
3. Adjust previous wrong voltage setting.
If SOC/PU voltage is too low, may cause system crash on some
chips, we have a board that easily crash with GPU working and
doing some tar operation, with this voltage adjust, this issue
fixed.
Liu Ying [Tue, 14 Aug 2012 10:36:38 +0000 (18:36 +0800)]
ENGR00219872-2 MX6Q SabreSD:Disable LVDS CABC function
This patch sets CABC_EN0/1 to low to disable LVDS panel
CABC function so that LVDS backlight will not be turned
by the LVDS panel automatically so that we may avoid
annoying unstable backlight issue.
Signed-off-by: Rong Dian <b38775@freescale.com> Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit a169940fb39216e644018304e3a3bdaca61ea88a)
Robby Cai [Mon, 13 Aug 2012 08:12:31 +0000 (16:12 +0800)]
ENGR00220161: imx6sl: Add EVK board Support
- Copied the board file from ARM2, and consolidated the pinmux setting.
- Added a new pmic file for EVK.
- Added a new mach type.
- Added board_is_mx6sl_evk() API for late use if needed.
- Updated the defconfig
Liu Ying [Fri, 10 Aug 2012 10:08:42 +0000 (18:08 +0800)]
ENGR00219859 MXC V4L2 capture:Pwr down/on opened cam
Currently, we support 2 cameras, which are relevant to
2 video devices respectively. This patch checks if video
device is opened to determine whether we need to power
down/on relevant camera when doing suspend/resume.
Also, this patch protects capture resources with busy
lock semaphore.
Xinyu Chen [Wed, 15 Aug 2012 05:36:24 +0000 (13:36 +0800)]
ENGR00219856-2 mxc pwm: do pwm software reset after disable
When android doing suspend/resume, we may meet the issue of
backlight is not on (pwm pin no signal) after system wakeup.
The root cause is PWM sample can not be set into the PWMSAR
register after pwm being used and disabled for a while.
The value read back after write is 0 when this issue happens.
Do a software reset after pwm disable can resolve this
issue, this makes sure the next sample update is correct.
Xinyu Chen [Wed, 15 Aug 2012 05:32:06 +0000 (13:32 +0800)]
ENGR00219856-1 mx6q sabresd: add debounce to gpio key
Add a 1ms debounce to the gpio key to avoid
unexpected gpio status read from gpio_key driver's
workqueue. This issue happens on android's resume stage,
sometimes the framework get more than one up key even
user press the power key once.
Sandor Yu [Tue, 14 Aug 2012 12:14:17 +0000 (20:14 +0800)]
ENGR00180117 HDMI: No audio output in 1080P on some TV
Some TV support specific video mode that different with
CEA standard, and it's pixel clock not comply CEA standard.
But audio configuration paramter N and CTS should follow CEA standard.
So audio may not work in these specific video mode.
Filter video mode get from EDID, only keep standard CEA video mode
in the modelist.
Nancy Chen [Tue, 14 Aug 2012 14:49:05 +0000 (09:49 -0500)]
ENGR00220297 [MX6SL]: Fix AHB clock not correct after kernel boot
1. Fix AHB_CLK is not right after system up. ahb_clk is 49.5MHz
after system up. It should be 132MHz.
2. Remove the voltage changes for VDDSOC_CAP since there are vddarm
voltage changed in CPUFREQ and vddsoc voltage and vddarm voltage
should meet the constraint condition: VDDSOC > VDDARM - 50mV. Therefore
VDDSOC voltage changes will be implemented in CPUFREQ.
Robin Gong [Tue, 14 Aug 2012 07:27:27 +0000 (15:27 +0800)]
ENGR00220340 mx6sl pfuze: keep NVCC_1V8 and NVCC_1.2V always on
1. Keep the corresponding rail of pfuze:VGEN4 and VGEN1 "always on".
2. mx6sl enable LDO bypass default, which can't including adjust soc
and pu regulator. To support old LDO bypass code, need check soc_regulator
and pu_regulator, otherwise, system will crash.
Add on-demand governor's threshold for FEC to improves performance.
i.mx6q TO1.1 tx throughput only is 64Mbps in 100Mbps mode on sabresd
platform, after the change, the throughput can reach to 95Mbps for tx.
Yuxi Sun [Fri, 10 Aug 2012 05:52:32 +0000 (13:52 +0800)]
ENGR00219173 V42L overlay Add back ground overlay support
Add back ground overlay support based on ipu device driver.
Default using this driver instead of prp_vf driver for back
ground overlay. when want using prp_vf back ground overlay,
unselect ipu deviece overlay drivers and choose to build
related driver as build-in.
Chen Liangjun [Sun, 12 Aug 2012 15:03:01 +0000 (23:03 +0800)]
ENGR00220172 ESAI ASRC: put all asrc pair release operation to shutdown()
When use ASRC for ESAI P2P playback, ESAI driver would release ASRC pair
resource immediately after ASRC function's error return.It may
introduce risk that in ESAI machine driver's shutdown(), ASRC resource
release operation may be double called. In this case, system hang
happens due to ASRC register's operation with no clock.
In this patch, let all ASRC resource release operation in ESAI machine
driver's shutdown().
Chen Liangjun [Sat, 11 Aug 2012 07:36:20 +0000 (15:36 +0800)]
ENGR00220181-2 HDMI SDMA: workround for HDMI SDMA audio no sound issue
Issue: When playback HDMI audio in SDMA stress test, HDMI audio may stop
caused by SDMA channel's failing to work. While checking the SDMA register
and HDMI module stauts, we found that SDMA fall to an unknown error state.
The issue is detected both in RIGEL TO1.1 and ARIK TO1.2.
This patch introduces a workround for this issue: For the memory passed
to SDMA core, HDMI driver would allocate it with the attribute of C=0,
B=0 instead of C=0, B=1. This patch have be tested in RIGEL TO1.1 for
about 60 hours, no issue happens.
Robin Gong [Sat, 11 Aug 2012 09:41:52 +0000 (17:41 +0800)]
ENGR00220154 GPT mx6: move mx6_timer_rate to clock.c
System will report oops as below. To fix it we will move mx6_timer_rate to
clock.c, so that we can avoid use clk_get_sys which cause schedule after
spin_lock.
oops log:
BUG: scheduling while atomic: kinteractiveup/1403/0x00000002
Modules linked in:
(unwind_backtrace+0x0/0xfc) from [<804f05f0>] (__schedule+0x4b8/0x6b0)
(__schedule+0x4b8/0x6b0) from [<804f12ac>] (__mutex_lock_slowpath+0x138/0x208)
(__mutex_lock_slowpath+0x138/0x208) from [<804f13b4>] (mutex_lock+0x38/0x3c)
mutex_lock+0x38/0x3c) from [<803b9134>] (clk_get_sys+0x1c/0xec)
(clk_get_sys+0x1c/0xec) from [<8005f814>] (mx6_timer_rate+0x14/0x7c)
(mx6_timer_rate+0x14/0x7c) from [<80056a20>] (_clk_gpt_get_rate+0x18/0x2c)
(_clk_gpt_get_rate+0x18/0x2c) from [<8005e89c>] (clk_get_rate+0x34/0x40)
(clk_get_rate+0x34/0x40) from [<80055f3c>] (_clk_pll_enable+0xa8/0x1ec)
(_clk_pll_enable+0xa8/0x1ec) from [<80056088>] (_clk_pll1_enable+0x8/0x20)
(_clk_pll1_enable+0x8/0x20) from [<80056998>] (_clk_arm_set_rate+0x278/0x2e8)
(_clk_arm_set_rate+0x278/0x2e8) from [<8005e824>] (clk_set_rate+0x54/0x68)
(clk_set_rate+0x54/0x68) from [<80061660>] (set_cpu_freq+0xb8/0x160)
(set_cpu_freq+0xb8/0x160) from [<800618b4>] (mxc_set_target+0xf0/0x20c)
(mxc_set_target+0xf0/0x20c) from [<80372388>](__cpufreq_driver_target+0x54/0x60) Signed-off-by: Robin Gong <b38343@freescale.com>
Robin Gong [Sat, 11 Aug 2012 08:36:35 +0000 (16:36 +0800)]
ENGR00220153 cpufreq mx6: new cpu set point and add VDDSOC/PU adjust
1.add new cpu setpoint: replace 498Mhz with 672Mhz,and remove 198Mhz.
but now 498Mhz seems not stable enough, comment now, test enough to
add it. Rigel kept unchange now.
2.support adjusting VDDSOC/VDDPU when cpu frequency change.
Steve Cornelius [Thu, 9 Aug 2012 22:26:33 +0000 (15:26 -0700)]
ENGR00216259 caam: improve RNG4 initialization process
Early versions of this driver used a set of entropy generation parameters
inherited from QorIQ devices. Those parameters were a hardcoded set
based upon internally-suggested values, and worked well on QorIQ. However,
for certain mx6 devices, oscillator values were found to be exceeding
the upper limit, and so RNG instantiation was failing in those cases.
This code improves initialization by (a) making sure the oscillator
divider is set to a known value, and (b) converting the parameter selection
to a symbolic compiler-generated form, instead of using embedded
magic number constants.
The calculation is now based on the definition of RNG4_ENT_CLOCKS_SAMPLE,
which defaults to 1600 unless overridden by something. The lower limit
is then set as /4, and the upper limit set to *8.
Tested-by: Minnick Michael-B21710 <b21710@freescale.com> Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com> Signed-off-by: Jason Liu <r64343@freescale.com>
Anson Huang [Thu, 9 Aug 2012 16:35:59 +0000 (00:35 +0800)]
ENGR00220022 [MX6]Add necessary protection to bus freq variables and function
All bus freq related variables and function calls need to be protected by
mutex, or these variables may be wrong and result in triggering bus freq
change by mistake, it will impact many modules function.
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