Stefan Roese [Mon, 26 Nov 2012 14:46:12 +0000 (15:46 +0100)]
ARM: sunxi: Add missing sun4i.dtsi file
Patch f055f1f6 [ARM: sunxi: Add sun4i and cubieboard support] missed
this sun4i.dtsi include file. This patch finally brings it upstream
enabling support for sun4i boards.
Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Olof Johansson [Mon, 26 Nov 2012 07:34:36 +0000 (23:34 -0800)]
Merge tag 'imx-soc-1' of git://git.pengutronix.de/git/imx/linux-2.6 into next/soc
From Sascha Hauer:
ARM i.MX SoC updates for v3.8
* tag 'imx-soc-1' of git://git.pengutronix.de/git/imx/linux-2.6:
ARM i.MX6: remove gate_mask from pllv3
ARM i.MX6: Fix ethernet PLL clocks
ARM i.MX6: rename PLLs according to datasheet
ARM i.MX6: Add pwm support
ARM i.MX51: Add pwm support
ARM i.MX53: Add pwm support
ARM: mx5: Replace clk_register_clkdev with clock DT lookup
Olof Johansson [Fri, 23 Nov 2012 16:25:39 +0000 (08:25 -0800)]
Merge branch 'depends/gpio-devel' into next/soc
Pulling in a newer version of the depend branch from the gpio tree,
since there was some randconfig breakage introduced at the version we
had, and we want to keep those things as bisectable as possible. It's
not bad enough to warrant a rebase though, so there'll be a window of
exposure to this.
* depends/gpio-devel:
gpio: SPEAr: add spi chipselect control driver
gpio: gpio-max710x: Support device tree probing
gpio: twl4030: Use only TWL4030_MODULE_LED for LED configuration
gpio: tegra: read output value when gpio is set in direction_out
gpio: pca953x: Add compatible strings to gpio-pca953x driver
gpio: pca953x: Register an IRQ domain
gpio: mvebu: Set free callback for gpio_chip
gpio: tegra: Drop exporting static functions
gpio: tegra: Staticize non-exported symbols
gpio: tegra: fix suspend/resume apis
gpio-pch: Set parent dev for gpio chip
gpio: em: Fix build errors
Sascha Hauer [Thu, 22 Nov 2012 09:18:41 +0000 (10:18 +0100)]
ARM i.MX6: remove gate_mask from pllv3
Now that the additional enable bits in the enet PLL are handled
as gates, the gate_mask is identical for all plls. Remove the
gate_mask from the code and use the BM_PLL_ENABLE bit for
enabling/disabling the PLL.
Sascha Hauer [Wed, 21 Nov 2012 13:42:31 +0000 (14:42 +0100)]
ARM i.MX6: Fix ethernet PLL clocks
In current code the ethernet PLL is not handled correctly. The PLL runs at 500MHz
and has different outputs. Only the enet reference clock is implemented. This
patch changes the PLL so that it outputs 500MHz and adds the additional outputs
as dividers. This now matches the datasheet which says:
> This PLL synthesizes a low jitter clock from 24 MHz reference clock.
> The PLL outputs a 500 MHz clock. The reference clocks generated by this PLL are:
> • Ref_PCIe = 125 MHz
> • Ref_SATA = 100 MHz
> • Ref_ethernet, which is configurable based on the PLL_ENET[1:0] register field.
Sascha Hauer [Thu, 22 Nov 2012 09:05:13 +0000 (10:05 +0100)]
ARM i.MX6: rename PLLs according to datasheet
In recent reference manuals the PLLs were renumbered. PLL8 now is
PLL6 and vice versa. Change the code according to the reference
manual to avoid confusion.
Thomas Abraham [Wed, 10 Oct 2012 00:41:12 +0000 (09:41 +0900)]
pinctrl: exynos5440: add pinctrl driver for Samsung EXYNOS5440 SoC
Add a new pinctrl driver for Samsung EXYNOS5440 SoC. The pin controller
module in EXYNOS5440 is different from the pin controller found on other
Samsung SoC. Hence, the pin controller driver for EXYNOS5440 SoC is
independent of the Samsung pinctrl framework.
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Kukjin Kim [Wed, 24 Oct 2012 04:41:15 +0000 (13:41 +0900)]
ARM: dts: add initial dts file for EXYNOS5440, SSDK5440
This patch adds initial dts file for EXYNOS5440 SoC and adds the
dts file for SSDK5440 board which is a kind of reference board.
More properties will be added later.
Olof Johansson [Wed, 21 Nov 2012 18:18:54 +0000 (10:18 -0800)]
Merge branch 'samsung/pinctrl' into next/soc
From Kukjin Kim:
Here is Samsung DT for v3.8 and this is including DT for EXYNOS4X12
SoC, SMDK4412 board, pinctrl for exynos4x12, TMU, MFC, SATA and SATA
PHY.
As I commented on [4/7], this branch merged pinctrl/samsung to support
pinctrl for exynos4x12 without useless merge conflicts.
* samsung/pinctrl:
pinctrl: samsung: Update error check for unsigned variables
pinctrl: samsung: Add support for EXYNOS4X12
Documentation: Update samsung-pinctrl device tree bindings documentation
pinctrl: samsung: Add GPIO to IRQ translation
pinctrl: exynos: Set pin function to EINT in irq_set_type of wake-up EINT
pinctrl: samsung: Use per-bank IRQ domain for wake-up interrupts
pinctrl: samsung: Use one GPIO chip per pin bank
pinctrl: exynos: Use one IRQ domain per pin bank
pinctrl: samsung: Include bank-specific eint offset in bank struct
pinctrl: samsung: Hold pointer to driver data in bank struct
pinctrl: samsung: Match pin banks with their device nodes
ARM: dts: exynos4210-pinctrl: Add nodes for pin banks
pinctrl: samsung: Distinguish between pin group and bank nodes
pinctrl: samsung: Remove static pin enumerations
pinctrl: samsung: Assing pin numbers dynamically
pinctrl: samsung: Do not pass gpio_chip to pin_to_reg_bank
pinctrl: samsung: Detect and handle unsupported configuration types
Olof Johansson [Wed, 21 Nov 2012 17:58:28 +0000 (09:58 -0800)]
Merge branch 'clps711x/soc2' into next/soc
From Alexander Shiyan:
The main direction of this patchset - approaching the platform to the
possibility of using configurations with multiple platforms in a single
kernel. Added support of the majority of the necessary kernel symbol.
Also part of the driver code used only for the platform was moved to the
board code and converted to the use of standard drivers.
* clps711x/soc2:
MAINTAINERS: Add ARM CLPS711X entry
ARM: clps711x: Update defconfig due latest changes and new kernel symbols
ARM: clps711x: Rename board files to match functionality
ARM: clps711x: edb7211: Add support for NOR-Flash
ARM: clps711x: Moving backlight controls of framebuffer driver to the board
ARM: clps711x: p720t: Special driver for handling NAND memory is removed
ARM: clps711x: Moving power management of framebuffer driver to the board
ARM: clps711x: autcpu12: Special driver for handling NAND memory is removed
ARM: clps711x: Unused empty "ACK" calls for IRQ-chips removed
ARM: clps711x: Add FIQ interrupt handling
ARM: clps711x: Implement usage "MULTI_IRQ_HANDLER" kernel option for a platform
ARM: clps711x: Implement usage "SPARSE_IRQ" kernel option for a platform
ARM: clps711x: cdb89712: Special driver for handling memory is removed
ARM: clps711x: Always select AUTO_ZRELADDR for a platform
ARM: clps711x: p720t: Unneeded inclusion of head-sa1100.S removed
ARM: clps711x: Transform clps711x-framebuffer to platform driver and use it
ARM: clps711x: p720t: Using "leds-gpio" driver for LED control
ARM: clps711x: Using platform_driver for ethernet device
Alexander Shiyan [Sat, 17 Nov 2012 13:57:20 +0000 (17:57 +0400)]
ARM: clps711x: Moving backlight controls of framebuffer driver to the board
This patch moves the backlight controls for clps711x-framebuffer driver
to the board code. To control we use "generic-bl" driver.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
[olof: fixed space/tab whitespace in drivers/video/clps711xfb.c] Signed-off-by: Olof Johansson <olof@lixom.net>
Alexander Shiyan [Sat, 17 Nov 2012 13:57:15 +0000 (17:57 +0400)]
ARM: clps711x: Add FIQ interrupt handling
CLPS711X-target CPU can have a several FIQ interrupts. With this patch
we adds handling for a one which will be used for ALSA PCM later.
Since FIQ have a separate handler we only add "mask" and "unmask" calls
which will used for enable/disable_irq functions.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Olof Johansson <olof@lixom.net>
Olof Johansson [Wed, 21 Nov 2012 17:39:13 +0000 (09:39 -0800)]
Merge branch 'depends/gpio-devel' into next/soc
This is required for some of the clps711x series, so we're bringing in
the dependency explicitly.
By Linus Walleij (5) and others
via Linus Walleij
* depends/gpio-devel:
GPIO: clps711x: use platform_device_unregister in gpio_clps711x_init()
gpio/tc3589x: convert to use the simple irqdomain
gpio/em: convert to linear IRQ domain
gpio/mvebu: convert to use irq_domain_add_simple()
gpio/tegra: convert to use linear irqdomain
gpiolib: unlock on error in gpio_export()
gpiolib: add gpio get direction callback support
GPIO: clps711x: Fix direction logic for PORTD
GPIO: clps711x: Fix return value for gpio_clps711x_get
gpiolib: Refactor gpio_export
GPIO: vt8500: Add extended gpio bank for WM8505/WM8650
gpio: clps711x: delete local <mach/gpio.h> header
GPIO: Add support for GPIO on CLPS711X-target platform
DA9055 GPIO driver
gpio/gpio-omap: Use existing pointer to struct device
gpio/gpio-pl061: Covert to use devm_* functions
Olof Johansson [Wed, 21 Nov 2012 09:12:49 +0000 (01:12 -0800)]
Merge tag 'highbank-debugll-cleanup' of git://sources.calxeda.com/kernel/linux into next/soc
From Rob Herring:
Use common debug_ll_init function and remove the static mapping code
from mach-highbank.
* tag 'highbank-debugll-cleanup' of git://sources.calxeda.com/kernel/linux:
ARM: highbank: use common debug_ll_io_init
ARM: implement debug_ll_io_init()
Olof Johansson [Wed, 21 Nov 2012 09:06:16 +0000 (01:06 -0800)]
Merge branch 'vexpress-clk-soc' of git://git.linaro.org/people/pawelmoll/linux into next/soc
From Pawel Moll:
* 'vexpress-clk-soc' of git://git.linaro.org/people/pawelmoll/linux:
ARM: vexpress: Remove motherboard dependencies in the DTS files
ARM: vexpress: Start using new Versatile Express infrastructure
ARM: vexpress: Add config bus components and clocks to DTs
mfd: Versatile Express system registers driver
mfd: Versatile Express config infrastructure
Olof Johansson [Wed, 21 Nov 2012 09:06:05 +0000 (01:06 -0800)]
Merge branch 'depends/clk' into next/soc
From Mike Turquette:
* depends/clk:
clk: Common clocks implementation for Versatile Express
clk: Versatile Express clock generators ("osc") driver
CLK: clk-twl6040: Initial clock driver for OMAP4+ McPDM fclk clock
clk: fix return value check in sirfsoc_of_clk_init()
clk: fix return value check in of_fixed_clk_setup()
clk: ux500: Update sdmmc clock to 100MHz for u8500
clk: ux500: Support prcmu ape opp voltage clock
mfd: dbx500: Export prmcu_request_ape_opp_100_voltage
clk: Don't return negative numbers for unsigned values with !clk
clk: Fix documentation typos
clk: Document .is_enabled op
clk: SPEAr: Vco-pll: Fix compilation warning
Olof Johansson [Wed, 21 Nov 2012 08:50:07 +0000 (00:50 -0800)]
Merge tag 'bcm2835-for-3.8-defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-rpi into next/soc
From Stephen Warren:
ARM: bcm2835: defconfig updates
procfs and sysfs are enabled in bcm2835_defconfig.
* tag 'bcm2835-for-3.8-defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-rpi:
ARM: bcm2835: enable procfs and sysfs in defconfig
Olof Johansson [Wed, 21 Nov 2012 08:32:18 +0000 (00:32 -0800)]
Merge tag 'tegra-for-3.8-defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/soc
From Stephen Warren:
ARM: tegra: defconfig update
Many new features are enabled in tegra_defconfig:
* BRCMFMAC: wlan driver, enable as module.
* MTD, MTD_CHAR, MTD_M25P80, SPI_TEGRA20_SLINK, CONFIG_SPI_TEGRA20_SFLASH
to enable serial flash on Cardhu and TrimSlice.
* PWM/backlight features for use with tegradrm.
* tegradrm; Tegra's new display driver.
* CMA, so that tegradrm can allocate large buffers.
* SquashFS, which is used as the root filesystem on boards based on
the Tamonten processor module.
* tag 'tegra-for-3.8-defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra:
ARM: tegra: defconfig updates
Olof Johansson [Wed, 21 Nov 2012 08:29:02 +0000 (00:29 -0800)]
Merge tag 'tegra-for-3.8-cpuidle' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/soc
From Stephen Warren:
ARM: tegra: cpuidle enhancements
A cpuidle state "LP2" is added, which power-gates the CPUs. Support for
CPUs 1..n is essentially complete, although support for CPU0 could
benefit from future use of coupled-cpuidle or similar techniques.
A couple of very minor cleanups to cpuidle were included too.
This pull request is based on tegra-for-3.8-soc.
* tag 'tegra-for-3.8-cpuidle' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra:
ARM: tegra: retain L2 content over CPU suspend/resume
ARM: tegra30: cpuidle: add powered-down state for CPU0
ARM: tegra30: flowctrl: add cpu_suspend_exter/exit function
ARM: tegra30: clocks: add CPU low-power function into tegra_cpu_car_ops
ARM: tegra30: common: enable csite clock
ARM: tegra30: cpuidle: add powered-down state for secondary CPUs
ARM: tegra: cpuidle: add CPU resume function
ARM: tegra: cpuidle: separate cpuidle driver for different chips
ARM: tegra: rename the file of "sleep-tXX" to "sleep-tegraXX"
ARM: tegra: cpuidle: replace LP3 with ARM_CPUIDLE_WFI_STATE
Alexander Shiyan [Sat, 17 Nov 2012 13:57:09 +0000 (17:57 +0400)]
ARM: clps711x: Transform clps711x-framebuffer to platform driver and use it
clps711x-framebuffer driver needs to be updated and this is a first step
to make driver better. With this patch we are convert clps711x-framebuffer
to platform device and load this driver from board code.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Olof Johansson <olof@lixom.net>
Stefan Roese [Mon, 19 Nov 2012 11:09:42 +0000 (12:09 +0100)]
ARM: sunxi: Add sun4i and cubieboard support
This patch adds support for the Cubieboard based on the Allwinner
A10/sun4i SoC. Currently only UART is supported. Other devices
will eventually follow.
Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Stefan Roese [Mon, 19 Nov 2012 11:09:40 +0000 (12:09 +0100)]
ARM: sunxi: Restructure sunxi dts/dtsi files
For the new sun4i/Cubieboard (A10) support, lets re-strucure the
sun5i dts files to make it more generic. Those are the new
dts/dtsi files:
sunxi.dtsi - Devices common to all Allwinner sunXi SoC's
sun4i.dtsi - sun4i Devices, will include sunxi.dtsi
sun5i.dtsi - sun5i Devices, will include sunxi.dtsi
board.dts - will include either sun4i.dtsi or sun5i.dtsi
Additionally the "duart" label in the olinuxino.dts is changed to
"uart1".
Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Christian Daudt [Mon, 19 Nov 2012 17:46:10 +0000 (09:46 -0800)]
Add support for generic BCM SoC chipsets
In order to start upstreaming Broadcom SoC support, create
a starting hierarchy, arch and dts files.
The first support SoC family that is planned is the
BCM281XX (BCM11130/11140/11351/28145/28155) family of dual A9 mobile
SoC cores.
This code is just the skeleton code for get the machine upstreamed. It
has been made MULTIPLATFORM compatible.
Next steps
----------
Upstream a basic set of drivers - sufficient for a console boot to
ramdisk. These will includer timer, gpio, i2c drivers.
After this basic set, we will proceed with a more comprehensive set
of drivers for the 281XX SoC family.
v2 patch mods
--------
- Remove l2x0_of_init call as there were problems with the code.
A separate patch will be submitted with cache init code
- Rename capri files and refs to bcm281xx-based names
- Add bcm281xx binding doc
- various misc cleanups
v3 patch mods
-------------
- Remove extra #include lines
- Remove remaining references to capri
- dt uart chipset string added
- cleaned up chip # references
v4 patch mods
-------------
- swap order of compatible definitions for uart
- fix typo
v5 patch mods
-------------
- Rename bcm281xx to bcm11351 in dts+code,
leaving references to bcm281xx only in help+comments.
Olof Johansson [Tue, 20 Nov 2012 06:13:24 +0000 (22:13 -0800)]
Merge tag 'davinci-for-v3.8/soc' of git://gitorious.org/linux-davinci/linux-davinci into next/soc
From Sekhar Nori:
SoC updates for DaVinci. Changes include:
1) Support for PRUSS UIO driver for DA850 SoC
and related SRAM support updates.
2) Prepration for common clock migration
3) Serial support related changes for DA850 DT boot
* tag 'davinci-for-v3.8/soc' of git://gitorious.org/linux-davinci/linux-davinci:
ARM: davinci: da8xx: add DA850 PRUSS support
ARM: davinci: add platform hook to fetch the SRAM pool
ARM: davinci: da850: changed SRAM allocator to shared ram.
ARM: davinci: sram: switch from iotable to ioremapped regions
uio: uio_pruss: replace private SRAM API with genalloc
ARM: davinci: serial: provide API to initialze UART clocks
ARM: davinci: convert platform code to use clk_prepare/clk_unprepare
Tomasz Figa [Tue, 6 Nov 2012 23:44:59 +0000 (08:44 +0900)]
pinctrl: samsung: Add support for EXYNOS4X12
This patch extends the driver with any necessary SoC-specific
definitions to support EXYNOS4X12 SoCs.
Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Shiraz Hashim [Fri, 16 Nov 2012 05:15:25 +0000 (10:45 +0530)]
gpio: SPEAr: add spi chipselect control driver
SPEAr platform provides a provision to control chipselects of ARM PL022
Prime Cell spi controller through its system registers, which otherwise
remains under PL022 control which some protocols do not want.
This commit intends to provide the spi chipselect control in software over
gpiolib interface. spi chip drivers can use the exported gpiolib interface to
define their chipselect through DT or platform data.
Peter Ujfalusi [Tue, 13 Nov 2012 09:35:13 +0000 (10:35 +0100)]
gpio: twl4030: Use only TWL4030_MODULE_LED for LED configuration
Avoid using the TWL4030_MODULE_PWMA/B as module ID. The LEDEN, PWMA ON/OFF
and PWMB ON/OFF registers are in a continuous range starting from LED base.
This is going to be helpful for further cleanup in the twl stack.
No functional changes.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Arnd Bergmann [Fri, 16 Nov 2012 15:59:17 +0000 (16:59 +0100)]
Merge tag 'imx-soc' of git://git.pengutronix.de/git/imx/linux-2.6 into next/soc
From Sascha Hauer <s.hauer@pengutronix.de>:
ARM i.MX SoC updates
based on imx-multiplatform branch.
* tag 'imx-soc' of git://git.pengutronix.de/git/imx/linux-2.6:
ARM i.MX51 babbage: Add display support
ARM i.MX6: Add IPU support
ARM i.MX51: Add IPU support
ARM i.MX53: Add IPU support
ARM i.MX5: switch IPU clk support to devicetree bindings
ARM i.MX6: fix ldb_di_sel mux
ARM i.MX51: setup MIPI during startup
mx2_camera: Fix regression caused by clock conversion
ARM: clk-imx27: Add missing clock for mx2-camera
ARM i.MX27: Fix low reference clock path
ARM: dts: imx27-3ds: Remove local watchdog inclusion
watchdog: Support imx watchdog on SOC_IMX53
ARM: mach-imx: Support for DryIce RTC in i.MX53
ARM : i.MX27 : split code for allocation of ressources of camera and eMMA
Sascha Hauer [Mon, 12 Nov 2012 14:39:01 +0000 (15:39 +0100)]
ARM i.MX51 babbage: Add display support
The babbage board has a DVI-I output which allows to output analog
and digital signals simultaneously. This patch adds support for it
to the devicetree. The DDC signals are not wired up on the board, so
DRM will fall back on default VESA modes.
Sascha Hauer [Tue, 5 Jun 2012 11:53:32 +0000 (13:53 +0200)]
ARM i.MX5: switch IPU clk support to devicetree bindings
The i.MX5 clk support has platform based clock bindings for the
IPU. IPU support is devicetree only, so move them over to devicetree
based bindings. Also, enable MIPI clocks which do not have a device
associated with, but still need to be enabled to do graphics on
i.MX51.
Sascha Hauer [Mon, 12 Nov 2012 14:39:55 +0000 (15:39 +0100)]
ARM i.MX51: setup MIPI during startup
The MIPI interface has to be initialized for proper IPU support.
The MIPI officially is not supported, but still needs initialization.
This patch adds this to the SoC startup as all it does is poking
some magic values into registers for which we do not have documentation.
Fabio Estevam [Tue, 30 Oct 2012 12:03:26 +0000 (10:03 -0200)]
mx2_camera: Fix regression caused by clock conversion
Since mx27 transitioned to the commmon clock framework in 3.5, the correct way
to acquire the csi clock is to get csi_ahb and csi_per clocks separately.
By not doing so the camera sensor does not probe correctly:
soc-camera-pdrv soc-camera-pdrv.0: Probing soc-camera-pdrv.0
mx2-camera mx2-camera.0: Camera driver attached to camera 0
ov2640 0-0030: Product ID error fb:fb
mx2-camera mx2-camera.0: Camera driver detached from camera 0
mx2-camera mx2-camera.0: MX2 Camera (CSI) driver probed, clock frequency: 66500000
Adapt the mx2_camera driver to the new clock framework and make it functional
again.
Sascha Hauer [Wed, 31 Oct 2012 07:25:08 +0000 (08:25 +0100)]
ARM i.MX27: Fix low reference clock path
The i.MX27 clock tree can either be driven from a 26MHz oscillator
or from a 32768Hz oscillator. The latter was not properly implemented,
the mux between these two pathes was missing. Add this mux and while
at it rename the 'prem' (premultiplier) clk to 'fpm' (Frequency
Pre-Multiplier) to better match the datasheet.
Roland Stigge [Thu, 18 Oct 2012 16:06:10 +0000 (18:06 +0200)]
ARM: mach-imx: Support for DryIce RTC in i.MX53
This patch enables support for i.MX53 in addition to i.MX25 by providing a
dummy clock on i.MX53 since this one doesn't have a separate clock for internal
RTC but the driver requests one.
Signed-off-by: Roland Stigge <stigge@antcom.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
ARM : i.MX27 : split code for allocation of ressources of camera and eMMA
This is to prepare addition of m2m-emmapp driver otherwise
IMX_HAVE_PLATFORM_MX2_CAMERA must be declared even if only Post-Processor is
needed.
IMX_HAVE_PLATFORM_MX2_EMMA define has been added.
Changes since v1:
- Add "select IMX_HAVE_PLATFORM_MX2_EMMA" for MACH_IMX27_VISSTRIM_M10 platform
due to pending patch in linux-media tree that will call
imx27_add_mx2_emmaprp().
Signed-off-by: Gaëtan Carlier <gcembed@gmail.com> Acked-by: Javier Martin <javier.martin@vista-silicon.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Stephen Warren [Fri, 21 Sep 2012 08:55:00 +0000 (16:55 +0800)]
ARM: tegra: defconfig updates
New options enabled:
* BRCMFMAC: wlan driver, enable as module.
* MTD, MTD_CHAR, MTD_M25P80, SPI_TEGRA20_SLINK, CONFIG_SPI_TEGRA20_SFLASH
to enable serial flash on Cardhu and TrimSlice.
* PWM/backlight features for use with tegradrm.
* tegradrm; Tegra's new display driver.
* CMA, so that tegradrm can allocate large buffers.
* SquashFS, which is used as the root filesystem on boards based on
the Tamonten processor module.
Signed-off-by: Wei Ni <wni@nvidia.com> Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Stephen Warren <swarren@nvidia.com>
Joseph Lo [Tue, 13 Nov 2012 02:04:48 +0000 (10:04 +0800)]
ARM: tegra: retain L2 content over CPU suspend/resume
The L2 RAM is in different power domain from the CPU cluster. So the
L2 content can be retained over CPU suspend/resume. To do that, we
need to disable L2 after the MMU is disabled, and enable L2 before
the MMU is enabled. But the L2 controller is in the same power domain
with the CPU cluster. We need to restore it's settings and re-enable
it after the power be resumed.
Signed-off-by: Joseph Lo <josephl@nvidia.com> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
Joseph Lo [Wed, 31 Oct 2012 09:41:21 +0000 (17:41 +0800)]
ARM: tegra30: cpuidle: add powered-down state for CPU0
This is a power gating idle mode. It support power gating vdd_cpu rail
after all cpu cores in "powered-down" status. For Tegra30, the CPU0 can
enter this state only when all secondary CPU is offline. We need to take
care and make sure whole secondary CPUs were offline and checking the
CPU power gate status. After that, the CPU0 can go into "powered-down"
state safely. Then shut off the CPU rail.
Be aware of that, you may see the legacy power state "LP2" in the code
which is exactly the same meaning of "CPU power down".
Base on the work by:
Scott Williams <scwilliams@nvidia.com>
Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
Joseph Lo [Wed, 31 Oct 2012 09:41:20 +0000 (17:41 +0800)]
ARM: tegra30: flowctrl: add cpu_suspend_exter/exit function
The flow controller can help CPU to go into suspend mode (powered-down
state). When CPU go into powered-down state, it needs some careful
settings before getting into and after leaving. The enter and exit
functions do that by configuring appropriate mode for flow controller.
Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
Joseph Lo [Wed, 31 Oct 2012 09:41:19 +0000 (17:41 +0800)]
ARM: tegra30: clocks: add CPU low-power function into tegra_cpu_car_ops
Add suspend, resume and rail_off_ready API into tegra_cpu_car_ops. These
functions were used for CPU powered-down state maintenance. One thing
needs to notice the rail_off_ready API only availalbe for cpu_g cluster
not cpu_lp cluster.
Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
Joseph Lo [Wed, 31 Oct 2012 09:41:18 +0000 (17:41 +0800)]
ARM: tegra30: common: enable csite clock
Enable csite (debug and trace controller) clock at init to prevent it
be disabled. And this also the necessary clock for CPU be brought up or
resumed from a power-gating low power state.
Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
Joseph Lo [Wed, 31 Oct 2012 09:41:17 +0000 (17:41 +0800)]
ARM: tegra30: cpuidle: add powered-down state for secondary CPUs
This supports power-gated idle on secondary CPUs for Tegra30. The
secondary CPUs can go into powered-down state independently. When
CPU goes into this state, it saves it's contexts and puts itself
to flow controlled WFI state. After that, it will been power gated.
Be aware of that, you may see the legacy power state "LP2" in the
code which is exactly the same meaning of "CPU power down".
Based on the work by:
Scott Williams <scwilliams@nvidia.com>
Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
Joseph Lo [Wed, 31 Oct 2012 09:41:16 +0000 (17:41 +0800)]
ARM: tegra: cpuidle: add CPU resume function
The CPU suspending on Tegra means CPU power gating. We add a resume
function for taking care the CPUs that resume from power gating status.
This function was been hooked to the reset handler. We take care
everything here before go into kernel.
Be aware of that, you may see the legacy power status "LP2" in the code
which is exactly the same meaning of "CPU power down".
Based on the work by:
Scott Williams <scwilliams@nvidia.com>
Colin Cross <ccross@android.com>
Gary King <gking@nvidia.com>
Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
Thierry Reding [Thu, 15 Nov 2012 21:07:58 +0000 (22:07 +0100)]
ARM: tegra: Add AUXDATA for Tegra30 host1x
Add the OF_DEV_AUXDATA table entries required to associate the proper
names with host1x and its children. In turn, this allows the devices to
find the required clocks.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Stephen Warren <swarren@nvidia.com>
Thierry Reding [Thu, 15 Nov 2012 21:07:56 +0000 (22:07 +0100)]
ARM: tegra: Add Tegra20 host1x clock support
Extend the pll_d frequency table with a few entries to support common
HDMI and LVDS display modes and setup the clock parents for the two
display controllers and HDMI.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Stephen Warren <swarren@nvidia.com>
projects / linux-beck.git / log