Paul Burton [Fri, 11 Jul 2014 15:44:35 +0000 (16:44 +0100)]
MIPS: disable preemption whilst initialising MSA
Preemption must be disabled throughout the process of enabling the FPU,
enabling MSA & initialising the vector registers. Without doing so it
is possible to lose the FPU or MSA whilst initialising them causing
that initialisation to fail.
Paul Burton [Fri, 11 Jul 2014 15:44:34 +0000 (16:44 +0100)]
MIPS: ensure MSA gets disabled during boot
The kernel relies upon MSA being disabled when a task begins running,
so that it can initialise or restore context in response to the
resulting MSA disabled exception. Previously the state of MSA following
boot was left as it was before the kernel ran, where MSA could
potentially have been enabled. Explicitly disable it during boot to
prevent any problems.
As a nice side effect the code reads a little better too.
Paul Burton [Fri, 11 Jul 2014 15:44:33 +0000 (16:44 +0100)]
MIPS: fix read_msa_* & write_msa_* functions on non-MSA toolchains
Commit d96cc3d1ec5d "MIPS: Add microMIPS MSA support." attempted to use
the value of a macro within an inline asm statement but instead emitted
a comment leading to the cfcmsa & ctcmsa instructions being omitted. Fix
that by passing CFC_MSA_INSN & CTC_MSA_INSN as arguments to the asm
statements.
Paul Burton [Thu, 31 Jul 2014 13:53:16 +0000 (14:53 +0100)]
MIPS: fix MSA context for tasks which don't use FP first
If a task does not execute scalar FP instructions prior to using MSA
then the flags indicating that the task has live MSA context were not
being set. The upper 64b of each vector register would then be lost
upon the tasks first context switch after using MSA.
Paul Burton [Wed, 30 Jul 2014 07:53:20 +0000 (08:53 +0100)]
MIPS: init upper 64b of vector registers when MSA is first used
When a task first makes use of MSA we need to ensure that the upper
64b of the vector registers are set to some value such that no
information can be leaked to it from the previous task to use MSA
context on the CPU. The architecture formerly specified that these
bits would be cleared to 0 when a scalar FP instructions wrote to the
aliased FP registers, which would have implicitly handled this as the
kernel restored scalar FP context. However more recent versions of the
specification now state that the value of the bits in such cases is
unpredictable. Initialise them explictly to be sure, and set all the
bits to 1 rather than 0 for consistency with the least significant
64b.
Paul Burton [Fri, 11 Jul 2014 15:44:30 +0000 (16:44 +0100)]
MIPS: save/disable MSA in lose_fpu
The kernel depends upon MSA never being enabled when the FPU is not, a
condition which is currently violated in a few places (whilst saving
sigcontext, following mips_cpu_save). Catch all the problem cases by
disabling MSA in lose_fpu, after saving context if necessary.
Paul Burton [Fri, 11 Jul 2014 15:44:29 +0000 (16:44 +0100)]
MIPS: preserve scalar FP CSR when switching vector context
Switching the vector context implicitly saves & restores the state of
the aliased scalar FP data registers, however the scalar FP control
& status register is distinct from the MSA control & status register.
In order to allow scalar FP to function correctly in programs using
MSA, the scalar CSR needs to be saved & restored along with the MSA
vector context.
Paul Burton [Fri, 11 Jul 2014 15:44:28 +0000 (16:44 +0100)]
MIPS: save/restore MSACSR register on context switch
I added a field for the MSACSR register in struct mips_fpu_struct, but
never actually made use of it... This is a clear bug. Save and restore
the MSACSR register along with the vector registers.
Aaro Koskinen [Sat, 28 Jun 2014 20:34:08 +0000 (23:34 +0300)]
MIPS: OCTEON: cvmx-bootinfo: add D-Link DSR-1000N
Add a definition for D-Link DSR-1000N router. The bootloader on this board
supplies 20006 in the bootinfo; the enum CVMX_BOARD_TYPE_CUST_DSR1000N
comes from the GPL sources of the board.
Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: David Daney <ddaney.cavm@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/7217/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Aaro Koskinen [Fri, 27 Jun 2014 21:59:50 +0000 (00:59 +0300)]
MIPS: OCTEON: watchdog: don't jump to bootloader without entry address
If CONFIG_HOTPLUG_CPU is set, the driver thinks bootloader entry
address is configured and we should jump there. However, this is
not necessarily true if the kernel is booted on a system
with older/incompatible bootloader.
Add dynamic checks for the bootloader entry address.
Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi> Cc: linux-watchdog@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: David Daney <ddaney.cavm@gmail.com> Cc: linux-watchdog@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/7201/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Florian Fainelli [Wed, 25 Jun 2014 23:41:13 +0000 (16:41 -0700)]
MIPS: Document the cca= command-line parameter
Commit 351336929ccf222ae38ff0cb7a8dd5fd5c6236a0 ("[MIPS] Allow setting
of the cache attribute at run time") introduced the 'cca=' kernel
command-line parameter which allows overriding the kernel pages
cacheable attributes, document that parameter.
[ralf@linux-mips.org: replace @mips.com email addresses with it's imgtec.com
equivalent in this commit message. Rephrase slightly for a bit more
pedantic correctness.]
The Malta malta_ipi_irqdispatch() routine now checks only IPI interrupts
when handling IPIs. It could previously call do_IRQ() for non-IPIs, and
also call do_IRQ() with an invalid IRQ number if there were no pending
GIC interrupts when gic_get_int() was called.
MIPS: GIC: Generalise check for pending interrupts
Move most of the functionality of gic_get_int() into a new function
gic_get_int_mask() which takes a bitmask of interrupts in which the
caller is interested, and returns the subset which are pending for the
current CPU.
This allows CP0 IRQ dispatch routines to check only the GIC interrupts
which are routed to a particular CPU interrupt input.
gic_get_int() is reimplemented using gic_get_int_mask() and is retained
for use by any platforms for which gic_get_int() is sufficient.
A GIC interrupt which is declared as having a GIC_MAP_TO_NMI_MSK
mapping causes the cpu parameter to gic_setup_intr() to be increased
to 32, causing memory corruption when pcpu_masks[] is written to again
later in the function.
irq-gic.c:gic_get_int() masks out interrupts from the pending set which
aren’t in the pcpu_mask. Only interrupts marked with GIC_FLAG_IPI were
set in pcpu_mask, meaning that peripheral interrupts also had to be
marked as IPIs. Remove the use of GIC_FLAG_IPI and allow the flags
member of struct gic_intr_map to be zero.
The value of GIC_NUM_INTRS is platform-specific. Using a default value
from gic.h will result in incorrect behaviour on some systems, so
require a suitable definition to be present in the platform's irq.h.
Several bitmaps are declared in arch/mips/include/asm/gic.h, but the
scope of their use is limited to arch/mips/kernel/irq-gic.c. Move the
declarations from the header file to the C file.
Detect if the core supports unique exception codes for the
Read-Inhibit and Execute-Inhibit exceptions and set the
option accordingly. The RI/XI exception support is detected
by setting the 27th bit (IEC) of the PageGrain C0 register
and reading back the value of that register to verify the
bit is enabled.
Leonid Yegoshin [Tue, 15 Jul 2014 13:09:56 +0000 (14:09 +0100)]
MIPS: Use dedicated exception handler if CPU supports RI/XI exceptions
Use the regular tlb_do_page_fault_0 (no write) handler to handle
the RI and XI exceptions. Also skip the RI/XI validation check
on TLB load handler since it's redundant when the CPU has
unique RI/XI exceptions.
MIPS: mm: Use the Hardware Page Table Walker if the core supports it
The Hardware Page Table Walker aims to speed up TLB refill exceptions
by handling them in the hardware level instead of having a software
TLB refill handler. However, a TLB refill exception can still be
thrown in certain cases such as, synchronus exceptions, or address
translation or memory errors during the HTW operation. As a result of
which, HTW must not be considered a complete replacement for the TLB
refill software handler, but rather a fast-path for it.
For HTW to work, the PWBase register must contain the task's page
global directory address so the HTW will kick in on TLB refill
exceptions.
Due to HTW being a separate engine embedded deep in the CPU pipeline,
we need to restart the HTW everytime a PTE changes to avoid HTW
fetching a old entry from the page tables. It's also necessary to
restart the HTW on context switches to prevent it from fetching a
page from the previous process. Finally, since HTW is using the
entryhi register to write the translations to the TLB, it's necessary
to stop the HTW whenever the entryhi changes (eg for tlb probe
perations) and enable it back afterwards.
== Performance ==
The following trivial test was used to measure the performance of the
HTW. Using the same root filesystem, the following command was used
to measure the number of tlb refill handler executions with and
without (using 'nohtw' kernel parameter) HTW support. The kernel was
modified to use a scratch register as a counter for the TLB refill
exceptions.
MIPS: kernel: cpu-probe: Add support for the HardWare Table Walker
Detect if the core implements the HTW and set the option accordingly.
Also, add a new kernel parameter called 'nohtw' allowing
the user to disable the htw support and fallback to the software
refill handler.
MIPS: cpu-info: Change the cpu options variable to unsigned long long
Long integers which are 4 bytes in MIPS32 can't hold new CPU
options anymore, so the type of the 'options' variable is changed
to unsigned long long which allows 32 more cpu options to be defined
for MIPS32
Also, re-arrange the 'options' struct member to avoid potential 4-byte
alignment gap in the middle of the struct.
James Hogan [Fri, 4 Jul 2014 10:08:57 +0000 (11:08 +0100)]
MIPS: perf: Add hardware events for P5600
Add cases in perf_event_mipsxx.c for CPU_P5600. All the event numbers
listed for proAptiv also apply to P5600, so we use mipsxxcore_event_map2
and mipsxxcore_cache_map2 too, but the P5600 has 8-bit event numbers so
bit 8 (256) of the user ABI config is used for the parity bit (to
specify odd/even counter events).
James Hogan [Fri, 4 Jul 2014 10:08:56 +0000 (11:08 +0100)]
MIPS: perf: Allow for more perf events
In mipsxx_pmu_map_raw_event(), set event_id to base_id after the cpu
type conditional code to allow that code to override the base_id to use
more bits from the config and a higher bit for parity.
This will allow cores with up to 512 events between all even/odd
counters (an 8-bit event id) such as P5600 to use bit 8 for parity.
Alex Smith [Wed, 23 Jul 2014 13:40:16 +0000 (14:40 +0100)]
MIPS: asm/reg.h: Move to uapi
This header defines an exported interface (the register layout used in
core dumps and the GP regset accessible with PTRACE_{GET,SET}REGSET),
therefore belongs in uapi.
Signed-off-by: Alex Smith <alex@alex-smith.me.uk> Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/7458/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Alex Smith [Wed, 23 Jul 2014 13:40:15 +0000 (14:40 +0100)]
MIPS: Remove asm/user.h
The struct user definition in this file is not used anywhere (the ELF
core dumper does not use that format). Therefore, remove the header and
instead enable the asm-generic user.h which is an empty header to
satisfy a few generic headers which still try to include user.h.
Signed-off-by: Alex Smith <alex@alex-smith.me.uk> Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/7459/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Alex Smith [Wed, 23 Jul 2014 13:40:13 +0000 (14:40 +0100)]
MIPS: ptrace: Fix user pt_regs definition, use in ptrace_{get, set}regs()
In uapi/asm/ptrace.h, a user version of pt_regs is defined wrapped in
ifndef __KERNEL__. This structure definition does not match anything
used by any kernel API, in particular it does not match the format used
by PTRACE_{GET,SET}REGS.
Therefore, replace the structure definition with one matching what is
used by PTRACE_{GET,SET}REGS. The format used by these is the same for
both 32-bit and 64-bit.
Also, change the implementation of PTRACE_{GET,SET}REGS to use this new
structure definition. The structure is renamed to user_pt_regs when
__KERNEL__ is defined to avoid conflicts with the kernel's own pt_regs.
Signed-off-by: Alex Smith <alex@alex-smith.me.uk> Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/7457/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Alex Smith [Wed, 23 Jul 2014 13:40:11 +0000 (14:40 +0100)]
MIPS: O32/32-bit: Fix bug which can cause incorrect system call restarts
On 32-bit/O32, pt_regs has a padding area at the beginning into which the
syscall arguments passed via the user stack are copied. 4 arguments
totalling 16 bytes are copied to offset 16 bytes into this area, however
the area is only 24 bytes long. This means the last 2 arguments overwrite
pt_regs->regs[{0,1}].
If a syscall function returns an error, handle_sys stores the original
syscall number in pt_regs->regs[0] for syscall restart. signal.c checks
whether regs[0] is non-zero, if it is it will check whether the syscall
return value is one of the ERESTART* codes to see if it must be
restarted.
Should a syscall be made that results in a non-zero value being copied
off the user stack into regs[0], and then returns a positive (non-error)
value that matches one of the ERESTART* error codes, this can be mistaken
for requiring a syscall restart.
While the possibility for this to occur has always existed, it is made
much more likely to occur by commit 46e12c07b3b9 ("MIPS: O32 / 32-bit:
Always copy 4 stack arguments."), since now every syscall will copy 4
arguments and overwrite regs[0], rather than just those with 7 or 8
arguments.
Since that commit, booting Debian under a 32-bit MIPS kernel almost
always results in a hang early in boot, due to a wait4 syscall returning
a PID that matches one of the ERESTART* codes, which then causes an
incorrect restart of the syscall.
The problem is fixed by increasing the size of the padding area so that
arguments copied off the stack will not overwrite pt_regs->regs[{0,1}].
Alex Smith [Wed, 23 Jul 2014 13:40:09 +0000 (14:40 +0100)]
MIPS: ptrace: Change GP regset to use correct core dump register layout
Commit 6a9c001b7ec3 ("MIPS: Switch ELF core dumper to use regsets.")
switched the core dumper to use regsets, however the GP regset code
simply makes a direct copy of the kernel's pt_regs, which does not
match the original core dump register layout as defined in asm/reg.h.
Furthermore, the definition of pt_regs can vary with certain Kconfig
variables, therefore the GP regset can never be relied upon to return
registers in the same layout.
Therefore, this patch changes the GP regset to match the original core
dump layout. The layout differs for 32- and 64-bit processes, so
separate implementations of the get/set functions are added for the
32- and 64-bit regsets.
Signed-off-by: Alex Smith <alex@alex-smith.me.uk> Cc: <stable@vger.kernel.org> # v3.13+ Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/7452/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Alex Smith [Wed, 23 Jul 2014 13:40:08 +0000 (14:40 +0100)]
MIPS: asm/reg.h: Make 32- and 64-bit definitions available at the same time
Get rid of the WANT_COMPAT_REG_H test and instead define both the 32-
and 64-bit register offset definitions at the same time with
MIPS{32,64}_ prefixes, then define the existing EF_* names to the
correct definitions for the kernel's bitness.
This patch is a prerequisite of the following bug fix patch.
Signed-off-by: Alex Smith <alex@alex-smith.me.uk> Cc: <stable@vger.kernel.org> # v3.13+ Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/7451/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Alex Smith [Wed, 23 Jul 2014 13:40:06 +0000 (14:40 +0100)]
MIPS: ptrace: Avoid smp_processor_id() when retrieving FPU IR
Whenever ptrace attempts to retrieve the FPU implementation register it
accesses it through current_cpu_data, which calls smp_processor_id().
Since the code may execute with preemption enabled, this can trigger
a warning. Fix this by using boot_cpu_data to get the IR instead.
Signed-off-by: Alex Smith <alex@alex-smith.me.uk> Cc: <stable@vger.kernel.org> # v3.15+ Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/7449/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Function add_temporary_entry is needed by bcm47xx to support highmem. We
need to add a temporary entry to check for amount of RAM.
The only change made in this revert was replacing (ENTER|EXIT)_CRITICAL.
Rafał Miłecki [Tue, 17 Jun 2014 14:36:51 +0000 (16:36 +0200)]
MIPS: BCM47XX: Select SYS_SUPPORTS_HIGHMEM for BCM47XX_BCMA
It seems that bcm47xx can handle only 128 MiB of RAM directly. There
are few devices with 256 MiB, but Broadcom's SDK uses highmem to handle
anything above 128 MiB.
Huacai Chen [Thu, 26 Jun 2014 03:41:32 +0000 (11:41 +0800)]
MIPS: Loongson: Rename CONFIG_LEMOTE_MACH3A to CONFIG_LOONGSON_MACH3X
Since this CONFIG option will be used for both Loongson-3A/3B machines,
and not all Loongson-3 machines are produced by Lemote, we rename
CONFIG_LEMOTE_MACH3A to CONFIG_LOONGSON_MACH3X.
Signed-off-by: Huacai Chen <chenhc@lemote.com> Cc: John Crispin <john@phrozen.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/7190/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Huacai Chen [Thu, 26 Jun 2014 03:41:31 +0000 (11:41 +0800)]
MIPS: Loongson-3: Enable the COP2 usage
Loongson-3 has some specific instructions (MMI/SIMD) in coprocessor 2.
COP2 isn't independent because it share COP1 (FPU)'s registers. This
patch enable the COP2 usage so user-space programs can use the MMI/SIMD
instructions. When COP2 exception happens, we enable both COP1 (FPU)
and COP2, only in this way the fp context can be saved and restored
correctly.
Signed-off-by: Huacai Chen <chenhc@lemote.com> Cc: John Crispin <john@phrozen.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/7189/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Huacai Chen [Thu, 26 Jun 2014 03:41:30 +0000 (11:41 +0800)]
MIPS: Add Loongson-3B support
Loongson-3B is a 8-cores processor. In general it looks like there are
two Loongson-3A integrated in one chip: 8 cores are separated into two
groups (two NUMA node), each node has its own local memory.
Of course there are some differences between one Loongson-3B and two
Loongson-3A. E.g., the base addresses of IPI registers of each node are
not the same; Loongson-3A use ChipConfig register to enable/disable
clock, but Loongson-3B use FreqControl register instead.
There are two revision of Loongson-3B, the first revision is called as
Loongson-3B1000, whose frequency is 1GHz and has a PRid 0x6306, the
second revision is called as Loongson-3B1500, whose frequency is 1.5GHz
and has a PRid 0x6307. Both revisions has a bug that clock cannot be
disabled at runtime, but this will be fixed in future.
Signed-off-by: Huacai Chen <chenhc@lemote.com> Cc: John Crispin <john@phrozen.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/7188/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Huacai Chen [Thu, 26 Jun 2014 03:41:29 +0000 (11:41 +0800)]
MIPS: Add numa api support
Enable sys_mbind()/sys_get_mempolicy()/sys_set_mempolicy() for O32, N32,
and N64 ABIs. By the way, O32/N32 should use the compat version of
sys_migrate_pages()/sys_move_pages(), so fix that.
Signed-off-by: Huacai Chen <chenhc@lemote.com> Cc: John Crispin <john@phrozen.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/7186/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Huacai Chen [Thu, 26 Jun 2014 03:41:28 +0000 (11:41 +0800)]
MIPS: Add NUMA support for Loongson-3
Multiple Loongson-3A chips can be interconnected with HT0-bus. This is
a CC-NUMA system that every chip (node) has its own local memory and
cache coherency is maintained by hardware. The 64-bit physical memory
address format is as follows:
0x-0000-YZZZ-ZZZZ-ZZZZ
The high 16 bits should be 0, which means the real physical address
supported by Loongson-3 is 48-bit. The "Y" bits is the base address of
each node, which can be also considered as the node-id. The "Z" bits is
the address offset within a node, which means every node has a 44 bits
address space.
Macros XPHYSADDR and MAX_PHYSMEM_BITS are modified unconditionally,
because many other MIPS CPUs have also extended their address spaces.
Signed-off-by: Huacai Chen <chenhc@lemote.com> Cc: John Crispin <john@phrozen.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/7187/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Huacai Chen [Thu, 26 Jun 2014 03:41:26 +0000 (11:41 +0800)]
MIPS: Support CPU topology files in sysfs
This patch is prepared for Loongson's NUMA support, it offer meaningful
sysfs files such as physical_package_id, core_id, core_siblings and
thread_siblings in /sys/devices/system/cpu/cpu?/topology.
Signed-off-by: Huacai Chen <chenhc@lemote.com> Reviewed-by: Andreas Herrmann <andreas.herrmann@caviumnetworks.com> Cc: John Crispin <john@phrozen.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/7184/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Huacai Chen [Thu, 26 Jun 2014 03:41:25 +0000 (11:41 +0800)]
MIPS: Support hard limit of cpu count (nr_cpu_ids)
On MIPS currently, only the soft limit of cpu count (maxcpus) has its
effect, this patch enable the hard limit (nr_cpus) as well. Processor
cores which greater than maxcpus and less than nr_cpus can be taken up
via cpu hotplug. The code is borrowed from X86.
Signed-off-by: Huacai Chen <chenhc@lemote.com> Reviewed-by: Andreas Herrmann <andreas.herrmann@caviumnetworks.com> Cc: John Crispin <john@phrozen.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/7183/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Emil Goode [Sat, 5 Jul 2014 23:23:58 +0000 (01:23 +0200)]
MIPS: Remove incorrect NULL check in local_flush_tlb_page()
We check that the struct vm_area_struct pointer vma is NULL and then
dereference it a few lines below. The intent was to make sure vma is
not NULL but this is not necessary since the bug pre-dates GIT history
and seem to never have caused a problem. The tlb-4k and tlb-8k versions
of local_flush_tlb_page() don't bother checking if vma is NULL, also
vma is dereferenced before being passed to local_flush_tlb_page(),
thus it is safe to remove this NULL check.
Signed-off-by: Emil Goode <emilgoode@gmail.com> Reviewed-by: Jonas Gorski <jogo@openwrt.org> Acked-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: Paul Gortmaker <paul.gortmaker@windriver.com> Cc: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: kernel-janitors@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/7264/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Paul Burton [Wed, 9 Jul 2014 11:51:05 +0000 (12:51 +0100)]
MIPS: smp-cps: Fix entry code cache flush for systems with coherent I/O
The dma_cache_wback_inv function performs exactly as is required here,
unless the system has coherent I/O in which case it's a no-op. Call the
underlying cache writeback functions directly, which is arguably clearer
anyway given that the code doesn't actually have anything to do with
DMA in a strict sense.
Paul Burton [Wed, 9 Jul 2014 11:48:21 +0000 (12:48 +0100)]
MIPS: {pm,smp}-cps: use cpu_vpe_id macro
When determining the VPE ID of a CPU, make use of the cpu_vpe_id macro
which will return 0 in a non-MT kernel build. Most code is already doing
so but a couple of places weren't. Fixing this prevents a build failure
for non-MT kernels where struct cpuinfo_mips does not contain the vpe_id
field:
arch/mips/kernel/pm-cps.c: In function 'cps_pm_enter_state':
arch/mips/kernel/pm-cps.c:153:51: error: 'struct cpuinfo_mips' has no
member named 'vpe_id'
vpe_cfg = &core_cfg->vpe_config[current_cpu_data.vpe_id];
arch/mips/kernel/smp-cps.c: In function 'wait_for_sibling_halt':
arch/mips/kernel/smp-cps.c:363:33: error: 'struct cpuinfo_mips' has no
member named 'vpe_id'
unsigned vpe_id = cpu_data[cpu].vpe_id;
Paul Burton [Wed, 9 Jul 2014 11:48:20 +0000 (12:48 +0100)]
MIPS: Fix potential build failures using cpu_vpe_id on non-MT
When used in a non-MT kernel, the cpu_vpe_id macro never made use of
its cpuinfo argument. It doesn't actually need to since it is returning
a constant 0. However not using the argument can lead to build failures
if the compiler then notices that a variable used as part of the
argument is unused. Prevent that problem by "using" the argument as far
as the compiler is concerned, whilst still returning 0 as before.
Paul Burton [Wed, 9 Jul 2014 11:48:19 +0000 (12:48 +0100)]
MIPS: pm-cps: Select CONFIG_MIPS_CPC
The pm-cps code can run without a CPC, although will be limited to using
only the 2 wait idle states. However the code does check for CPC
presence, and in order to work optimally the CPC support is needed. So
select it.
Paul Burton [Wed, 9 Jul 2014 11:48:18 +0000 (12:48 +0100)]
MIPS: pm-cps: Prevent use of mips_cps_* without CPS SMP
These symbols will not be defined when CONFIG_MIPS_CPS=n, but although
the CPS_PM_POWER_GATED state will never be used in that case the
compiler doesn't have enough information to figure that out. Add checks
which evaluate to a constant false for CONFIG_MIPS_CPS=n cases in order
to help the compiler out & eliminate the symbol references.
MIPS: BCM47XX: fixup broken MAC addresses in nvram
The address prefix 00:90:4C is used by Broadcom in their initial
configuration. When a mac address with the prefix 00:90:4C is used all
devices from the same series are sharing the same mac address. To
prevent mac address collisions we replace them with a mac address based
on the base address. To generate such addresses we take the main mac
address from et0macaddr and increase it by two for the first wifi
device and by 3 for the second one. This matches the printed mac
address on the device. The main mac address increased by one is used as
wan address by the vendor code.
The reboot on the BCM47XX SoCs is done, by setting the watchdog counter
to 1 and let it trigger a reboot, when it reaches 0. Some devices with
a BCM4705/BCM4785 SoC do not reboot when the counter is set to 1 and
decreased to 0 by the hardware. It looks like it works more reliable
when we set it to 3. As far as I understand the hardware, this should
not make any difference, but I do not have access to any documentation
for this SoC.
It is still not 100% reliable.
Atsushi Nemoto [Sat, 28 Jun 2014 14:56:57 +0000 (23:56 +0900)]
MIPS: TXx9: Add __init_refok annotation to quirk_slc90e66_bridge
This pci fixup routine calls __init functions.
In general pci fixup routine must not call __init functions,
but this pci/isa bridge device is not hotpluggable anyway.
MIPS: SB1: Check optional compilation flags one by one
This fixes a regression caused by commit bb6c0bd3fdb67c8a1fceea1d4700b9ee593309f9 [MIPS: SB1: Fix excessive kernel
warnings.], that makes `-march=r5000' selected for compilation flags
rather than supposed `-march=sb1' with compilers that do not support the
ASE selection flags introduced with that change.
For example GCC 4.1.2 supports `-mips3d'/`-mno-mips3d' (and obviously
`-march=sb1'), however it does not support `-mdmx'/`-mno-mdmx'. As a
result the whole selection of flags fails and compilation resorts to using
`-march=r5000', meant for really old compilers indeed only.
It is always best to pick the flags individually unless we are absolutely
sure a set of flags was introduced to the toolchain together (`-march=sb1'
and `-mtune=sb1' would be a good example), and this change makes it happen
for CONFIG_CPU_SB1. Consequently the flags ultimately selected with GCC
4.1.2 are `-march=sb1 -Wa,--trap -mno-mips3d'
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: Richard Sandiford <rdsandiford@googlemail.com> Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/7223/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
{standard input}: Assembler messages:
{standard input}:145: Error: opcode not supported on this processor: vr5000 (mips4) `clz $2,$2'
{standard input}:920: Error: opcode not supported on this processor: vr5000 (mips4) `clz $7,$9'
{standard input}:1797: Error: opcode not supported on this processor: vr5000 (mips4) `clz $7,$7'
{standard input}:1851: Error: opcode not supported on this processor: vr5000 (mips4) `clz $7,$7'
{standard input}:2831: Error: opcode not supported on this processor: vr5000 (mips4) `clz $7,$7'
{standard input}:4209: Error: opcode not supported on this processor: vr5000 (mips4) `clz $7,$7'
{standard input}:4329: Error: opcode not supported on this processor: vr5000 (mips4) `clz $2,$2'
make[2]: *** [arch/mips/mm/tlbex.o] Error 1
which triggered due to a regression causing the file to be built with
`-march=r5000' rather than `-march=sb1', fixed separately. Nevertheless
the error should not happen, the other uses of CLZ are appropriately
guarded. This change copies the arrangement from one of those other
places.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/7222/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Code in a switch statement in probe_pcache checks the CPU type twice
unnecessarily for processor implementations that have the alias removal
feature reported by the CP0 Config7.AR and Config7.IAR bits. This change
rewrites the affected fragment avoiding the extraneous check and improving
readability.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/7221/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Jonas Gorski [Sat, 12 Jul 2014 10:49:35 +0000 (12:49 +0200)]
MIPS: BCM63xx: Replace irq dispatch code with a generic version
The generic version uses a variable length of u32 registers instead of u32/u64.
This allows easier support for "wider" registers without having to rewrite
everything.
This "generic" version is as fast as the old version in the best case
(i == next set bit), and twice as fast in the worst case in 64 bits.
Using a macro was chosen over a (forced) inline version because gcc generated
more compact code with the macro.
The change from (signed) int to unsigned int for i and to_call was intentional
as the value can be only between 0 and (width - 1) anyway, and allowed gcc to
optimise the code a bit further.
Signed-off-by: Jonas Gorski <jogo@openwrt.org> Cc: linux-mips@linux-mips.org Cc: John Crispin <blogic@openwrt.org> Cc: Maxime Bizon <mbizon@freebox.fr> Cc: Florian Fainelli <florian@openwrt.org> Cc: Kevin Cernekee <cernekee@gmail.com> Cc: Gregory Fong <gregory.0xf0@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/7316/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Jonas Gorski [Tue, 8 Jul 2014 14:26:13 +0000 (16:26 +0200)]
MIPS: BCM63xx: Sync MIPS counters during CPU bringup
We are using the mips counters as the clock source, so we need to ensure
they are synced, else e.g. gettimeofday will return different values
depending on which core it was run.
Observed difference was about 8 seconds, causing ~8 seconds ping or time
running backwards for some programs.
Signed-off-by: Jonas Gorski <jogo@openwrt.org> Cc: linux-mips@linux-mips.org Cc: John Crispin <blogic@openwrt.org> Cc: Maxime Bizon <mbizon@freebox.fr> Cc: Florian Fainelli <florian@openwrt.org> Cc: Kevin Cernekee <cernekee@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/7265/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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