Nimrod Andy [Thu, 11 Dec 2014 01:20:31 +0000 (09:20 +0800)]
net: fec: reset fep link status in suspend function
On some i.MX6 serial boards, phy power and refrence clock are supplied
or controlled by SOC. When do suspend/resume test, the power and clock
are disabled, so phy device link down.
For current driver, fep->link is still up status, which cause extra operation
like below code. To avoid the dumy operation, we set fep->link to down when
phy device is real down.
...
if (fep->link) {
napi_disable(&fep->napi);
netif_tx_lock_bh(ndev);
fec_stop(ndev);
netif_tx_unlock_bh(ndev);
napi_enable(&fep->napi);
fep->link = phy_dev->link;
status_change = 1;
}
...
Signed-off-by: Fugang Duan <B38611@freescale.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Fugang Duan [Wed, 10 Dec 2014 05:46:08 +0000 (13:46 +0800)]
MLK-9919 net: fec: reinit MAC0 MII bus for MAC1 use after resume back
i.MX6SX-AI board has two enet MACs (MAC0 and MAC1), they share MAC0 MII
bus. When PHY0 don't connect to enet MAC0, MAC0 mii bus probe phy0 failed,
and the net interface is set to unattach mode. During suspend resume test,
driver don't reinit MAC0 after resume back, so MII bus don't work that causes
MAC1 also cannot access PHY1.
The patch just is workaround that reinit MAC0 MII bus for MAC1 using.
Fugang Duan [Mon, 13 Oct 2014 09:17:27 +0000 (17:17 +0800)]
MLK-9977 ARM: dts: imx6sx: specify the phy address
Since fec controller contain mdio bus, for imx serial chips, there have
no independent/external MDIO bus. ENET1 and ENET2 share use ENET1 mdio bus.
So, specify the phy address for two MACs.
The current enet RGMII TXCLK rise/fall time which could be observed(~0.85ns)
is longer than requirement (<=0.75ns).
The current setting, SPEED/DSE/SRE=10/110/1 is used, and then it needs to
increase DSE to 111 "37 Ohm @ 3.3V, 21 Ohm@1.8V, 34 Ohm for DDR". After the
change RGMII TXCLK match the spec requirement.
Robin Gong [Mon, 8 Dec 2014 09:30:40 +0000 (17:30 +0800)]
MLK-9768: dma: imx-sdma: fix UART loopback random failed
For UART, we need use old chn_real_count to know the real rx count even in
cylic dma mode, because UART driver use cyclic mode to increase performance
without any data loss.
Fugang Duan [Mon, 8 Dec 2014 09:05:32 +0000 (17:05 +0800)]
net: fec: init maximum receive buffer size for ring1 and ring2
i.MX6SX fec support three rx ring1, the current driver lost to init
ring1 and ring2 maximum receive buffer size, that cause receving
frame date length error. The driver reports "rcv is not +last" error
log in user case.
Signed-off-by: Fugang Duan <B38611@freescale.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Lothar Waßmann [Mon, 17 Nov 2014 09:51:22 +0000 (10:51 +0100)]
net: fec: use swab32s() instead of cpu_to_be32()
when swap_buffer() is being called, we know for sure, that we need to
byte swap the data. Furthermore, this function is called for swapping
data in both directions. Thus cpu_to_be32() is semantically not
correct for all use cases. Use swab32s() to reflect this.
Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de> Signed-off-by: David S. Miller <davem@davemloft.net>
Lothar Waßmann [Fri, 7 Nov 2014 09:02:47 +0000 (10:02 +0100)]
net: fec: fix regression on i.MX28 introduced by rx_copybreak support
commit 1b7bde6d659d ("net: fec: implement rx_copybreak to improve rx performance")
introduced a regression for i.MX28. The swap_buffer() function doing
the endian conversion of the received data on i.MX28 may access memory
beyond the actual packet size in the DMA buffer. fec_enet_copybreak()
does not copy those bytes, so that the last bytes of a packet may be
filled with invalid data after swapping.
This will likely lead to checksum errors on received packets.
E.g. when trying to mount an NFS rootfs:
UDP: bad checksum. From 192.168.1.225:111 to 192.168.100.73:44662 ulen 36
Do the byte swapping and copying to the new skb in one go if
necessary.
Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de> Tested-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Fugang Duan [Mon, 8 Dec 2014 08:27:54 +0000 (16:27 +0800)]
MLK-9828 ARM: imx: change uart clk parent to pll3_80m on i.mx6sx in default
By default, uboot set uart clk parent to OSC to make UART work when M4
is enabled. In the situation, uart maximum baud rate only reach at 1.5Mbps
that cannot match real case requirement.
The patch set the uart module clock source to pll3_80m in default. If
test low power case, it needs to add "uart_from_osc" in kernel command line.
Fugang Duan [Thu, 20 Nov 2014 09:50:41 +0000 (17:50 +0800)]
MLK-9893 tty: serial: imx: sync the completed and cur index
The current logic has one potential issue cause data buffer lost in
busy system. When sdma copy data buffer count is zero, completed index
also increase, which cause data buffer lost. The patch fix the issue.
Anson Huang [Tue, 19 Aug 2014 03:02:48 +0000 (11:02 +0800)]
ENGR00327584-1 : ARM: dts: imx6sx: add new ocram node for mega/fast save/restore
As when Mega/Fast mix power domain is off in DSM mode, ocram
need to do save/restore for entire space, some of the ocram
space is reserved by low power modules, so to make ocram save/restore
simple, we define a node including total ocram space for DSM
save/restore when mega/fast mix is off.
Shengjiu Wang [Thu, 23 Oct 2014 10:00:39 +0000 (18:00 +0800)]
MLK-9723-2: ASoC: fsl_sai: fix no frame clk in master mode
After several open/close sai test with ctrl+c, there will be I/O error.
The SAI can't work anymore, can't recover. There will be no frame clock.
With adding the software reset in trigger stop, the issue can be fixed.
Shengjiu Wang [Thu, 23 Oct 2014 09:17:30 +0000 (17:17 +0800)]
MLK-9723-1: ASoC: fsl_sai: add mclk divider function for master mode
SAI has 4 mclk source, and the divider is 8bit. fsl_sai_set_bclk will
select proper mclk source and calculate the divider.
After fsl_sai_set_bclk, enable the selected mclk in hw_params(), and
add hw_free() to disable the mclk.
Nicolin Chen [Mon, 4 Aug 2014 07:07:25 +0000 (15:07 +0800)]
ASoC: fsl_sai: Set SYNC bit of TCR2 to Asynchronous Mode
There is one design rule according to SAI's reference manual:
If the transmitter bit clock and frame sync are to be used by both transmitter
and receiver, the transmitter must be configured for asynchronous operation
and the receiver for synchronous operation.
And SYNC of TCR2 is a 2-width control bit:
00 Asynchronous mode.
01 Synchronous with receiver.
10 Synchronous with another SAI transmitter.
11 Synchronous with another SAI receiver.
So the driver should have set SYNC bit of TCR2 to 0x0, and meanwhile set SYNC
bit of RCR2 to 0x1 (Synchronous with transmitter).
Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Mark Brown <broonie@linaro.org>
(cherry picked from commit 855675f6e6a65688a7f4cf45b9b5a98cf6c6f5c3)
Nicolin Chen [Fri, 8 Aug 2014 10:41:19 +0000 (18:41 +0800)]
ASoC: fsl_sai: Make Synchronous and Asynchronous modes exclusive
The previous patch (ASoC: fsl_sai: Add asynchronous mode support) added
new Device Tree bindings for Asynchronous and Synchronous modes support.
However, these two shall not be present at the same time.
So this patch just simply makes them exclusive so as to avoid incorrect
Device Tree binding usage.
Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Mark Brown <broonie@linaro.org>
(cherry picked from commit ce7344a4ebabe90e064d3e087727f45624cdc942)
Nicolin Chen [Tue, 5 Aug 2014 07:32:05 +0000 (15:32 +0800)]
ASoC: fsl_sai: Add asynchronous mode support
SAI supports these operation modes:
1) asynchronous mode
Both Tx and Rx are set to be asynchronous.
2) synchronous mode (Rx sync with Tx)
Tx is set to be asynchronous, Rx is set to be synchronous.
3) synchronous mode (Tx sync with Rx)
Rx is set to be asynchronous, Tx is set to be synchronous.
4) synchronous mode (Tx/Rx sync with another SAI's Tx)
5) synchronous mode (Tx/Rx sync with another SAI's Rx)
* 4) and 5) are beyond this patch because they are related with another SAI.
As the initial version of this SAI driver, it supported 2) as default while
the others were totally missing.
So this patch just adds supports for 1) and 3).
Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Mark Brown <broonie@linaro.org>
(cherry picked from commit 08fdf65e37d560581233e06a659f73deeb3766f9)
Nicolin Chen [Mon, 4 Aug 2014 07:07:25 +0000 (15:07 +0800)]
ASoC: fsl_sai: Set SYNC bit of TCR2 to Asynchronous Mode
There is one design rule according to SAI's reference manual:
If the transmitter bit clock and frame sync are to be used by both transmitter
and receiver, the transmitter must be configured for asynchronous operation
and the receiver for synchronous operation.
And SYNC of TCR2 is a 2-width control bit:
00 Asynchronous mode.
01 Synchronous with receiver.
10 Synchronous with another SAI transmitter.
11 Synchronous with another SAI receiver.
So the driver should have set SYNC bit of TCR2 to 0x0, and meanwhile set SYNC
bit of RCR2 to 0x1 (Synchronous with transmitter).
Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Mark Brown <broonie@linaro.org>
(cherry picked from commit af96ff5b7448dc776dc24a5c4313c6ec1ee94e53)
Nicolin Chen [Tue, 5 Aug 2014 09:20:21 +0000 (17:20 +0800)]
ASoC: fsl_sai: Initialize with software reset
This patch adds software reset code in dai_probe() so as to make a true init
by clearing SAI's internal logic, including the bit clock generation, status
flags, and FIFO pointers.
Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Mark Brown <broonie@linaro.org>
(cherry picked from commit 376d1a92ca587d3974d4791cdb99baa8b8e7f0dd)
In 3f81aadd7e12ee7d83b271354b76316d31a04ffc, we set the ESAI clock route
in mach-imx6sx.c. In L3.14, as there is assigned-clks feature in devicetree,
we can set the clock route in dts file.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
Shengjiu Wang [Mon, 13 Oct 2014 03:47:32 +0000 (11:47 +0800)]
MLK-9684-6: ARM: clk-imx6sx: add missing lvds2 clock to the clock tree
We actually have lvds2 (analog clock2), an I/O clock like lvds1, in the SoC.
And this lvds2, along with lvds1, can be used to provide external clock source
to the internal pll, such as pll4_audio and pll5_video.
So This patch mainly adds the lvds2 to the clock tree and fix its relationship
with pll4 accordingly.
Shengjiu Wang [Mon, 13 Oct 2014 03:26:02 +0000 (11:26 +0800)]
MLK-9684-2: ASoC: imx-si476x: remove the codec_name, use the codec_of_node
As the codec_name has a suffix, which is a index and is different
for different platform or different kernel. So here change machine driver
to use codec_of_node, which can be same for different platform/kernel,
then we can maintain a same machine driver for fm.
Shengjiu Wang [Fri, 31 Oct 2014 05:51:20 +0000 (13:51 +0800)]
MLK-9731 ASoC: imx-hdmi-dma: audio output is noisy in long time playback
In the frame_to_bytes(), when hw_ptr*frame_bits exceed the maxmum of unsigned
long, the return value is saturated, so the appl_bytes is wrong.
This patch is to correct the usage of frame_to_bytes().
Shengjiu Wang [Tue, 18 Nov 2014 06:20:55 +0000 (14:20 +0800)]
MLK-9866: mfd: si476x: FM will fail to open sometimes.
In commit e856a0ebc23dcd2c933e3f902317652cc50f0067, we disabled
wait_event_timeout for CMD_POWER_DOWN, which will cause power down
failed sometimes, then FM will fail to reopen.
In this patch enable the wait_event_timeout for power down.
Shengjiu Wang [Mon, 3 Nov 2014 08:47:17 +0000 (16:47 +0800)]
MLK-9782: ASoC: fsl_esai: fix the channel swap issue in low possibility
There is very low possibility that channel swap happened in beginning when
multi output/input pin is enabled. The issue is that hardware can't send data
to correct pin in the begginning with the normal enable flow.
Here use TSMA/TSMB as the trigger for sending data to workaround this issue.
Shengjiu Wang [Wed, 29 Oct 2014 07:47:35 +0000 (15:47 +0800)]
MLK-9760: ASoC: fsl_esai: fix NULL pointer issue in reset handler
When test with case arecord -Dhw:0,1 | aplay -Dhw:0,0, xrun happened,
the reset handler will be called, but for BE(backend) stream, the
substream->ops is null.
This patch is to fix this null pointer issue.
Bai Ping [Thu, 4 Dec 2014 11:44:26 +0000 (19:44 +0800)]
MLK-9954 arm: imx: update operating point for i.MX6DL
Update the i.MX6DL cpu operating points to comply with the latest
published datasheet. Latest i.MX6DL datasheet of Rev.4, 10/2014
updates the 396MHz setpoint's min voltage from 1.075V to 1.125V, Add a
25mV margin to cover the board IR drop, here use 1.15V for 396MHz to
match datasheet.
Loren Huang [Wed, 26 Nov 2014 03:59:38 +0000 (11:59 +0800)]
MGS-304 [#1461]GPU driver will cause kernel panic when allocate memory failed
-The issue is triggered by suspend/resume test
when doing bonnie++ which will consume lots of
memory.
-The root cause is vivante didn't report the allocation
failure to uplevel correctly which cause the improper
free.
-Correct the free logic to fix this issue.
Date: Nov 26, 2014 Signed-off-by: Loren Huang <b02279@freescale.com> Acked-by: Jason Liu Tested-by: Peter Chen
(cherry picked from commit 2378f1c0b48f1c632a96c1e6c1107e2773f34170)
Loren Huang [Tue, 25 Nov 2014 08:19:49 +0000 (16:19 +0800)]
MGS-298 gpu:Add new option to enable shadow memory free
It's a specific requirement form customer.
Environmant variable VIV_FBO_PERFER_MEM is added.
When it's set, driver will free fbo shadow memory immediately
when it's switch out.
Original vivante patch name:cl29153.diff
Sandor Yu [Thu, 20 Nov 2014 08:36:25 +0000 (16:36 +0800)]
MLK-9779-05 csi: Remove csi driver source from mxc/capture folder
- Remove v4l2 csi capture driver, vadc driver and csi driver
from mxc/capture folder.
- Rename ov5640 module name from ov5640_camera.ko to
ov5640_camera_int.ko
Sandor Yu [Mon, 10 Nov 2014 07:36:49 +0000 (15:36 +0800)]
MLK-9779-01 camera: imx6sx/sl CSI/VADC driver in subdev
CSI and VADC driver rewrite with v4l2 subdev architecture.
- mx6s_capture.c driver support imx6sx and imx6sl csi module.
- No PXP function included in csi driver, csi driver not support
csc, crop and resize function.
- Both csi and vadc driver register device tree.
- v4l2 subdev bridge device drivers register device with asynchronous.
Bai Ping [Wed, 19 Nov 2014 16:35:38 +0000 (00:35 +0800)]
MLK-9876 cpufreq: imx6: update operating point for imx6Q
Update the imx6Q cpu operating points to comply with the latest
published datasheet. Latest i.MX6Q datasheet of Rev.3, 02/2014
updates the 792MHz setpoint's min voltage from 1.125V to 1.15V, add a
25mV margin to cover the board IR drop, here use 1.175V for 792MHz to
match datasheet.
Bai Ping [Sat, 8 Nov 2014 13:35:26 +0000 (21:35 +0800)]
MLK-9817 spi: imx: convert all clk_enable to clk_prepare_enable
This is done in preperation for low power mode. Convert all clk_enable
to clk_prepare_enable and clk_disable to clk_disable_unprepare. Make sure
PLL3 power down when entering low power mode.
Bai Ping [Mon, 10 Nov 2014 14:59:34 +0000 (22:59 +0800)]
MLK-9818 arm: imx: Add uart to be source from OSC 24MHz support
In order to optmize low power IDLE power number all PLLs should be in bypass mode.
On imx6sl, UART can be sourced directly from the 24MHz XTAL. Its frequency is
limited to 4MHz due to an internal divider of 6. For customer who don't require
higher uart speed, add "uart_at_4M" to the kernel command line.
Anson Huang [Tue, 11 Nov 2014 02:13:58 +0000 (10:13 +0800)]
MLK-9823 arm: imx: correct L2 controller settings after resume
As we have specific tag and data latency settings on our platforms,
so we have to restore these settings after resume with L2 controller
power gated. Otherwise, system perpormance will be impacted a lot:
dd read test(dd if=/dev/mmcblk2 of=/dev/null bs=1M count=2000) of SD
card would lower from 61.4MB/s to 57.7MB/s, ~6% drop.
Issue reproduce steps:
1. Boot up without HDMI cable plugin
2. Insert the HDMI cable.
3. echo mem > /sys/power/state , enter suspend,
4. resume it,
System can resume from suspend but display is blank.
Error log:
mxc_sdc_fb fb.31: Unable to allocate framebuffer memory
detected fb_set_par error, error code: -12
In mxc hdmi driver, if system bootup without hdmi cable plugin,
driver will create a default modelist.
In fbcon driver, array fb_display[] initialized when system bootup
and save current mode pointer that point to default modelist.
When hdmi cable is plugin the modelist will rebuild according edid
data, but the pointer of video mode in fb_display[] is not updated.
When system resume, fbcon will use the invalidate pointer to
configured framebuffer, framebuffer will crash.
Add function fb_new_modelist() after modelist is rebuild to fix the
issue.
Anson Huang [Mon, 20 Jan 2014 11:30:09 +0000 (19:30 +0800)]
ENGR00295814 ARM: dts: imx6qdl: correct gpio key's active state
From schematic, below GPIO keys' active state is low, so we need
to set correct active state in dts.
i.MX6Q/DL-SABRESD board: power, vol+ and vol-.
i.MX6Q/DL-SABREAUTO board: home, back, prog, vol+ and vol-.
Signed-off-by: Anson Huang <b20788@freescale.com>
(cherry picked from commit f1319b3268db3e0e80d85ba9f4ae3b569b916dd4) Signed-off-by: Robin Gong <b38343@freescale.com>
ARM: imx: replace cpu type check with ddr type check
As the DDR/IO and MMDC setting are different on LPDDR2 and DDR3,
we used cpu type to decide how to do these settings in suspend
before which is NOT flexible, take i.MX6SL for example, although
it has LPDDR2 on EVK board, but users can also use DDR3 on other
boards, so it is better to read the DDR type from MMDC then decide
how to do related settings.
Sandor Yu [Fri, 7 Nov 2014 03:14:05 +0000 (11:14 +0800)]
MLK-9808 HDMI: EDID bug fixes / improvements
Changes in order of appearence:
- If an EDID extension block other than the known (CEA extension) is found
don't fail monitor detection completely, just proceed to the next block.
- If 4 or more extensions are present two problems arise:
- only 2 extensions will actually be read and
- parsing will read beyond the buffer.
Throw a BUG() and add a comment, don't have time for a rewrite right now.
- The EDID I2C read code has a 1 second timeout - per byte. With 128 bytes
per block this could take over 2 minutes. And we have indeed seen a very
long pause on Linux shutdown on rare occasions. At 100 kHz reading a byte
takes 0.6 ms, reduce the timeout to 30 ms.
- Checking extblknum < 0 is pointless when its value was assigned from an
unsigned char.
- Some old monitors didn't set the 'number of EDID ext. blocks' field. 0xFF
means no extensions.
- Calling mxc_edid_parse_ext_blk() only makes sense if an ext. block was
actually read. Otherwise it's sure to fail, and monitor detection with it.
- As the 1st extension was parsed beforehand the following for loop must
start at 2, otherwise the 1st extension is parsed twice.
- Inside the read loop all bytes were written to tmpedid[1], It should
tmpedid[i].
- And then when parsing the read data they have to start at tmpedid[0],
not at tmpedid[EDID_LENGTH], which is beyond the buffer.
- Improved debugging a bit by inserting a message if reading fails and also
removing one that may be confused with another with the same text.
- If getting the EDID data fails we will retry once. But if the failure was
due to not being able to parse the data rather than a read error
re-reading will yield HDMI_EDID_SAME. The code will misinterpret that as
'no change, video modes already set up'. Instead continue with the status
code of the initial attempt.
- Before retrying wait 0.2 s, most likely reading initially failed because
the cable had not been fully inserted.
ENGR00323271-02 hdmi: Add mipi core clock to hdmi drivers
HDMI isfr clock source from video 27M clock.
There are one clock gate control of video27m_root in CCM,
ccm_video27m_root_cg = ((lpcg_mipi_core_cfg_clk_enable_clock_root
| lpcg_mipi_core_pll_refclk_enable_clock_root) | lpcg_vpu_rclk_enable_clock_root);
The video 27M clock depend on vpu clock or mipi core clock.
In mx6 chip, vpu can been disabled by fuse,
so for vpu disabled case, mipi core clock should enabled and make sure
27M clock on.
Add mipi core clock management in hdmi drivers to support vpu disabled
case.
Liu Ying [Wed, 5 Nov 2014 07:28:29 +0000 (15:28 +0800)]
MLK-8906 video: mxc: mipi dsi: Set panel vm back to var in .setup()
In order to prevent some critical framebuffer var entries(e.g.,
sync/vmode flags) from being changed, this patch sets the active
mipi dsi panel's video mode back to the framebuffer var.
ENGR00332861 ARM:imx6x: Fix build break caused by GPU driver.
The GPU driver fails to build when the kernel is not built in-place,
KBUILD_OUTPUT is set to point to some other directory.
This patch fixes this issue.
Loren Huang [Fri, 15 Aug 2014 06:05:05 +0000 (14:05 +0800)]
ENGR00327306 [#1325]Make 3dMinClock be changeable
-Add sys interface for changing 3DMinClock.
This feature is blocked by vivante kernel platform change.
Sys interface /sys/bus/platform/drivers/galcore/gpu3DMinclock
is used for configure this value.
It's important feature for thermal.
it is not complete in the original implementation to query virtual command buffer,
it is necessary to this fix to get the correct GPU virtual memory result.
also include virtual command buffer database for Vivante gcDB tool.
Fugang Duan [Tue, 4 Nov 2014 05:23:34 +0000 (13:23 +0800)]
MLK-9786 net: fec: Add busfreq support to the driver
Add request_bus_freq() and release_bus_freq() calls to the
various drivers to ensure that the DDR and AHB are the requested
frequency before the driver starts its task.
Bai Ping [Fri, 31 Oct 2014 08:28:03 +0000 (16:28 +0800)]
MLK-9777 cpufreq: imx6: fix the high bus count mismatch
Normally, the system is booting up with higher cpufreq. In the
cpufreq set_target_index we will release the high bus mode if
the target cpu frequency is the lowest. It will release the high
bus mode and dcrease the high_bus_count.This will lead to a wrong
release of high bus mode. So, in the cpufreq_init function, if the
original frequency is not the lowest, we need request high busfreq.
Bai Ping [Mon, 27 Oct 2014 06:28:08 +0000 (14:28 +0800)]
MLK-9721 arm: imx6: add busfreq support for imx6sl
Add busfreq node in the dtsi file and modified the source code
to support imx6sl to enter low busfreq mode.
As the clk tree of imx6sl on 3.14 branch different with imx6q,
imx6sx, etc. So the busfreq change flow need some additional
code. Especially, after change the bus frequency to 24MHz, the
clock parent-child relationship need one more step to update.
Before change to 24MHz low bus mode, the clock tree between the
OSC and MMDC as below:
So the parent of pll2_bypass clock need to be set to pll2_bypass_src after
entering 24MHz mode, and set to pll2 after exiting 24MHz to reflect the correct
parent-child relationship in kernel.
Changing dev_dbg to printk to ease the debug of busfreq driver, print the busfreq
change information as needed.
projects / karo-tx-linux.git / log