Alan Tull [Fri, 17 Feb 2012 21:15:35 +0000 (15:15 -0600)]
ENGR00174809 hdmi audio oops in hdmi_dma_mmap_copy
Runtime dma_area may be invalid after trigger stop command.
This will cause an oops in hdmi_dma_mmap_copy. To fix this,
disable mmap copying with trigger stop command and also check
the runtime->dma_area before doing hdmi_dma_mmap_copy.
Chen Liangjun [Fri, 17 Feb 2012 06:33:50 +0000 (14:33 +0800)]
ENGR00174747 ASRC:fix spinlock bug
When use clk_enable and clk_disable function, system may enter
sleep. so these 2 funciton can not used surrounding with spin
lock/unlock. And the clk_enable/disable function already keep
the counter of open and close and it is no need to keep the counter
in driver.
Wayne Zou [Tue, 14 Feb 2012 01:10:53 +0000 (09:10 +0800)]
ENGR00174394 MX6Q_arm2/MX6Q_sabreauto: change ipu_id/disp_id for LDB config.
MX6Q_arm2/MX6Q_sabreauto: change ipu_id/disp_id for LDB configuration.
For, LDB_SEP0 mode, the disp_id should be 0, and sec_disp_id should be
1 on MX6Q, since the LDB channel 0 should be connected to IPU DI0.
Jason Liu [Wed, 15 Feb 2012 10:34:41 +0000 (18:34 +0800)]
ENGR00174540: i.mx6: anatop_regulator: LDO voltage print not correctly
The LDO voltage constraint not printed correctly:
print_constraints: vddpu: 725 <--> 1300 mV at 700 mV fast normal
print_constraints: vddsoc: 725 <--> 1300 mV at 700 mV fast normal
print_constraints: vdd2p5: 2000 <--> 2775 mV at 2000 mV fast normal
print_constraints: vdd1p1: 800 <--> 1400 mV at 700 mV fast normal
print_constraints: vdd3p0: 2800 <--> 3150 mV at 2625 mV fast normal
There due to one typo: << in the code, thus will make the LDO constraint print
not correctly, the patch will make the print correctly as the followings:
print_constraints: vddpu: 725 <--> 1300 mV at 1100 mV fast normal
print_constraints: vddsoc: 725 <--> 1300 mV at 1200 mV fast normal
print_constraints: vdd2p5: 2000 <--> 2775 mV at 2400 mV fast normal
print_constraints: vdd1p1: 800 <--> 1400 mV at 1100 mV fast normal
print_constraints: vdd3p0: 2800 <--> 3150 mV at 3000 mV fast normal
Danny Nold [Tue, 14 Feb 2012 23:15:23 +0000 (17:15 -0600)]
ENGR00174106-3 - EPDC fb: Support EPDC v2.0
- Added new register definitions for EPDCv2.0
- Added support for 64 LUTs
- Conditionalized code for EPDC versions 1.0, 2.0, and 2.1
- Support for EPDC auto-waveform selection
- Support for collision test mode
- Support for PxP bypassing
- Support for LUT cancellation
- Support for new PxP limitations
- Support for collision minimization EPDC feature
- Added workaround for collision status bug (can't clear
IRQ before reading collision status for LUTs 16-63)
Signed-off-by: Danny Nold <dannynold@freescale.com>
Fugang Duan [Tue, 14 Feb 2012 08:56:26 +0000 (16:56 +0800)]
ENGR00172274-02 - [MX6]: rework IEEE-1588 in MX6Q Sabre-lite/sd board.
- Config GPIO_16 pad to ENET_ANATOP_ETHERNET_REF_OUT.
- IEEE-1588 ts_clk and i2c3 are mutually exclusive, because
all of them use GPIO_16, so it only for one function work
at a moment.
- Test result:
TO1.1 IEEE 1588 is convergent in Sabrelite board.
Chen Liangjun [Tue, 14 Feb 2012 03:23:30 +0000 (11:23 +0800)]
ENGR00174399 ASRC: fix mmap fail bug
If output sample rate is less than input sample rate, it is possible
that the address of output dma buffer 0 can not be divided by page size.
Thus the mmap of output dma in the user space would fail and test
would fail.
let all output dma buffers allocate dma buffer together and we can
assure that the address of output dma buffer 0 can be divided by
page size.
Liu Ying [Mon, 13 Feb 2012 09:45:17 +0000 (17:45 +0800)]
ENGR00174395 V4L2 capture: Driver improvement
1) CSI module should be disabled first for CSI_MEM channel,
otherwise, the capture channels will hang after restarting
for several times.
2) Disable CSI module correctly for overlay. Move stopping
preview channel operation out of de-select interface.
3) Check cam->overlay_on is true in close function before
stopping preview.
4) Check cam->vf_start_sdc function before calling it.
Sammy He [Tue, 14 Feb 2012 02:09:05 +0000 (10:09 +0800)]
ENGR00174323 vpu: Fix system hang issue of multi-instances processing
VPU registers have been mapped with ioremap() at probe which
L_PTE_XN is 1, and the same physical address must be mapped multiple
times with same type when doing mmap() to user space, so also need
to set it to 1. Otherwise, there may be unexpected result in video
codec.
Here, Use new defined pgprot_noncachedxn for vm_page_prot in mmap().
Tony Lin [Fri, 10 Feb 2012 09:06:21 +0000 (17:06 +0800)]
ENGR00174232 [mx6q perfmon]PDM No. TKT055916: remove workaround for TO1.1
remove the workaround
For TO1.0: bit16 of GPR11 must be set to enable perfmon
For TO1.1 and later: bit0 of GPR11 is enable bit for perfmon.
set 1/0 to enable/disable perfmon
Xinyu Chen [Fri, 10 Feb 2012 07:54:41 +0000 (15:54 +0800)]
ENGR00174127 mag3110: merge the mag3110 sensor driver
Merge mag3110 drivers from sensor team.
The drivers are updated with chip position configure
in driver, export set delay interface to userspace and
use polling mode instead of interrupt mode.
Merge mma8451 drivers from sensor team.
The drivers are updated with chip position configure
in driver, export enable and position interface to userspace.
Zhang Jiejing [Wed, 11 Jan 2012 06:20:15 +0000 (14:20 +0800)]
ENGR00173857 MX6Q: add 600M work point
Add a 600M work point for better suit for cpufreq driver.
For current MX6Q clock tree, the most near 600M working point
is 624M, so we use 624M as 600M working point.
We found we have 200/400/800/1G working point is not very
good for cpufreq adjustment, since we don't have a uniform
working point distribution, since the interactive governor
is using cpu usage to adjust frequency, eg, 60% CPU, going
to 600M working point, if above a threshold (%85 default)
will going to max frequency directly.
From the [sheet] , you can see in game case, it will have much
chance in 400M working point, between 400M and 800M working
point, there is a gap, so the 400M will be most used frequency.
we add 600 WP to fill this gap, and make game case have
better experience.
Richard Zhu [Wed, 8 Feb 2012 06:58:41 +0000 (14:58 +0800)]
ENGR00174033-2 MX6 PCIE: add pcie RC driver
Add PCIE RC driver on MX6 platforms.
Based on iwl4965agn pcie wifi device, verified the following
features.
* Link up is stable
* map the CFG, IO and MEM spaces, and CFG/MEM spaces can accessed
Richard Zhu [Wed, 8 Feb 2012 06:57:56 +0000 (14:57 +0800)]
ENGR00174033-1 MX6 PCIE: add pcie RC driver
Add PCIE RC driver on MX6 platforms.
Based on iwl4965agn pcie wifi device, verified the following
features.
* Link up is stable
* map the CFG, IO and MEM spaces, and CFG/MEM spaces can be accessed
Peter Chen [Thu, 9 Feb 2012 09:38:59 +0000 (17:38 +0800)]
ENGR00174128-1 Revert "Remove the discharge for VBUS and DP-1"
As dp/dm is floating with no usb cable and switch host mode to
device mode situation, it do needs this discharge dp patch
But, discharge vbus doesn't be needed at suspend_irq, so
keep it removing.
Nancy Chen [Thu, 9 Feb 2012 16:27:07 +0000 (10:27 -0600)]
ENGR00174094 i.MX6DL: Change CPU voltages to 1V
Change CPU voltages (0.95V and 0.85V) to 1V
CPU voltage should be above 1.0V for all CPU frequency
since L1 Cache power is connected to VDDARM internally.
Jason Liu [Thu, 9 Feb 2012 06:09:58 +0000 (14:09 +0800)]
ENGR00174152 i.mx6/clock: set ddr clock parent to pll2_mfd_400M
on i.mx6dl, DDR clock is sourcing from pll2_mfd_400M, so, we need
set DDR/periph_clk parent to pll2_mfd_400M during clock init, which
will setup the clock usecount of pll2_mfd_400M correctly, otherwise,
when all the child device with clock source from pll2_mfd_400M turn
off, the pll2_mfd_400M will turns off automaticly, which will cause
system hang due to DDR clock is off when code is runing on it.
Peter Chen [Thu, 9 Feb 2012 09:07:44 +0000 (17:07 +0800)]
ENGR00174124: Revert "[USB Host]change the default wakeup value of RH"
This patch creates two bugs at current i.mx usb framework.
- The high speed device can't be recognized at the first time.
- The usb device can't be recognized after system resume with
usb vbus.
The reason why it creates bugs that it changes (auto)suspend/resume
process for usb core.
Tony LIU [Wed, 8 Feb 2012 07:33:56 +0000 (15:33 +0800)]
ENGR00174037-1 Add HSIC suspend/resume feature
MSL part
- For HSIC, not connect nor disconnect, then WKCN,
WKDC must not be set during suspend
- For HSIC, must set bit 21 in host control registry
after device connected to host controller
- USB PHY 480M clock output must turn on to avoid about
10ms delay before sending out resume signal
- HW_ANA_MISC clkgate delay must be set to 2 or 3 to
avoid 24M OSCI not stable issue
Signed-off-by: Tony LIU <junjie.liu@freescale.com>
Alan Tull [Wed, 8 Feb 2012 22:40:31 +0000 (16:40 -0600)]
ENGR00172342-2 EDID parse audio data blocks
Add functionality to parse Audio Data Blocks from EDID data to
find out what modes of LPCM are suppored by the HDMI sink device.
The parsed settings are saved in the hdmi mfd. The HDMI audio driver
will check the settings when the audio stream is opened and will
then apply appropriate constraints.
If we are unable to read from the EDID, then we default to supporting
Basic Audio as defined by the HDMI specification (stereo, 16 bit,
32KHz, 44.1KHz, 48KHz PCM).
Alan Tull [Thu, 26 Jan 2012 17:37:01 +0000 (11:37 -0600)]
ENGR00172342-1 EDID parse audio data blocks
Add functionality to parse Audio Data Blocks from EDID data to
find out what modes of LPCM are suppored by the HDMI sink device.
The parsed settings are saved in the hdmi mfd. The HDMI audio driver
will check the settings when the audio stream is opened and will
then apply appropriate constraints.
If we are unable to read from the EDID, then we default to supporting
Basic Audio as defined by the HDMI specification (stereo, 16 bit,
32KHz, 44.1KHz, 48KHz PCM).
Wayne Zou [Thu, 2 Feb 2012 07:10:35 +0000 (15:10 +0800)]
ENGR00171353 MIPI_DSI: mipi display blank and unblank fail fixed
mipi display blank and unblank fail on HW board: MX6Q_ARM2 1G SN 0112
The host processor sends PCLK, HS and VS information to display modules
two frames before sleep-out command is sent.
Sandor Yu [Wed, 8 Feb 2012 05:45:18 +0000 (13:45 +0800)]
ENGR00173962 Added HDMI enable function
Whenever IPU clock change or gating, the HDMI PHY should reset or config again,
otherwise the HDMI PHY will not work.
It is the root cause for Ubuntu can't show GUI to HDMI device when bootup
and GPU application tutorial4_es20 no output to HDMI device.
Added enable function in mxcfb_set_par() to fix aboved two issue.
Added HDMI initialization check, only one HDMI instanse supported.
After over 1100 (!) patches we have now reached a state where I would
like to start discussing about pushing the driver to the wireless
trees and replacing the staging driver.
The driver is now a lot smaller and looks like a proper Linux driver.
The size of the driver (measured with simple wc -l) dropped from 49
kLOC to 18 kLOC and the number of the .c and .h files dropped from 107
to 22. Most importantly the number of subdirectories reduced from 26
to zero :)
There are two remaining checkpatch warnings in the driver which we
decided to omit for now:
drivers/net/wireless/ath/ath6kl/debug.c:31:
WARNING: printk() should include KERN_ facility level
drivers/net/wireless/ath/ath6kl/sdio.c:527:
WARNING: msleep < 20ms can sleep for up to 20ms;
see Documentation/timers/timers-howto.txt
The driver has endian annotations for all the hardware specific
structures and there are no sparse errors. Unfortunately I don't have
any big endian hardware to test that right now.
We have been testing the driver both on x86 and arm platforms. The
code is also compiled with sparc and parisc cross compilers.
Notable missing features compared to the current staging driver are:
o HCI over SDIO support
o nl80211 testmode
o firmware logging
o suspend support
Testmode, firmware logging and suspend support will be added soon. HCI
over SDIO support will be more difficult as the HCI driver needs to
share code with the wifi driver. This is something we need to research
more.
Also I want to point out the changes I did for signed endian support.
As I wasn't able to find any support for signed endian annotations I
decided to follow what NTFS has done and added my own. Grep for sle16
and sle32, especially from wmi.h.
Various people have been working on the cleanup, the hall of
fame based on number of patches is:
543 Vasanthakumar Thiagarajan
403 Raja Mani
252 Kalle Valo
16 Vivek Natarajan
12 Suraj Sumangala
3 Joe Perches
2 Jouni Malinen
Signed-off-by: Vasanthakumar Thiagarajan <vthiagar@qca.qualcomm.com> Signed-off-by: Raja Mani <rmani@qca.qualcomm.com> Signed-off-by: Vivek Natarajan <nataraja@qca.qualcomm.com> Signed-off-by: Suraj Sumangala <surajs@qca.qualcomm.com> Signed-off-by: Joe Perches <joe@perches.com> Signed-off-by: Jouni Malinen <jouni@qca.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
Fugang Duan [Wed, 8 Feb 2012 03:39:25 +0000 (11:39 +0800)]
ENGR00172274-02 - IEEE-1588: rework ts_clk in MX6 ARIK CPU board.
Default use RMII 50MHz clock for ts_clk.
Test result:
Enet work fine at 100/1000Mbps in TO1.1 and Rigel.
IEEE 1588 timestamp is convergent for 25M & 50M & 100MHz
timestamp clock.
Fugang Duan [Wed, 8 Feb 2012 03:26:58 +0000 (11:26 +0800)]
ENGR00172274-01 - [MX6]: rework IEEE-1588 ts_clk in MX6Q ARIK CPU board.
- Fix GPIO_16 IOMUX config.
- Config GPIO_16 pad to ENET_ANATOP_ETHERNET_REF_OUT.
- IEEE-1588 ts_clk, S/PDIF in and i2c3 are mutually exclusive,
because all of them use GPIO_16, so it only for one function
work at a moment.
- Test result:
Enet work fine at 100/1000Mbps in TO1.1.
IEEE 1588 timestamp is convergent.
Jason Liu [Tue, 7 Feb 2012 06:00:21 +0000 (14:00 +0800)]
ENGR00173869-3: i.mx6: add the cpu_is_mx6dl() support
In order to support one image for i.mx6q and i.mx6dl, we introduce
the below functions by diff the value reading from ANATOP ID register.
cpu_is_mx6q() and cpu_is_mx6dl()
The layout for the register defines:
Major Minor
i.MX6Q1.1: 6300 01
i.MX6Q1.0: 6300 00
i.MX6DL1.0: 6100 00
For the common bits shared across all i.mx6 ports, we can use:
cpu_is_mx6() for it.
Huang Shijie [Wed, 18 Jan 2012 02:51:40 +0000 (10:51 +0800)]
ENGR00173731-3 mxs-dma : rewrite the last parameter of mxs_dma_prep_slave_sg()
[1] Background :
The GPMI does ECC read page operation with a DMA chain consist of three DMA
Command Structures. The middle one of the chain is used to enable the BCH,
and read out the NAND page.
The WAIT4END(wait for command end) is a comunication signal between
the GPMI and MXS-DMA.
[2] The current DMA code sets the WAIT4END bit at the last one, such as:
[3] But in the new GPMI version (used in MX50/MX60), the WAIT4END bit should
be set not only at the last DMA Command Structure,
but also at the middle one, such as:
+-----+ +-----+ +-----+
| cmd | ------------> | cmd | ------------------> | cmd |
+-----+ +-----+ +-----+
^ ^
| |
| |
set WAIT4END here too set WAIT4END here
If we do not set WAIT4END, the BCH maybe stalls in "ECC reading page" state.
In the next ECC write page operation, a DMA-timeout occurs.
This has been catched in the MX6Q board.
[4] In order to fix the bug, rewrite the last parameter of
mxs_dma_prep_slave_sg(), and use the dma_ctrl_flags:
---------------------------------------------------------
DMA_PREP_INTERRUPT : append a new DMA Command Structrue.
DMA_CTRL_ACK : set the WAIT4END bit for this DMA Command Structure.
---------------------------------------------------------
[5] changes to the relative drivers:
For gpmi-nand driver: use the new flags.
Huang Shijie [Mon, 6 Feb 2012 02:47:02 +0000 (10:47 +0800)]
ENGR00173731-1 mxs-dma : rename the dma.h for mxs-dma
Move the header to a more common place.
The mxs dma engine is not only used in mx23/mx28, but also used
in mx50/mx6q. It will also be used in the future chips.
projects / karo-tx-linux.git / log