Linus Torvalds [Sat, 27 Feb 2010 21:26:18 +0000 (13:26 -0800)]
Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc
* 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: (88 commits)
powerpc: Fix lwsync feature fixup vs. modules on 64-bit
powerpc: Convert pmc_owner_lock to raw_spinlock
powerpc: Convert die.lock to raw_spinlock
powerpc: Convert tlbivax_lock to raw_spinlock
powerpc: Convert mpic locks to raw_spinlock
powerpc: Convert pmac_pic_lock to raw_spinlock
powerpc: Convert big_irq_lock to raw_spinlock
powerpc: Convert feature_lock to raw_spinlock
powerpc: Convert i8259_lock to raw_spinlock
powerpc: Convert beat_htab_lock to raw_spinlock
powerpc: Convert confirm_error_lock to raw_spinlock
powerpc: Convert ipic_lock to raw_spinlock
powerpc: Convert native_tlbie_lock to raw_spinlock
powerpc: Convert beatic_irq_mask_lock to raw_spinlock
powerpc: Convert nv_lock to raw_spinlock
powerpc: Convert context_lock to raw_spinlock
powerpc/85xx: Add NOR, LEDs and PIB support for MPC8568E-MDS boards
powerpc/86xx: Enable VME driver on the GE SBC610
powerpc/86xx: Enable VME driver on the GE PPC9A
powerpc/86xx: Add MSI section to GE PPC9A DTS
...
Bjorn Helgaas [Wed, 24 Feb 2010 20:53:27 +0000 (13:53 -0700)]
MIPS: Cobalt: convert legacy port addresses to GT-64111 bus addresses
The GT-64111 PCI host bridge has no address translation mechanism, so
it can't generate legacy port accesses. This quirk fixes legacy device
port resources to contain the bus addresses actually generated by the
GT-64111.
I think this is the approach Ben Herrenschmidt suggested long ago:
http://marc.info/?l=linux-kernel&m=119733290624544&w=2
This allows us to remove the IORESOURCE_PCI_FIXED hack from
pcibios_fixup_device_resources(), which converts bus addresses to CPU
addresses. IORESOURCE_PCI_FIXED denotes resources that can't be moved;
it has nothing to do with converting bus to CPU addresses.
Manuel Lauss [Wed, 24 Feb 2010 16:40:21 +0000 (17:40 +0100)]
MIPS: Alchemy: use 36bit addresses for PCMCIA resources.
On Alchemy the PCMCIA area lies at the end of the chips 36bit system bus
area. Currently, addresses at the far end of the 32bit area are assumed
to belong to the PCMCIA area and fixed up to the real 36bit address before
being passed to ioremap().
A previous commit enabled 64 bit physical size for the resource datatype on
Alchemy and this allows to use the correct 36bit addresses when registering
the PCMCIA sockets.
This patch removes the 32-to-36bit address fixup and registers the Alchemy
demo board pcmcia socket with the correct 36bit physical addresses.
Tested on DB1200, with a CF card (ide-cs driver) and a 3c589 PCMCIA ethernet
card.
Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com>
To: Linux-MIPS <linux-mips@linux-mips.org> Cc: Manuel Lauss <manuel.lauss@gmail.com>
Patchwork: http://patchwork.linux-mips.org/patch/994/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Ralf Baechle [Wed, 24 Feb 2010 16:41:00 +0000 (17:41 +0100)]
MIPS: Cobalt: Fix theoretical port aliasing issue
Because the VIA SuperIO chip only decodes 24 bits of address space but port
address space currently being configured as 32MB there is the theoretical
possibility of aliases within the I/O port address range.
The complicated solution is to reserve all address range that potencially
could cause such aliases. But with the PCI spec limiting port allocations
for devices to a maximum of 256 bytes 16MB of port address space already is
way more than one would ever expect to be used so we just reduce the port
space to 16MB.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
To: Yoichi Yuasa <yuasa@linux-mips.org> Cc: Bjorn Helgaas <bjorn.helgaas@hp.com> Cc: linux-mips@linux-mips.org Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Patchwork: http://patchwork.linux-mips.org/patch/995/
David Daney [Thu, 4 Feb 2010 19:31:49 +0000 (11:31 -0800)]
MIPS: Optimize spinlocks.
The current locking mechanism uses a ll/sc sequence to release a
spinlock. This is slower than a wmb() followed by a store to unlock.
The branching forward to .subsection 2 on sc failure slows down the
contended case. So we get rid of that part too.
Since we are now working on naturally aligned u16 values, we can get
rid of a masking operation as the LHU already does the right thing.
The ANDI are reversed for better scheduling on multi-issue CPUs
On a 12 CPU 750MHz Octeon cn5750 this patch improves ipv4 UDP packet
forwarding rates from 3.58*10^6 PPS to 3.99*10^6 PPS, or about 11%.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/937/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Change to different macros for assembler macros since the old names in
powertv_setup.c were co-opted for use in asm/asm.h. This broken the
build for the powertv platform. This patch introduces new macros based on
the new macros in asm.h to take the place of the old macro values.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
To: netdev@vger.kernel.org
To: gregkh@suse.de
Patchwork: http://patchwork.linux-mips.org/patch/970/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
David Daney [Wed, 17 Feb 2010 01:25:32 +0000 (17:25 -0800)]
Staging: Octeon: Reformat a bunch of comments.
Many of the comments didn't follow kerneldoc guidlines.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
To: netdev@vger.kernel.org
To: gregkh@suse.de
Patchwork: http://patchwork.linux-mips.org/patch/971/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
David Daney [Mon, 15 Feb 2010 23:06:47 +0000 (15:06 -0800)]
Staging: Octeon: Free transmit SKBs in a timely manner
If we wait for the once-per-second cleanup to free transmit SKBs,
sockets with small transmit buffer sizes might spend most of their
time blocked waiting for the cleanup.
Normally we do a cleanup for each transmitted packet. We add a
watchdog type timer so that we also schedule a timeout for 150uS after
a packet is transmitted. The watchdog is reset for each transmitted
packet, so for high packet rates, it never expires. At these high
rates, the cleanups are done for each packet so the extra watchdog
initiated cleanups are neither needed nor triggered.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
To: netdev@vger.kernel.org
To: gregkh@suse.de Cc: Eric Dumazet <eric.dumazet@gmail.com>
Patchwork: http://patchwork.linux-mips.org/patch/968/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This version has spelling and comment changes based on feedback from
Eric Dumazet.
David Daney [Mon, 15 Feb 2010 20:13:18 +0000 (12:13 -0800)]
MIPS: Octeon: Do proper acknowledgment of CIU timer interrupts.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
To: netdev@vger.kernel.org
To: gregkh@suse.de
Patchwork: http://patchwork.linux-mips.org/patch/967/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
David Daney [Mon, 15 Feb 2010 20:13:17 +0000 (12:13 -0800)]
Staging: Octeon: Run phy bus accesses on a workqueue.
When directly accessing a phy, we must acquire the mdio bus lock. To
do that we cannot be in interrupt context, so we need to move these
operations to a workqueue.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
To: netdev@vger.kernel.org
To: gregkh@suse.de
Patchwork: http://patchwork.linux-mips.org/patch/965/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
David Daney [Mon, 15 Feb 2010 20:13:16 +0000 (12:13 -0800)]
Staging: octeon: remove unneeded includes
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
To: netdev@vger.kernel.org
To: gregkh@suse.de
Patchwork: http://patchwork.linux-mips.org/patch/964/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
David Daney [Wed, 10 Feb 2010 23:12:47 +0000 (15:12 -0800)]
MIPS: Implement Read Inhibit/eXecute Inhibit
The SmartMIPS ASE specifies how Read Inhibit (RI) and eXecute Inhibit
(XI) bits in the page tables work. The upper two bits of EntryLo{0,1}
are RI and XI when the feature is enabled in the PageGrain register.
SmartMIPS only covers 32-bit systems. Cavium Octeon+ extends this to
64-bit systems by continuing to place the RI and XI bits in the top of
EntryLo even when EntryLo is 64-bits wide.
Because we need to carry the RI and XI bits in the PTE, the layout of
the PTE is changed. There is a two instruction overhead in the TLB
refill hot path to get the EntryLo bits into the proper position.
Also the TLB load exception has to probe the TLB to check if RI or XI
caused the exception.
Also of note is that the layout of the PTE bits is done at compile and
runtime rather than statically. In the 32-bit case this allows for
the same number of PFN bits as before the patch as the _PAGE_HUGE is
not supported in 32-bit kernels (we have _PAGE_NO_EXEC and
_PAGE_NO_READ instead of _PAGE_READ and _PAGE_HUGE).
The patch is tested on Cavium Octeon+, but should also work on 32-bit
systems with the Smart-MIPS ASE.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/952/
Patchwork: http://patchwork.linux-mips.org/patch/956/
Patchwork: http://patchwork.linux-mips.org/patch/962/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
David Daney [Wed, 10 Feb 2010 23:12:44 +0000 (15:12 -0800)]
MIPS: Use 64-bit stores to c0_entrylo on 64-bit kernels.
64-bit CPUs have 64-bit c0_entrylo{0,1} registers. We should use the
64-bit dmtc0 instruction to set them. This becomes important if we
want to set the RI and XI bits present in some processors.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/954/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Frans Pop [Sat, 6 Feb 2010 17:47:13 +0000 (18:47 +0100)]
MIPS: Remove trailing space in messages
Signed-off-by: Frans Pop <elendil@planet.nl>
To: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/946/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Wu Zhangjin [Sun, 31 Jan 2010 12:39:40 +0000 (20:39 +0800)]
MIPS: Make the debugging of compressed kernel configurable
This patch adds a new DEBUG_ZBOOT option to allow the users to enable it
to debug the compressed kernel support for a new board and this optoin
should be disabled to reduce the kernel image size and speed up the
kernel booting procedure when the compressed kernel support is stable.
Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com>
To: Ralf Baechle <ralf@linux-mips.org> Cc: Manuel Lauss <manuel.lauss@googlemail.com> Cc: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/918/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
David Daney [Fri, 29 Jan 2010 00:52:12 +0000 (16:52 -0800)]
MIPS: Allow the auxv's elf_platform entry to be set.
The userspace runtime linker uses the elf_platform to find the libraries
optimized for the current CPU archecture variant. First we need to allow it
to be set to something other than NULL. Follow-on patches will set some
values for specific CPUs.
GLIBC already does the right thing. The kernel just needs to supply good
data.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/891/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Manuel Lauss [Wed, 14 Oct 2009 07:38:06 +0000 (09:38 +0200)]
MMC: AU1xMMC: Allow platforms to disable host capabilities
Although the hardware supports a 4/8bit SD interface and the driver
unconditionally advertises all hardware caps to the MMC core, not all
datalines may actually be wired up. This patch introduces another
field to au1xmmc platform data allowing platforms to disable certain
advanced host controller features.
Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com>
To: linux-mmc@vger.kernel.org CC: Linux-MIPS <linux-mips@linux-mips.org>
Patchwork: http://patchwork.linux-mips.org/patch/460/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Florian Fainelli [Thu, 28 Jan 2010 14:22:37 +0000 (15:22 +0100)]
MIPS: Deal with larger physical offsets
AR7 has a larger physical offset than other MIPS based systems and therefore
needs to setup its handlers beyond the usual KSEG0 range. When running the
kernel in mapped mode this modification is also required. Remove function
comment which is now incorrect.
Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Eugene Konev <ejka@imfi.kspu.ru> Signed-off-by: Florian Fainelli <florian@openwrt.org>
To: linux-mips@linux-mips.org
To: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Cc: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/889/
Patchwork: http://patchwork.linux-mips.org/patch/932/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Wu Zhangjin [Wed, 27 Jan 2010 14:39:46 +0000 (22:39 +0800)]
MIPS: Loongson: Cleanup the halt and poweroff action
In the old source code, I have let halt and poweroff do the same action,
but in reality, they have different meanings.
As the manpage of shutdown shows:
-r Reboot after shutdown.
-H Halt action is to halt or drop into boot monitor on systems that support it.
-P Halt action is to turn off the power.
and in the real world, some machines(e.g. NAS) did not provide a power
button and the shutdown works as reset, so, we need to provide a
mechanism to let the users turn off the power safely without breaking
the system, such a mechanism is "halt", which only put the system into a
dead loop or a power-save mode and print some information to the screen
to tell the users to turn off the power safely.
$ shutdown -hH now /* loongson_halt, not turn off the power */
$ shutdown -hP now /* loongson_poweroff, work as poweroff */
Roel Kluin [Tue, 19 Jan 2010 23:59:27 +0000 (00:59 +0100)]
MIPS: Cleanup switches with cases that can be merged
Signed-off-by: Roel Kluin <roel.kluin@gmail.com>
To: linux-mips@linux-mips.org
To: Andrew Morton <akpm@linux-foundation.org>
To: LKML <linux-kernel@vger.kernel.org>
Patchwork: http://patchwork.linux-mips.org/patch/860/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
David Daney [Fri, 22 Jan 2010 22:41:14 +0000 (14:41 -0800)]
MIPS: Remove probe_tlb().
The function probe_tlb() only does anything for processors that are
not PRID_COMP_LEGACY. This is precisely the set of processors for
which decode_configs() is called to do identical tlbsize probing
calculations. Therefore probe_tlb() is completely redundant and may
be removed.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/865/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Florian Fainelli [Wed, 16 Dec 2009 10:29:06 +0000 (11:29 +0100)]
MIPS: add readl/write_be accessors
MIPS currently lacks the readl_be and writel_be accessors
which are required by BCM63xx for OHCI and EHCI support.
Let's define them globally for MIPS. This also fixes the
compilation of the bcm63xx defconfig against USB.
Wu Zhangjin [Mon, 4 Jan 2010 09:16:52 +0000 (17:16 +0800)]
MIPS: Loongson: Lemote-2F: update defconfig
Changes:
o Serial port related configuration
Disable EARLY_PRINTK, CONFIG_SYS_SUPPORTS_ZBOOT_UART16550
Enable the serial port support as module.
o PM related support
Enable CPUFreq as module, use the external timer(MFGPT) instead of
r4k timer.
Enable Suspend support
Enable Run Time PM support
o Enable SM7XX Video Driver
Disable the buggy 2d acceleration
o Enable CONFIG_OPROFILE as module
o Use GZIP instead of LZMA, which need less decompression time
o Enable more USB devices support
o Enable initrd support(needed by gNewsense)
o Enable more crypto support
Wu Zhangjin [Mon, 4 Jan 2010 09:16:48 +0000 (17:16 +0800)]
MIPS: Loongson: Cleanup of the environment variables
Changes:
o Move bus_clock into prom_init_env()
o Initialize the cpu_clock_freq to the default values for the
correspoding processor revisions if no such environment variable
passed by BIOS/Bootloader.
Wu Zhangjin [Mon, 4 Jan 2010 09:16:46 +0000 (17:16 +0800)]
MIPS: Loongson: Remove the serial port output of compressed kernel support
The compressed kernel support on loongson family machines is stable now,
so, remove the debug information via using SYS_SUPPORTS_ZBOOT instead of
SYS_SUPPORTS_ZBOOT_UART16550. This may reduce the image size and speedup
the booting.
Wu Zhangjin [Mon, 4 Jan 2010 09:16:43 +0000 (17:16 +0800)]
MIPS: Loongson: Lemote-2F: Get the machine type from PMON_VER
Lemote have used the PMON_VER strings to indicate the loongson-2f
machine series:
PMON_VER=LM8089 Lemote 8.9'' netbook
LM8101 Lemote 10.1'' netbook
(The above two netbooks have the same kernel support)
LM6XXX Lemote FuLoong(2F) box series
LM9XXX Lemote LynLoong PC series
Before the machtype is supported by the PMON, we can get the machine
type from the PMON_VER for these machines, this will help the users a
lot.
David Daney [Thu, 7 Jan 2010 19:05:06 +0000 (11:05 -0800)]
Staging: Octeon Ethernet: Use constants from in.h
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
To: gregkh@suse.de
Patchwork: http://patchwork.linux-mips.org/patch/837/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
David Daney [Thu, 7 Jan 2010 19:05:05 +0000 (11:05 -0800)]
Staging: Octeon Ethernet: Enable scatter-gather.
Octeon ethernet hardware can handle NETIF_F_SG, so we enable it.
A gather list of up to six fragments will fit in the SKB's CB
structure, so no extra memory is required. If a SKB has more than six
fragments, we must linearize it.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
To: gregkh@suse.de
Patchwork: http://patchwork.linux-mips.org/patch/838/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
projects / linux-beck.git / log