Simon Horman [Tue, 23 Apr 2013 02:27:15 +0000 (02:27 +0000)]
ARM: shmobile: sh73a0: Use DEFINE_RES_MEM*() everywhere
Convert code to use DEFINE_RES_MEM*() macros.
These macros were already used in this file,
this change makes their usage consistent throughout the file.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This patch enables the use of the generic cpufreq-cpu0 driver on sh73a0.
Providing a regulator, a list of OPPs in DT, combined with a virtual
cpufreq-cpu0 platform device and a clock, attached to it is everything,
the cpufreq-cpu0 driver needs. The first sh73a0 platform, implementing
such CPUFreq support is kzm9g-reference.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
ARM: shmobile: sh73a0: add support for adjusting CPU frequency
On SH73A0 the output of PLL0 is supplied to two dividers, feeding clock to
the CPU core and SGX. Lower CPU frequencies allow the use of lower supply
voltages and thus reduce power consumption.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
ARM: shmobile: Define DT bindings for timer devices
The SH mobile series currently features 3 timer devices in the kernel:
Compare Match Timer (CMT), Timer Unit (TMU) and MTU2. These devices
share register layout characteristics amongst each that enable us to
define common DT bindings for them.
Signed-off-by: Bastian Hecht <hechtb+renesas@gmail.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Magnus Damm [Wed, 27 Mar 2013 15:49:54 +0000 (00:49 +0900)]
ARM: shmobile: r8a7790 IRQC support
Add IRQC interrupt controller support to r8a7790 by
hooking up a single IRQC instances to handle 4 external
IRQ signals. The IRQC controller is tied to SPIs of
the GIC. On r8a7790 the external IRQ pins routing is
handled by the PFC which is excluded from this patch.
Both platform devices and DT devices are added in this
patch. The platform device versions are used to provide
a static interrupt map configuration for board code
written in C.
Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Magnus Damm [Wed, 27 Mar 2013 15:49:44 +0000 (00:49 +0900)]
ARM: shmobile: r8a7790 SCIF support
Add SCIF serial port support to the r8a7790 SoC by
adding platform devices for SCIFA0 -> SCIFA2 as well
as SCIFB0 -> SCIFB2 and SCIF0 -> SCIF1 together with
clock bindings. DT device description is excluded at
this point since such bindings are still under
development.
Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Magnus Damm [Wed, 27 Mar 2013 15:49:34 +0000 (00:49 +0900)]
ARM: shmobile: Initial r8a7790 SoC support
Add initial support for the r8a7790 SoC including:
- Single Cortex-A15 CPU Core
- GIC
- Architecture timer
No static virtual mappings are used, all the components
make use of ioremap(). DT_MACHINE_START is still wrapped
in CONFIG_USE_OF to match other mach-shmobile code.
Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
ARM: shmobile: r8a7779: remove DIV4 clocks and use fixed ratio clock
R-Car H1 has many clocks, and it is possible to read/use clock ratio
of these clocks from FRQMRx as DIV4 clocks.
But, these ratio are fixed value and these are decided
by MD pin status.
This means that we can use fixed ratio clock via MD pin status,
instead of DIV4 clocks.
This patch reads MD pin status, and sets PLLA clock (= root clock),
and used fixed ratio clock for other clocks.
It was tesed on marzen board.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Acked-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
ARM: shmobile: add struct clk_ratio and fixed ratio clock macro
Renesas chip has many clocks inside,
and some of them are using fixed ratio via parent clock.
Current shmobile clock code is using own divX_recalc function
and divX_clk_ops.
This patch can reduce these code
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Acked-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Bastian Hecht [Wed, 27 Mar 2013 13:54:04 +0000 (14:54 +0100)]
ARM: shmobile: r8a7740: Migrate from INTC to GIC
With the added capabilty of the intc_irqpin driver to handle shared
external IRQs, all prerequisites are fulfilled and we are ready to
migrate completely to GIC. This includes the following steps:
- Kconfig: select ARM_GIC and RENESAS_INTC_IRQPIN
- intc-r8a7740: Throw out all legacy INTC code and init the GIC. We need
to mask out all shared IRQs as it is needed by the
shared intc_irqpin driver.
- setup-r8a7740: Add 4 irqpin devices to handle external IRQs and update
all IRQ numbers to point to the GIC SPI.
- board-armadillo: Update all IRQ numbers to point to the GIC SPI.
- pfc-r8a7740: Update all IRQ numbers of the GPIOs to point to the GIC
SPI.
Magnus Damm [Mon, 18 Mar 2013 13:58:18 +0000 (22:58 +0900)]
ARM: shmobile: Disallow PINCTRL without GPIOLIB
Modify mach-shmobile to only select PINCTRL in case of
ARCH_WANT_OPTIONAL_GPIOLIB is set.
This fixes a build error triggered when adding a new SoC
lacking GPIO software support (ARCH_WANT_OPTIONAL_GPIOLIB=n):
CC drivers/tty/vt/keyboard.o
In file included from drivers/pinctrl/core.c:30:0:
include/asm-generic/gpio.h: In function 'gpio_get_value_cansleep':
include/asm-generic/gpio.h:270:2: error: implicit declaration of function '__gpio_get_value'
include/asm-generic/gpio.h: In function 'gpio_set_value_cansleep':
include/asm-generic/gpio.h:276:2: error: implicit declaration of function '__gpio_set_value'
drivers/pinctrl/core.c: In function 'pinctrl_ready_for_gpio_range':
drivers/pinctrl/core.c:297:9: error: implicit declaration of function 'gpio_to_chip'
drivers/pinctrl/core.c:297:27: warning: initialization makes pointer from integer without a cast
drivers/pinctrl/core.c:304:45: error: dereferencing pointer to incomplete type
drivers/pinctrl/core.c:305:26: error: dereferencing pointer to incomplete type
drivers/pinctrl/core.c:305:39: error: dereferencing pointer to incomplete type
make[2]: *** [drivers/pinctrl/core.o] Error 1
make[1]: *** [drivers/pinctrl] Error 2
make[1]: *** Waiting for unfinished jobs....
LD drivers/sh/built-in.o
Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add DT nodes for the 4 irqpin interrupt controllers on sh73a0. We add them
to sh73a0.dtsi, which is also used by configurations, doing all their
device instantiation from board the .c code. We rely on the fact, that
such configurations don't instantiate devices from the device-tree.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add SCIF serial port support to the r8a7778 SoC by
adding platform devices together with clock bindings.
DT device description is excluded at this point since
such bindings are still under development.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Acked-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add initial support for the R8A7778 R-Car M1A SoC.
No static virtual mappings are used, all the components
make use of ioremap().
DT_MACHINE_START is still wrapped
in CONFIG_USE_OF to match other mach-shmobile code.
It is based on v1.0 datasheet
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Acked-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
ARM: shmobile: sh73a0: wait for completion when kicking the clock
To reconfigure clocks, controlled by FRQCRA and FRQCRB, a kick bit has to
be set and to make sure the setting has taken effect, it has to be read
back repeatedly until it is cleared by the hardware. This patch adds the
waiting part, that was missing until now.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Acked-by: Magnus Damm <damm@opensource.se Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Magnus Damm [Tue, 26 Mar 2013 01:34:42 +0000 (10:34 +0900)]
ARM: shmobile: r8a73a4 IRQC support V2
Add IRQC interrupt controller support to r8a73a4 by
hooking up two IRQC instances to handle 58 external
IRQ signals. There IRQC controllers are tied to SPIs
of the GIC. On r8a73a4 exact IRQ pin routing is handled
by the PFC which is excluded from this patch.
Both platform devices and DT devices are added in this
patch. The platform device versions are used to provide
a static interrupt map configuration for board code
written in C.
Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Magnus Damm [Tue, 26 Mar 2013 01:34:33 +0000 (10:34 +0900)]
ARM: shmobile: r8a73a4 SCIF support V3
V3 of SCIF serial port support for the r8a73a4 SoC.
This is done by adding platform devices for SCIFA0
-> SCIFA1 as well as SCIFB0 -> SCIFB3 together with
clock bindings. DT device description is excluded at
this point since such bindings are still under
development.
Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Magnus Damm [Tue, 26 Mar 2013 01:34:24 +0000 (10:34 +0900)]
ARM: shmobile: Initial r8a73a4 SoC support V3
V3 of initial support for the r8a73a4 SoC including:
- Single Cortex-A15 CPU Core
- GIC
- Architecture timer
No static virtual mappings are used, all the components
make use of ioremap(). DT_MACHINE_START is still wrapped
in CONFIG_USE_OF to match other mach-shmobile code.
Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Simon Horman [Tue, 2 Apr 2013 01:55:57 +0000 (10:55 +0900)]
Merge tag 'renesas-intc-external-irq2-for-v3.10' into soc-base
Update for Renesas INTC External IRQ pin driver for v3.10
This adds support for shared interrupt lines to the
Renesas INTC External IRQ pin driver which has already
been queued up for v3.10 (tag renesas-intc-external-irq-for-v3.10).
The patch "irqchip: intc-irqpin: Add support for shared interrupt lines"
in renesas-intc-external-irq2-for-v3.10 is a dependency for
"ARM: shmobile: r8a7740: Migrate from INTC to GIC". That dependency is
the reason for this merge.
Bastian Hecht [Wed, 27 Mar 2013 13:54:03 +0000 (14:54 +0100)]
irqchip: intc-irqpin: Add support for shared interrupt lines
On some hardware we don't have a 1-1 mapping from the external
interrupts coming from INTC to the GIC SPI pins. We can however
share lines to demux incoming IRQs on these SoCs.
This patch enables the intc_irqpin driver to detect requests for shared
interrupt lines and demuxes them properly by querying the INTC INTREQx0A
registers.
If you need multiple shared intc_irqpin device instances, be sure to mask
out all interrupts on the INTC that share the one line before you start
to register them. Else you run into IRQ floods that would be caused by
interrupts for which no handler has been set up yet when the first
intc_irqpin device is registered.
Signed-off-by: Bastian Hecht <hechtb+renesas@gmail.com> Acked-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Magnus Damm [Wed, 27 Feb 2013 08:15:01 +0000 (17:15 +0900)]
irqchip: Renesas IRQC driver
This patch adds a driver for external IRQ pins connected
to the IRQC hardware block on recent SoCs from Renesas.
The IRQC hardware block is used together with more
recent ARM based SoCs using the GIC. As usual the GIC
requires external IRQ trigger setup somewhere else
which in this particular case happens to be IRQC.
This driver implements the glue code needed to configure
IRQ trigger and also handle mask/unmask and demux of
external IRQ pins hooked up from the IRQC to the GIC.
Tested on r8a73a4 but is designed to work with a wide
range of SoCs. The driver requires one GIC SPI per
external IRQ pin to operate. Each driver instance
will handle up to 32 external IRQ pins.
The SoCs using this driver are currently mainly used
together with regular platform devices so this driver
allows configuration via platform data to support things
like static interrupt base address. DT support will
be added incrementally in the not so distant future.
Signed-off-by: Magnus Damm <damm@opensource.se> Tested-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Magnus Damm [Tue, 26 Feb 2013 03:01:18 +0000 (12:01 +0900)]
ARM: shmobile: INTC External IRQ pin driver on r8a7779
Update the r8a7779 IRQ code to make use of the
INTC External IRQ pin driver for external
interrupt pins IRQ0 -> IRQ3.
The r8a7779 SoC can like older SH SoCs configure
to use the IRQ0 -> IRQ3 signals as individual
interrupts or a combined IRL mode.
Without this patch the r8a7779 SoC code does
not fully support external IRQ pins in individual
IRQ mode. The r8a7779 PFC code does not yet have
gpio_to_irq() support so no need to update such
code.
At this point the DT reference implementations
are not covered. In the future such code shall
tie in the INTC External IRQ pin driver via
DT, so this kind of verbose code is not needed
for the long term DT case.
Signed-off-by: Magnus Damm <damm@opensource.se> Tested-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Magnus Damm [Tue, 26 Feb 2013 03:01:09 +0000 (12:01 +0900)]
ARM: shmobile: INTC External IRQ pin driver on sh73a0
Adjust the sh73a0 IRQ code to make use of the
INTC External IRQ pin driver for external
interrupt pins IRQ0 -> IRQ31.
This removes quite a bit of special-case code
in intc-sh73a0.c but the number of lines get
replaced with platform device information in
setup-sh73a0.c. The PFC code is also adjusted
to make gpio_to_irq() return the correct
interrupt number.
At this point the DT reference implementations
are not covered. In the future such code shall
tie in the INTC External IRQ pin driver via
DT, so this kind of verbose code is not needed
for the long term DT case.
Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Magnus Damm [Mon, 18 Feb 2013 14:28:34 +0000 (23:28 +0900)]
irqchip: Renesas INTC External IRQ pin driver
This patch adds a driver for external IRQ pins connected
to the INTC block on recent SoCs from Renesas.
The INTC hardware block usually contains a rather wide
range of features ranging from external IRQ pin handling
to legacy interrupt controller support. On older SoCs
the INTC is used as a general purpose interrupt controller
both for external IRQ pins and on-chip devices.
On more recent ARM based SoCs with Cortex-A9 the main
interrupt controller is the GIC, but IRQ trigger setup
still need to happen in the INTC hardware block.
This driver implements the glue code needed to configure
IRQ trigger and also handle mask/unmask and demux of
external IRQ pins hooked up from the INTC to the GIC.
Tested on sh73a0 and r8a7779. The hardware varies quite
a bit with SoC model, for instance register width and
bitfield widths vary wildly. The driver requires one GIC
SPI per external IRQ pin to operate. Each driver instance
will handle up to 8 external IRQ pins.
The SoCs using this driver are currently mainly used
together with regular platform devices so this driver
allows configuration via platform data to support things
like static interrupt base address. DT support will
be added incrementally in the not so distant future.
Signed-off-by: Magnus Damm <damm@opensource.se> Acked-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Phil Edworthy [Thu, 31 Jan 2013 01:45:01 +0000 (02:45 +0100)]
r8a7779: Add Display Unit clock support
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
[Rename device from to rcarfb to rcar-du] Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
[Manual conflict resolution] Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Simon Horman [Tue, 5 Mar 2013 06:40:42 +0000 (15:40 +0900)]
clocksource: sh_mtu2: Set initcall level to subsys
The reason for this is to ensure that MTU2 is probed earlier
than with its previous initcall level, module init.
This came up as a problem with using CMT as a clock source kzm9g-reference
which does not make use of early timers or devices. In that scenario
initialisation of SDHI and MMCIF both stall on msleep() calls due to the
absence of a initialised clock source.
The purpose of this change is to keep the MTU2 code in sync with the CMT code
which has been modified in a similar manner..
Compile tested only using se7206_defconfig.
I do not believe I have any boards that support the MTU2.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Simon Horman [Tue, 5 Mar 2013 06:40:42 +0000 (15:40 +0900)]
clocksource: em_sti: Set initcall level to subsys
The reason for this is to ensure that STI is probed earlier
than with its previous initcall level, module init.
This came up as a problem with using CMT as a clock source kzm9g-reference
which does not make use of early timers or devices. In that scenario
initialisation of SDHI and MMCIF both stall on msleep() calls due to the
absence of a initialised clock source.
The purpose of this change is to keep the STI code in sync with the CMT code
which has been modified in a similar manner..
Boot tested on: kzm9d.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Simon Horman [Tue, 5 Mar 2013 06:40:42 +0000 (15:40 +0900)]
clocksource: sh_tmu: Set initcall level to subsys
The reason for this is to ensure that TMU is probed earlier
than with its previous initcall level, module init.
This came up as a problem with using CMT as a clock source kzm9g-reference
which does not make use of early timers or devices. In that scenario
initialisation of SDHI and MMCIF both stall on msleep() calls due to the
absence of a initialised clock source.
The purpose of this change is to keep the TMU code in sync with the CMT code
which has been modified in a similar manner..
Boot tested on: mackerel.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Simon Horman [Tue, 5 Mar 2013 06:40:42 +0000 (15:40 +0900)]
clocksource: sh_cmt: Set initcall level to subsys
The reason for this is to ensure that CMT is probed earlier
than with its previous initcall level, module init.
This came up as a problem with using kzm9g-reference which does
not make use of early timers or devices. In that scenario initialisation
of SDHI and MMCIF both stall on msleep() calls due to the absence
of a initialised clock source.
Boot tested on: armadillo800eva, mackerel and kzm9g
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Magnus Damm [Fri, 14 Dec 2012 05:54:28 +0000 (14:54 +0900)]
clocksource: sh_cmt: Add control register callbacks
This patch adds control register callbacks for the CMT
driver. At this point only 16-bit access is supported
but in the future this will be updated to allow 32-bit
access as well.
Signed-off-by: Magnus Damm <damm@opensource.se> Acked-by: John Stultz <john.stultz@linaro.org> Tested-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Magnus Damm [Fri, 14 Dec 2012 05:54:19 +0000 (14:54 +0900)]
clocksource: sh_cmt: CMCNT and CMCOR register access update
Break out the CMCNT and CMCOR register access code
into separate 16-bit and 32-bit functions that are
hooked into callbacks at init time. This reduces
the amount of software calculations happening at
runtime.
Signed-off-by: Magnus Damm <damm@opensource.se> Acked-by: John Stultz <john.stultz@linaro.org> Tested-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Magnus Damm [Fri, 14 Dec 2012 05:54:10 +0000 (14:54 +0900)]
clocksource: sh_cmt: CMSTR and CMCSR register access update
Update hardware register access code for CMSTR and CMCSR
from using sh_cmt_read() and sh_cmt_write() to make use
of 16-bit register access functions such as sh_cmt_read16()
and sh_cmt_write16(). Also update sh_cmt_read() and
sh_cmt_write() now when the special cases are gone.
This patch moves us one step closer to the goal of separating
counter register access functions from control control register
functions.
Signed-off-by: Magnus Damm <damm@opensource.se> Acked-by: John Stultz <john.stultz@linaro.org> Tested-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Introduce sh_cmt_read_cmstr/cmcsr/cmcnt() and
sh_cmt_write_cmstr/cmcsr/cmcnt/cmcor() to in the
future allow us to split counter registers from
control registers and reduce code complexity by
removing sh_cmt_read() and sh_cmt_write().
Signed-off-by: Magnus Damm <damm@opensource.se> Acked-by: John Stultz <john.stultz@linaro.org> Tested-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Sergei Shtylyov [Thu, 7 Mar 2013 23:31:03 +0000 (02:31 +0300)]
ARM: shmobile: R8A7779: use gic_iid() in SATA IRQ resource
Commit "ARM: shmobile: r8a7779: use gic_iid macro" switched R8A7779 platform
devices to using gic_iid() macro instead of gic_spi() but commit "ARM: mach-
shmobile: r8a7779: add SATA support" added another use of gic_spi(). Convert
the SATA IRQ resource to using gic_iid().
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Vladimir Barinov [Wed, 27 Feb 2013 20:39:14 +0000 (23:39 +0300)]
ARM: mach-shmobile: r8a7779: add SATA support
Add SATA clock for r8a7779 SoC (for both device tree and usual cases).
Register SATA controller as a "late" platform device on r8a7779 SoC.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Vladimir Barinov [Wed, 27 Feb 2013 20:34:36 +0000 (23:34 +0300)]
ARM: mach-shmobile: r8a7779: SATA DT configuration
Allow configuration of the r8a7779 SoC SATA controller using a flattened device
tree.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
rcar thermal driver doesn't support IRQ on r8a7779 chip
since it is using old design IRQ.
R-Car/R-Mobile next generation chips are using new design IRQ,
and rcar thermal driver is supporting these.
This patch adds rcar_thermal DT support for r8a7779 without IRQ.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
"ARM: shmobile: add gic_iid macro for ICCIAR / interrupt ID"
enabled to use gic_iid macro.
This patch exchange current GIC interrupt setting
from gic_spi() to gic_iid()
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
[ horms+renesas@verge.net.au: Updated git commit id in changelog ] Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
ARM: shmobile: add gic_iid macro for ICCIAR / interrupt ID
R-Car H1 datasheet GIC number is indicating
GIC ICCIAR / interrupt ID number, not SPI number,
but current marzen board code is using gic_spi() with
un-understandable calculation.
This patch adds new gic_iid() macro which means
ICCIAR / interrupt ID, and used the number
currently written on datasheet.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
[ horms+renesas@verge.net.au: Split board-marzen.c portion into a separate patch ] Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Magnus Damm [Mon, 18 Feb 2013 13:48:03 +0000 (22:48 +0900)]
ARM: shmobile: Remove unused hotplug.c
Each CPU Hotplug implementation for mach-shmobile
is now self-contained, so this change removes unused
helper code in hotplug.c. The two CPU Hotplug capable
SoCs sh73a0 and r8a7779 remain unchanged.
Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Magnus Damm [Mon, 18 Feb 2013 13:47:54 +0000 (22:47 +0900)]
ARM: shmobile: Rearrange r8a7779 cpu hotplug code
Update the r8a7779 SMP code and CPU Hotplug in particular
to follow the same style as sh73a0. This means dropping
__maybe_unused for #ifdef CONFIG_HOTPLUG_CPU.
Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Magnus Damm [Mon, 18 Feb 2013 13:47:44 +0000 (22:47 +0900)]
ARM: shmobile: Use sh73a0-specific cpu disable code
Convert the sh73a0 CPU Hotplug code to use a local
implementation of ->cpu_disable(). With this change
in place the sh73a0 SMP code does no longer depend
on hotplug.c.
Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Magnus Damm [Mon, 18 Feb 2013 13:47:35 +0000 (22:47 +0900)]
ARM: shmobile: Update r8a7779 to use scu_power_mode()
Update the SMP code for R8A7779 to make use of the
shared SCU function scu_power_mode() together with
the early setup code in shmobile_secondary_vector_scu.
With this patch in place the secondary CPUs modify the
SCU setting during early boot instead of letting other
CPUs deal with the coherency setting before boot. In
other words, we used to setup coherency before boot
in r8a7779_boot_secondary() but that bit is now instead
handled by the code in shmobile_secondary_vector_scu.
Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Magnus Damm [Mon, 18 Feb 2013 13:47:25 +0000 (22:47 +0900)]
ARM: shmobile: Update r8a7779 to check SCU for hotplug
Update the r8a7779 CPU Hotplug code to use SCU PSR
to wait for the target CPU core. Previously the
shared code in hotplug.c was used to let cpu_kill()
wait for cpu_die(). With this change in place the
r8a7779 SMP code does not depend on hotplug.c anymore.
Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Rework the IOMEM() usage for the SCU base address in the
case of sh73a0. Removes recently introduced build warnings:
arch/arm/mach-shmobile/smp-sh73a0.c:45:15: warning: initialization makes integer from pointer without a cast [enabled by default]
arch/arm/mach-shmobile/smp-sh73a0.c:45:15: warning: (near initialization for 'twd_local_timer.res[0].start') [enabled by default]
arch/arm/mach-shmobile/smp-sh73a0.c:45:15: warning: initialization makes integer from pointer without a cast [enabled by default]
/arch/arm/mach-shmobile/smp-sh73a0.c:45:15: warning: (near initialization for 'twd_local_timer.res[0].end') [enabled by default]
Reported-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Magnus Damm [Wed, 13 Feb 2013 13:47:27 +0000 (22:47 +0900)]
ARM: shmobile: Update EMEV2 to use scu_power_mode()
Update the SMP code for EMEV2 to make use of the
shared SCU function scu_power_mode() together with
the early setup code in shmobile_secondary_vector_scu.
With this patch in place the secondary CPUs modify the
SCU setting during early boot instead of letting other
CPUs deal with the coherency setting before boot. In
other words, we used to setup coherency before boot
in emev2_boot_secondary() but that bit is now instead
handled by the code in shmobile_secondary_vector_scu.
Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Magnus Damm [Wed, 13 Feb 2013 13:47:17 +0000 (22:47 +0900)]
ARM: shmobile: Common shmobile_scu_base in headsmp-scu.S
Update the code in headsmp-scu.S to use a global
shmobile_scu_base variable both for convenient SCU
base address storage and for the early SCU setup
code in shmobile_secondary_vector_scu.
With this patch applied r8a7779, sh73a0 and EMEV2
all make use of the global shmobile_scu_base
variable. However only sh73a0 makes use of the SCU
bring up code in shmobile_secondary_vector_scu.
Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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