Tony Lin [Fri, 10 Feb 2012 09:06:21 +0000 (17:06 +0800)]
ENGR00174232 [mx6q perfmon]PDM No. TKT055916: remove workaround for TO1.1
remove the workaround
For TO1.0: bit16 of GPR11 must be set to enable perfmon
For TO1.1 and later: bit0 of GPR11 is enable bit for perfmon.
set 1/0 to enable/disable perfmon
Xinyu Chen [Fri, 10 Feb 2012 07:54:41 +0000 (15:54 +0800)]
ENGR00174127 mag3110: merge the mag3110 sensor driver
Merge mag3110 drivers from sensor team.
The drivers are updated with chip position configure
in driver, export set delay interface to userspace and
use polling mode instead of interrupt mode.
Merge mma8451 drivers from sensor team.
The drivers are updated with chip position configure
in driver, export enable and position interface to userspace.
Zhang Jiejing [Wed, 11 Jan 2012 06:20:15 +0000 (14:20 +0800)]
ENGR00173857 MX6Q: add 600M work point
Add a 600M work point for better suit for cpufreq driver.
For current MX6Q clock tree, the most near 600M working point
is 624M, so we use 624M as 600M working point.
We found we have 200/400/800/1G working point is not very
good for cpufreq adjustment, since we don't have a uniform
working point distribution, since the interactive governor
is using cpu usage to adjust frequency, eg, 60% CPU, going
to 600M working point, if above a threshold (%85 default)
will going to max frequency directly.
From the [sheet] , you can see in game case, it will have much
chance in 400M working point, between 400M and 800M working
point, there is a gap, so the 400M will be most used frequency.
we add 600 WP to fill this gap, and make game case have
better experience.
Richard Zhu [Wed, 8 Feb 2012 06:58:41 +0000 (14:58 +0800)]
ENGR00174033-2 MX6 PCIE: add pcie RC driver
Add PCIE RC driver on MX6 platforms.
Based on iwl4965agn pcie wifi device, verified the following
features.
* Link up is stable
* map the CFG, IO and MEM spaces, and CFG/MEM spaces can accessed
Richard Zhu [Wed, 8 Feb 2012 06:57:56 +0000 (14:57 +0800)]
ENGR00174033-1 MX6 PCIE: add pcie RC driver
Add PCIE RC driver on MX6 platforms.
Based on iwl4965agn pcie wifi device, verified the following
features.
* Link up is stable
* map the CFG, IO and MEM spaces, and CFG/MEM spaces can be accessed
Peter Chen [Thu, 9 Feb 2012 09:38:59 +0000 (17:38 +0800)]
ENGR00174128-1 Revert "Remove the discharge for VBUS and DP-1"
As dp/dm is floating with no usb cable and switch host mode to
device mode situation, it do needs this discharge dp patch
But, discharge vbus doesn't be needed at suspend_irq, so
keep it removing.
Nancy Chen [Thu, 9 Feb 2012 16:27:07 +0000 (10:27 -0600)]
ENGR00174094 i.MX6DL: Change CPU voltages to 1V
Change CPU voltages (0.95V and 0.85V) to 1V
CPU voltage should be above 1.0V for all CPU frequency
since L1 Cache power is connected to VDDARM internally.
Jason Liu [Thu, 9 Feb 2012 06:09:58 +0000 (14:09 +0800)]
ENGR00174152 i.mx6/clock: set ddr clock parent to pll2_mfd_400M
on i.mx6dl, DDR clock is sourcing from pll2_mfd_400M, so, we need
set DDR/periph_clk parent to pll2_mfd_400M during clock init, which
will setup the clock usecount of pll2_mfd_400M correctly, otherwise,
when all the child device with clock source from pll2_mfd_400M turn
off, the pll2_mfd_400M will turns off automaticly, which will cause
system hang due to DDR clock is off when code is runing on it.
Peter Chen [Thu, 9 Feb 2012 09:07:44 +0000 (17:07 +0800)]
ENGR00174124: Revert "[USB Host]change the default wakeup value of RH"
This patch creates two bugs at current i.mx usb framework.
- The high speed device can't be recognized at the first time.
- The usb device can't be recognized after system resume with
usb vbus.
The reason why it creates bugs that it changes (auto)suspend/resume
process for usb core.
Tony LIU [Wed, 8 Feb 2012 07:33:56 +0000 (15:33 +0800)]
ENGR00174037-1 Add HSIC suspend/resume feature
MSL part
- For HSIC, not connect nor disconnect, then WKCN,
WKDC must not be set during suspend
- For HSIC, must set bit 21 in host control registry
after device connected to host controller
- USB PHY 480M clock output must turn on to avoid about
10ms delay before sending out resume signal
- HW_ANA_MISC clkgate delay must be set to 2 or 3 to
avoid 24M OSCI not stable issue
Signed-off-by: Tony LIU <junjie.liu@freescale.com>
Alan Tull [Wed, 8 Feb 2012 22:40:31 +0000 (16:40 -0600)]
ENGR00172342-2 EDID parse audio data blocks
Add functionality to parse Audio Data Blocks from EDID data to
find out what modes of LPCM are suppored by the HDMI sink device.
The parsed settings are saved in the hdmi mfd. The HDMI audio driver
will check the settings when the audio stream is opened and will
then apply appropriate constraints.
If we are unable to read from the EDID, then we default to supporting
Basic Audio as defined by the HDMI specification (stereo, 16 bit,
32KHz, 44.1KHz, 48KHz PCM).
Alan Tull [Thu, 26 Jan 2012 17:37:01 +0000 (11:37 -0600)]
ENGR00172342-1 EDID parse audio data blocks
Add functionality to parse Audio Data Blocks from EDID data to
find out what modes of LPCM are suppored by the HDMI sink device.
The parsed settings are saved in the hdmi mfd. The HDMI audio driver
will check the settings when the audio stream is opened and will
then apply appropriate constraints.
If we are unable to read from the EDID, then we default to supporting
Basic Audio as defined by the HDMI specification (stereo, 16 bit,
32KHz, 44.1KHz, 48KHz PCM).
Wayne Zou [Thu, 2 Feb 2012 07:10:35 +0000 (15:10 +0800)]
ENGR00171353 MIPI_DSI: mipi display blank and unblank fail fixed
mipi display blank and unblank fail on HW board: MX6Q_ARM2 1G SN 0112
The host processor sends PCLK, HS and VS information to display modules
two frames before sleep-out command is sent.
Sandor Yu [Wed, 8 Feb 2012 05:45:18 +0000 (13:45 +0800)]
ENGR00173962 Added HDMI enable function
Whenever IPU clock change or gating, the HDMI PHY should reset or config again,
otherwise the HDMI PHY will not work.
It is the root cause for Ubuntu can't show GUI to HDMI device when bootup
and GPU application tutorial4_es20 no output to HDMI device.
Added enable function in mxcfb_set_par() to fix aboved two issue.
Added HDMI initialization check, only one HDMI instanse supported.
After over 1100 (!) patches we have now reached a state where I would
like to start discussing about pushing the driver to the wireless
trees and replacing the staging driver.
The driver is now a lot smaller and looks like a proper Linux driver.
The size of the driver (measured with simple wc -l) dropped from 49
kLOC to 18 kLOC and the number of the .c and .h files dropped from 107
to 22. Most importantly the number of subdirectories reduced from 26
to zero :)
There are two remaining checkpatch warnings in the driver which we
decided to omit for now:
drivers/net/wireless/ath/ath6kl/debug.c:31:
WARNING: printk() should include KERN_ facility level
drivers/net/wireless/ath/ath6kl/sdio.c:527:
WARNING: msleep < 20ms can sleep for up to 20ms;
see Documentation/timers/timers-howto.txt
The driver has endian annotations for all the hardware specific
structures and there are no sparse errors. Unfortunately I don't have
any big endian hardware to test that right now.
We have been testing the driver both on x86 and arm platforms. The
code is also compiled with sparc and parisc cross compilers.
Notable missing features compared to the current staging driver are:
o HCI over SDIO support
o nl80211 testmode
o firmware logging
o suspend support
Testmode, firmware logging and suspend support will be added soon. HCI
over SDIO support will be more difficult as the HCI driver needs to
share code with the wifi driver. This is something we need to research
more.
Also I want to point out the changes I did for signed endian support.
As I wasn't able to find any support for signed endian annotations I
decided to follow what NTFS has done and added my own. Grep for sle16
and sle32, especially from wmi.h.
Various people have been working on the cleanup, the hall of
fame based on number of patches is:
543 Vasanthakumar Thiagarajan
403 Raja Mani
252 Kalle Valo
16 Vivek Natarajan
12 Suraj Sumangala
3 Joe Perches
2 Jouni Malinen
Signed-off-by: Vasanthakumar Thiagarajan <vthiagar@qca.qualcomm.com> Signed-off-by: Raja Mani <rmani@qca.qualcomm.com> Signed-off-by: Vivek Natarajan <nataraja@qca.qualcomm.com> Signed-off-by: Suraj Sumangala <surajs@qca.qualcomm.com> Signed-off-by: Joe Perches <joe@perches.com> Signed-off-by: Jouni Malinen <jouni@qca.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
Fugang Duan [Wed, 8 Feb 2012 03:39:25 +0000 (11:39 +0800)]
ENGR00172274-02 - IEEE-1588: rework ts_clk in MX6 ARIK CPU board.
Default use RMII 50MHz clock for ts_clk.
Test result:
Enet work fine at 100/1000Mbps in TO1.1 and Rigel.
IEEE 1588 timestamp is convergent for 25M & 50M & 100MHz
timestamp clock.
Fugang Duan [Wed, 8 Feb 2012 03:26:58 +0000 (11:26 +0800)]
ENGR00172274-01 - [MX6]: rework IEEE-1588 ts_clk in MX6Q ARIK CPU board.
- Fix GPIO_16 IOMUX config.
- Config GPIO_16 pad to ENET_ANATOP_ETHERNET_REF_OUT.
- IEEE-1588 ts_clk, S/PDIF in and i2c3 are mutually exclusive,
because all of them use GPIO_16, so it only for one function
work at a moment.
- Test result:
Enet work fine at 100/1000Mbps in TO1.1.
IEEE 1588 timestamp is convergent.
Jason Liu [Tue, 7 Feb 2012 06:00:21 +0000 (14:00 +0800)]
ENGR00173869-3: i.mx6: add the cpu_is_mx6dl() support
In order to support one image for i.mx6q and i.mx6dl, we introduce
the below functions by diff the value reading from ANATOP ID register.
cpu_is_mx6q() and cpu_is_mx6dl()
The layout for the register defines:
Major Minor
i.MX6Q1.1: 6300 01
i.MX6Q1.0: 6300 00
i.MX6DL1.0: 6100 00
For the common bits shared across all i.mx6 ports, we can use:
cpu_is_mx6() for it.
Huang Shijie [Wed, 18 Jan 2012 02:51:40 +0000 (10:51 +0800)]
ENGR00173731-3 mxs-dma : rewrite the last parameter of mxs_dma_prep_slave_sg()
[1] Background :
The GPMI does ECC read page operation with a DMA chain consist of three DMA
Command Structures. The middle one of the chain is used to enable the BCH,
and read out the NAND page.
The WAIT4END(wait for command end) is a comunication signal between
the GPMI and MXS-DMA.
[2] The current DMA code sets the WAIT4END bit at the last one, such as:
[3] But in the new GPMI version (used in MX50/MX60), the WAIT4END bit should
be set not only at the last DMA Command Structure,
but also at the middle one, such as:
+-----+ +-----+ +-----+
| cmd | ------------> | cmd | ------------------> | cmd |
+-----+ +-----+ +-----+
^ ^
| |
| |
set WAIT4END here too set WAIT4END here
If we do not set WAIT4END, the BCH maybe stalls in "ECC reading page" state.
In the next ECC write page operation, a DMA-timeout occurs.
This has been catched in the MX6Q board.
[4] In order to fix the bug, rewrite the last parameter of
mxs_dma_prep_slave_sg(), and use the dma_ctrl_flags:
---------------------------------------------------------
DMA_PREP_INTERRUPT : append a new DMA Command Structrue.
DMA_CTRL_ACK : set the WAIT4END bit for this DMA Command Structure.
---------------------------------------------------------
[5] changes to the relative drivers:
For gpmi-nand driver: use the new flags.
Huang Shijie [Mon, 6 Feb 2012 02:47:02 +0000 (10:47 +0800)]
ENGR00173731-1 mxs-dma : rename the dma.h for mxs-dma
Move the header to a more common place.
The mxs dma engine is not only used in mx23/mx28, but also used
in mx50/mx6q. It will also be used in the future chips.
Ryan QIAN [Tue, 31 Jan 2012 03:01:52 +0000 (11:01 +0800)]
ENGR00173288-02 merge "[MX6Q]add SDHC3.0 support on uSDHC controller"
ENGR152547-03 [MX6Q]add SDHC3.0 support on uSDHC controller
add voltage switch function due to SDHC3.0 spec requirement
add tuning function due to SDHC3.0 spec requirement
extend some functions to support SDR50 & SDR104 speed mode
- adjust the sequence of current_limit and bus_speed_mode
- add FSL specific tuning procedure
Ryan QIAN [Tue, 31 Jan 2012 02:58:38 +0000 (10:58 +0800)]
ENGR00173288-01 merge "[MX6Q]add SDHC3.0 support on uSDHC controller"
ENGR152547-03 [MX6Q]add SDHC3.0 support on uSDHC controller
add voltage switch function due to SDHC3.0 spec requirement
add tuning function due to SDHC3.0 spec requirement
extend some functions to support SDR50 & SDR104 speed mode
- add support for SD3.0.
- add workaround for accessing non-exist registers on FSL SDHC.
Peter Chen [Fri, 3 Feb 2012 06:31:35 +0000 (14:31 +0800)]
ENGR00173639 mx6q: clock: PLL3's power can be off at runtime at TO1.1
It is the fix for Design PDM TKT064178, IC has already verified it,
and no more power consumption for setting/clear this bit.
With this bit, the power of pll3 can be off even the power bit for pll3
is on. In order to support USB wakeup, the power bit for pll3 should
be always on, and the power of pll3 is controller by USB hardware and
this new added bit at runtime.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
ENGR00173586-2 [MX6] Add support to source GPT from 24MHz
On MX6Q TO1.1, MX6DL/S and MX6Solo, GPT can be sourced
from a constant source (better for frequency scaling).
Currently we set the GPT clock to 3MHz (24MHz div by 8).
ENGR00173586-1 [MX6] Add support to source GPT from 24MHz
On MX6Q TO1.1, MX6DL/S and MX6Solo, GPT can be sourced
from a constant source (better for frequency scaling).
Currently we set the GPT clock to 3MHz (24MHz div by 8).
Alan Tull [Thu, 26 Jan 2012 10:37:10 +0000 (04:37 -0600)]
ENGR00171536 HDMI handle mmapped audio buffers
The ALSA userspace requires mmapped buffer access to support sample
rate conversion.
Our hardware requires the driver to add frame information to the pcm
data. For non-mmap access, the snd_pcm_ops' copy routine will do it.
For mmap access, we have to do it in the isr. This is not ideal, but
it will work.
Anson Huang [Thu, 2 Feb 2012 10:05:40 +0000 (18:05 +0800)]
ENGR00173645 [MX6]Implement low power actions into DSM
1. Need to follow right programming model for wb_per_at_lpm
,zeroed wb_count each time exit from DSM and set it before
entering DSM;
2. For TO1.1, need to set fet_odrive for better power gate.
Anson Huang [Thu, 19 Jan 2012 09:07:02 +0000 (17:07 +0800)]
ENGR00172391 [MX6]Remove unnecessary workaround of wdog for TO1.1
On TO1.1, there is no such issue now, so remove the workaround,
as this is a very very low possibility to reproduce this issue, and the
workaround has very complicated logic, it is hard and non-necessary
to add SOC version check, so just remove it.
ENGR00173585: MX6: Added WAIT mode workaround for MX6Q TO1.1
There is small window where an interrupt can occur when the SOC is
in the process of entering WAIT mode. The ARM core responds to this
interrupt and can access the internal memories when their clocks are
disabled.
To avoid crashes generated due to this, WFI code should be executed
from non-cacheable IRAM and enough delay should added after the
WFI so that accesses to memories are prevented.
This workaround assumes that all interrupts are routed to CPU0 only.
This workaround is applicable to iMX6DL/Solo also.
Peter Chen [Tue, 31 Jan 2012 05:34:20 +0000 (13:34 +0800)]
ENGR00173378-1 usb: device: Change judgement condition for resume occurrence
At former code, it uses portsc.fpr to indicate if the host sends
resume signal to device, but it has some limitations that if the code
can't be executed before the resume signal finishes, the portsc.fpr
will be cleared automatically.
Now, it uses usbsts.pci to judge host resume signal, this bit
will not be cleared before the non-wakeup interrupt handler is called,
and the wakeup code is executed before non-wakeup interrupt handler.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
Encapsulate last MTD partition parser argument into a separate
structure. Currently it holds only 'origin' field for RedBoot parser,
but will be extended in future to contain at least device_node for OF
devices.
Lots (nearly all) mtd drivers contain nearly the similar code that
calls parse_mtd_partitions, provides some platform-default values, if
parsing fails, and registers mtd device.
This is an aim to provide single implementation of this scenario:
mtd_device_parse_register() which will handle all this parsing and
defaults.
Richard Zhao [Tue, 15 Nov 2011 06:47:56 +0000 (14:47 +0800)]
clk: add helper functions clk_prepare_enable and clk_disable_unprepare
It's for migrating to generic clk framework API.
The helper functions help cases clk_enable/clk_disable is used
in non-atomic context.
For example, Call clk_enable in probe and clk_disable in remove.
Signed-off-by: Richard Zhao <richard.zhao@linaro.org> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Cc: Russell King <linux@arm.linux.org.uk> Acked-by: Marek Vasut <marek.vasut@gmail.com>
Russell King [Thu, 22 Sep 2011 10:30:50 +0000 (11:30 +0100)]
clk: provide prepare/unprepare functions
As discussed previously, there's the need on some platforms to run some
parts of clk_enable() in contexts which can schedule. The solution
which was agreed upon was to provide clk_prepare() and clk_unprepare()
to contain this parts, while clk_enable() and clk_disable() perform
the atomic part.
This patch provides a common definition for clk_prepare() and
clk_unprepare() in linux/clk.h, and provides an upgrade path for
existing implementation and drivers: drivers can start using
clk_prepare() and clk_unprepare() once this patch is merged without
having to wait for platform support. Platforms can then start to
provide these additional functions.
Eventually, HAVE_CLK_PREPARE will be removed from the kernel, and
everyone will have to provide these new APIs.
Acked-by: Saravana Kannan <skannan@codeaurora.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Lothar Waßmann [Thu, 8 Dec 2011 08:15:44 +0000 (09:15 +0100)]
dma: mxs-dma: Don't use CLKGATE bits in CTRL0 to disable DMA channels
This is how the original Freescale code (unintentionally) worked,
because the code path which would have asserted the CLKGATE bit was
never actually reached in their code.
This fixes the nefarious "DMA timout" bug when multiple DMA channels
(e.g. GPMI NAND and MMC) are used at the same time.
If a better fix for this problem should be found, the clkgate handling
could be reinstated.
See http://lists.infradead.org/pipermail/linux-arm-kernel/2011-September/065228.html
Also reverse the order of mxs_dma_disable_chan() and
mxs_dma_reset_chan() in mxs_dma_control() because mxs_dma_reset_chan()
can only work when the DMA channel is enabled.
Lothar Waßmann [Thu, 8 Dec 2011 08:15:42 +0000 (09:15 +0100)]
dma: mxs-dma: Always leave mxs_dma_init() with the clock disabled.
There is no need to have the clock enabled all the time the driver is
loaded.
It will be enabled anyway in mxs_dma_alloc_chan_resources() when a
channel is actually going to be used.
Other files using dma.h may fail to compile as follows:
In file included from sound/soc/mxs/mxs-pcm.h:22,
from sound/soc/mxs/mxs-saif.h:112,
from sound/soc/mxs/mxs-sgtl5000.c:34:
arch/arm/mach-mxs/include/mach/dma.h:16: warning: 'struct dma_chan' declared inside parameter list
arch/arm/mach-mxs/include/mach/dma.h:16: warning: its scope is only this definition or declaration, which is probably not what you want
arch/arm/mach-mxs/include/mach/dma.h: In function 'mxs_dma_is_apbh':
arch/arm/mach-mxs/include/mach/dma.h:18: error: dereferencing pointer to incomplete type
arch/arm/mach-mxs/include/mach/dma.h: At top level:
arch/arm/mach-mxs/include/mach/dma.h:21: warning: 'struct dma_chan' declared inside parameter list
arch/arm/mach-mxs/include/mach/dma.h: In function 'mxs_dma_is_apbx':
arch/arm/mach-mxs/include/mach/dma.h:23: error: dereferencing pointer to incomplete type
make[3]: *** [sound/soc/mxs/mxs-sgtl5000.o] Error 1
make[2]: *** [sound/soc/mxs] Error 2
make[1]: *** [sound/soc] Error 2
make: *** [sound] Error 2
It seems it's better for dma.h to include dmaengine.h himself.
Shawn Guo [Tue, 13 Dec 2011 15:48:03 +0000 (23:48 +0800)]
dmaengine: add DMA_TRANS_NONE to dma_transfer_direction
Before dma_transfer_direction was introduced to replace
dma_data_direction, some dmaengine device uses DMA_NONE of
dma_data_direction for some talk with its client drivers.
The mxs-dma and its clients mxs-mmc and gpmi-nand are such case.
This patch adds DMA_TRANS_NONE to dma_transfer_direction and
migrate the DMA_NONE use in mxs-dma to it.
It also fixes the compile warning below.
CC drivers/dma/mxs-dma.o
drivers/dma/mxs-dma.c: In function ‘mxs_dma_prep_slave_sg’:
drivers/dma/mxs-dma.c:420:16: warning: comparison between ‘enum dma_transfer_direction’ and ‘enum dma_data_direction’
Paul Gortmaker [Fri, 29 Jul 2011 06:55:11 +0000 (16:55 +1000)]
linux/dmaengine.h: fix implicit use of bitmap.h and asm/page.h
The implicit presence of module.h and all its sub-includes was
masking these implicit header usages:
include/linux/dmaengine.h:684: warning: 'struct page' declared inside parameter list
include/linux/dmaengine.h:684: warning: its scope is only this definition or declaration, which is probably not what you want
include/linux/dmaengine.h:687: warning: 'struct page' declared inside parameter list
include/linux/dmaengine.h:736:2: error: implicit declaration of function 'bitmap_zero'
With input from Stephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Vinod Koul [Thu, 13 Oct 2011 09:45:27 +0000 (15:15 +0530)]
dmaengine: add new enum dma_transfer_direction
This new enum removes usage of dma_data_direction for dma direction. The new
enum cleans tells the DMA direction and mode
This further paves way for merging the dmaengine _prep operations and also for
interleaved dma
Suggested-by: Jassi Brar <jaswinder.singh@linaro.org> Reviewed-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
For clients which require a single slave transfer and dont want to be bothered
about the scatterlist api, this helper gives simple API for this transfer and
creates single scatterlist for DMA API
projects / karo-tx-linux.git / log