Pull the parameter checking from drm_primary_helper_update() out into
its own function; drivers that provide their own setplane()
implementations rather than using the helper may still want to share
this parameter checking logic.
A few of the checks here were also updated based on suggestions by
Ville Syrjälä.
v3:
- s/primary_helper/plane_helper/ --- this checking logic may be useful
for other types of planes as well.
- Fix visibility check (need to dereference visibility pointer)
v2:
- Pass src/dest/clip rects and min/max scaling down to helper to avoid
duplication of effort between helper and drivers (suggested by
Ville).
- Allow caller to specify whether the primary plane should be
updatable while the crtc is disabled.
Cc: dri-devel@lists.freedesktop.org Reviewed-by: Chon Ming Lee <chon.ming.lee@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Acked-by: Dave Airlie <airlied@gmail.com>
[danvet: Include header properly and fixup declaration mismatch to
make this compile.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Matt Roper [Thu, 29 May 2014 15:06:51 +0000 (08:06 -0700)]
drm: Check CRTC compatibility in setplane
The DRM core setplane code should check that the plane is usable on the
specified CRTC before calling into the driver.
Prior to this patch, a plane's possible_crtcs field was purely
informational for userspace and was never actually verified at the
kernel level (aside from the primary plane helper).
Cc: dri-devel@lists.freedesktop.org Reviewed-by: Chon Ming Lee <chon.ming.lee@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Acked-by: Dave Airlie <airlied@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Ville Syrjälä [Wed, 28 May 2014 16:12:13 +0000 (19:12 +0300)]
drm/i915: Don't WARN about ring idle bit on gen2
Gen2 doesn't have the ring idle/stop bits in the SCPD/MI_MODE register,
so don't go spewing warnings about the state of those bits.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Chris Wilson [Wed, 28 May 2014 15:16:41 +0000 (16:16 +0100)]
drm/i915: Silence the WARN if the user tries to GTT mmap an incoherent object
If the user tries to mmap through the GTT an object that is marked as
snooped, we report an error rather than allow the GPU to hang the
machine. The choice of EINVAL, however, was unfortunate as we turn that
into a WARN rather than a quiet SIGBUS.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Ville Syrjälä [Tue, 25 Feb 2014 13:13:41 +0000 (15:13 +0200)]
drm/i915: Move the C3 LP write bit setup to gen3_init_clock_gating() for KMS
Move the MI_ARB_STATE MI_ARB_C3_LP_WRITE_ENABLE setup to
gen3_init_clock_gating() from i915_gem_load() when KMS is enabled. Leave
it in i915_gem_load() for the UMS case, but add an explcit check, just
to make it easier to spot it when we eventually rip out UMS support.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Ville Syrjälä [Tue, 25 Feb 2014 13:13:40 +0000 (15:13 +0200)]
drm/i915: Enable interrupt-based AGPBUSY# enable on 85x
85x also has a similar AGPBUSY# bit as gen3. Enable it to make
sure vblank interrupts don't get dealyed during C3 state.
There's also another bit which controls whether AGPBUSY# is asserted
based on pending cacheable cycles and interrupts, or just based on
pending commands in the ring and interrupts. Select the cacheable
cycles mode since that seems to be the new way of doing things in
85x, and it does give slightly better C3 residency numbers with
glxgears running.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Ville Syrjälä [Tue, 25 Feb 2014 13:13:39 +0000 (15:13 +0200)]
drm/i915: Flip the sense of AGPBUSY_DIS bit
My Gen3 Bspec lists the AGPBUSY# bit in INSTPM as an enable bit rather
than a disable bit. Our code has the opposite idea. Make the code match
the spec.
Might fix some gen3 C3 related interrupt delivery problems. Untested
due to lack of hardware.
v2: call it AGPBUSY_INT_EN to make it clearer it has to do with interrupts
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Ville Syrjälä [Tue, 25 Feb 2014 13:13:38 +0000 (15:13 +0200)]
drm/i915: Set AGPBUSY# bit in init_clock_gating
I don't see why we wouldn't want interrupts to wake up the CPU from C3
always, so just set the AGPBUSY# bit in gen3_init_clock_gating().
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Jesse Barnes [Fri, 23 May 2014 20:16:40 +0000 (13:16 -0700)]
drm/i915/vlv: assert and de-assert sideband reset at boot and resume v3
This is a bit like the CMN reset de-assert we do in DPIO_CTL, except
that it resets the whole common lane section of the PHY. This is
required on machines where the BIOS doesn't do this for us on boot or
resume to properly re-calibrate and get the PHY ready to transmit data.
Without this patch, such machines won't resume correctly much of the time,
with the symptom being a 'port ready' timeout and/or a link training
failure.
Note that simply asserting reset at suspend and de-asserting at resume
is not sufficient, nor is simply de-asserting at boot. Both of these
cases have been tested and have still been found to have failures on
some configurations.
v2: extract simpler set_power_well function for use in reset_dpio (Imre)
move to reset_dpio (Daniel & Ville)
v3: don't reset if DPIO reset is already de-asserted (Imre)
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Imre Deak [Tue, 27 May 2014 16:00:09 +0000 (19:00 +0300)]
drm/i915: dsi: fix pipe-off timeout due to port vs. pipe disable ordering
If we disable first the port (by disabling DPI) and only then the
display pipe the pipe-off flag will never be set, possibly leading to a
hanged pipe state at the next modeset-enable.
Note that according to the VLV2 display cluster HAS, we should disable
the port before the pipe. This doesn't seem to match reality based on
the above and it's also asymmetric with the enabling sequence, where we
first enable the port and then the pipe.
v2:
- send the panel shutdown command before stopping the pipe, since this
is the recommended sequence (Shobhit)
Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Shobhit Kumar <shobhit.kumar@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Shobhit Kumar [Tue, 27 May 2014 14:03:59 +0000 (19:33 +0530)]
drm/i915: Detect if MIPI panel based on VBT and initialize only if present
It seems by default the VBT has MIPI configuration block as well. The
Generic driver will assume always MIPI if MIPI configuration block is found.
This is causing probelm when actually there is eDP. Fix this by looking
into general definition block which will have device configurations. From here
we can figure out what is the LFP type and initialize MIPI only if MIPI
is found.
v2: Addressed review comments by Damien
- Moved PORT definitions to intel_bios.h and renamed as DVO_PORT_MIPIA
- renamed is_mipi to has_mipi and moved definition as suggested
- Check has_mipi inside parse_mipi and intel_dsi_init insted of outside
v3: Make has_mipi as a bitfield as suggested
Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
[danvet: fold in conditions to pack everything neatly below 80 chars.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Akash Goel [Mon, 24 Mar 2014 17:30:07 +0000 (23:00 +0530)]
drm/i915/vlv: Modifying WA 'WaDisableL3Bank2xClockGate for vlv
For disabling L3 clock gating we need to set bit 25 of MMIO
register 940c. Earlier this was being done by just writing 1
into bit 25 and resetting all other bits.
This patch modifies the routine to read-modify-write of the
register, so that the values of other bits are not destroyed.
v2: Modifying the comments and the patch commit message (Chris)
Shobhit Kumar [Fri, 23 May 2014 16:05:27 +0000 (21:35 +0530)]
drm/i915: Add support for Generic MIPI panel driver
This driver makes use of the generic panel information from the VBT.
Panel information is classified into two - panel configuration and panel
power sequence which is unique to each panel. The generic driver uses the
panel configuration and sequence parsed from VBT block #52 and #53
v2: Address review comments by Jani
- Move all of the things in driver c file from header
- Make all functions static
- Make use of video/mipi_display.c instead of redefining
- Null checks during sequence execution
v3: Address review comments by Damien
- Rename the panel driver file as intel_dsi_panel_vbt.c
- Fix style changes as suggested
- Correct comments for lp->hs and hs->lp count calculations
- General updating comments to have more clarity
- using max() instead of ternary operator
- Fix names (ui_num, ui_den) while using UI in calculations
- compute max of lp_to_hs switch and hs_to_lp switch while computing
hs_lp_switch_count
Daniel Vetter [Thu, 22 May 2014 20:18:22 +0000 (22:18 +0200)]
drm/i915: Extract gen8_gt_irq_reset
Fallout from an intermediate patch revision that I deemed worth saving.
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Daniel Vetter [Thu, 22 May 2014 20:18:21 +0000 (22:18 +0200)]
drm/i915: Improve irq handling after gpu resets
Currently we do a full re-init of all interrupts after a gpu hang.
Which is pretty bad since we don't restore the interrupts we've
enabled at runtime correctly. Even with that addressed it's rather
horribly race.
But on g4x and later we only reset the gt and not the entire gpu.
Which means we only need to reset the GT interrupt bits. Which has the
nice benefit that vblank waits, pipe CRC interrupts and everything
else display related just keeps on working.
The downside is that gt interrupt handling (i.e. ring->get/put_irq) is
still racy. But as long as the gpu hang reliably wakes all waters and
we have a short time where the refcount drops to 0 we'll recover. So
not that bad really.
v2: Ville noticed that GTIMR and PMIMR don't get cleared, only the
subordinate per-ring registers. So let's rip out all the interrupt dancing.
The FIXME comment is still required though since the ring irq handling
happens at the per-ring interrupt mask registers, too.
Testcase: igt/kms_flip/vblank-vs-hang
Testcase: igt/kms_pipe_crc_basic/hang-* Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Daniel Vetter [Thu, 22 May 2014 15:56:33 +0000 (17:56 +0200)]
drm/i915: Disable gpu reset on i965g/gm
Ville figured out that it needs a full display reset since apparently
a lot more goes down than just the GT. Until that's address it's
better to just diable gpu reset.
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Daniel Vetter [Thu, 22 May 2014 15:56:32 +0000 (17:56 +0200)]
drm/i915: Fix up fifo underrun tracking, take N
So apparently this is tricky.
We need to consider:
- We start out with all the hw enabling bits disabled, both the
individual fifo underrun interrupts and the shared display error
interrupts masked. Otherwise if the bios config is broken we'll blow
up with a NULL deref in our interrupt handler since the crtc
structures aren't set up yet at driver load time.
- On gmch we need to mask fifo underruns on the sw side, so always
need to set that in sanitize_crtc for those platforms.
- On other platforms we try to set the sw tracking so that it reflects
the real state. But since a few platforms have shared bits we must
_not_ disable fifo underrun reporting. Otherwise we'll never enable
the shared error interrupt.
This is the state before out patch, but unfortunately this is not good
enough. But after a suspend resume operation this is broken:
1. We don't enable the hw interrupts since the same code runs on
resume as on driver load.
2. The fifo underrun state adjustments we do in sanitize_crtc doesn't
fire on resume since (except for hilarious firmware) all pipes are off
at that point. But they also don't hurt since the subsequent crtc
enabling due to force_restore will enable fifo underruns.
Which means when we enable fifo underrun reporting we notice that the
per-crtc state is already correct and short-circuit everthing out. And
the interrupt doesn't get enabled.
A similar problem would happen if the bios doesn't light up anything
when the driver loads. Which is exactly what happens when we reload
the driver since our unload functions disables all outputs.
Now we can't just rip out the short-circuit logic and unconditionally
update the fifo underrun reporting interrupt masking: We have some
checks for shared error interrupts to catch issues that happened when
the shared error interrupt was disabled.
The right fix is to push down this logic so that we can always update
the hardware state, but only check for missed fifo underruns on a real
enabled->disabled transition and ignore them when we're already
disabled.
On platforms with shared error interrupt the pipe CRC interrupts are
grouped together with the fifo underrun reporting this fixes pipe CRC
support after suspend and driver reloads.
Testcase: igt/kms_pipe_crc_basic/suspend-* Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Daniel Vetter [Thu, 22 May 2014 15:56:31 +0000 (17:56 +0200)]
drm/i915: Add fifo underrun reporting state to debugfs
On platforms with shared interrupt enable bits (which are shared even
with the pipe CRC logic) there's some tricky corner cases. Add
information to make debugging those easier.
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Rob Clark [Tue, 19 Nov 2013 17:10:12 +0000 (12:10 -0500)]
drm: convert crtc and connection_mutex to ww_mutex (v5)
For atomic, it will be quite necessary to not need to care so much
about locking order. And 'state' gives us a convenient place to stash a
ww_ctx for any sort of update that needs to grab multiple crtc locks.
Because we will want to eventually make locking even more fine grained
(giving locks to planes, connectors, etc), split out drm_modeset_lock
and drm_modeset_acquire_ctx to track acquired locks.
Atomic will use this to keep track of which locks have been acquired
in a transaction.
v1: original
v2: remove a few things not needed until atomic, for now
v3: update for v3 of connection_mutex patch..
v4: squash in docbook
v5: doc tweaks/fixes
Signed-off-by: Rob Clark <robdclark@gmail.com> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Wed, 4 Jun 2014 05:47:41 +0000 (15:47 +1000)]
Merge tag 'topic/core-stuff-2014-06-02' of git://anongit.freedesktop.org/drm-intel into drm-next
Just flushing out my pile of random drm patches for the merge window,
nothing big. And it all hung around in drm-intel trees for a while (only
just rebased now).
* tag 'topic/core-stuff-2014-06-02' of git://anongit.freedesktop.org/drm-intel:
imx-drm: imx-tve: remove unused variable
drm: Missed clflushopt in drm_clflush_virt_range
drm/plane: Fix a couple of checkpatch warnings
drm/plane: Fix sparse warnings
drm/exynos: Fix double locks at PM resume
drm/ast: Fix double lock at PM resume
drm/dp-helper: Deprecate old i2c-over-dp_aux heleprs
Dave Airlie [Wed, 4 Jun 2014 03:41:11 +0000 (13:41 +1000)]
Merge branch 'exynos-drm-next' of git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos into drm-next
Summary:
- Resolve probe order and deferred probe issue with component framework
support.
- Resolve hdmi dt broken issue.
. HDMI DT support, which was broken since CCF (common clock framework)
support, and considring legacy dt binding.
- Consolidate HDMI part.
. APB based phy support for Exynos5420 and later, and fixups related
to power on/off sequence.
- Consolidate IPP part.
. Mostly bug fixups and code cleanups.
- Trivial fixups and code cleanups.
* 'exynos-drm-next' of git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos: (64 commits)
drm/exynos: consider deferred probe case
drm/exynos: remove unnecessary exynos_hdmi.h file
drm/exynos/fimd: allow multiplatform configuration
drm/exynos: add hdmiphy power on/off sequence
drm/exynos: ipp: remove description of non-existing field
drm/exynos: ipp: update comment for struct drm_ipp_buf_info
drm/exynos: ipp: rearrange c_node->event_lock using routine
drm/exynos: ipp: rearrange c_node->mem_lock using routines
drm/exynos: ipp: add ipp_remove_id()
drm/exynos: ipp: add cmd_lock for cmd_list
drm/exynos: ipp: rename cmd_lock to lock
drm/exynos: ipp: remove duplicated setting
drm/exynos: ipp: remove usless list_empty() functions
drm/exynos: Use PTR_ERR_OR_ZERO in exynos_dp_core.c
drm/exynos: remove hardware overlays disable from fimd probe
drm/exynos: Fix checkpatch warning in exynos_dp_reg.c
drm/exynos: add fimd dependency to fimd related encoders
drm/exynos: remove redundant mutex_unlock
drm/exynos/fimc: simplify and rename fimc_dst_get_buf_seq
drm/exynos/fimc: replace mutex by spinlock
...
Dave Airlie [Wed, 4 Jun 2014 03:39:12 +0000 (13:39 +1000)]
Merge branch 'msm-next' of git://people.freedesktop.org/~robclark/linux into drm-next
Pretty small pull this time around for msm. Adds some useful debugfs
I'd been carrying around on a branch for a while, plus few fixes. And
Kconfig update for the great ARCH_MSM -> ARCH_QCOM split.
* 'msm-next' of git://people.freedesktop.org/~robclark/linux:
drm/msm: use correct gfp flag for vram allocation
drm/msm/mdp5: fix error return value
drm/msm: remove redundant private plane cleanup
drm/msm: add perf logging debugfs
drm/msm: add rd logging debugfs
drm/msm: update for ARCH_MSM -> ARCH_QCOM
drm/msm/hdmi: use gpio and HPD polling
drm/msm/mdp5: fix crash in error/unload paths
Daniel Vetter [Tue, 3 Jun 2014 17:30:45 +0000 (19:30 +0200)]
drm: Move plane helpers into drm_kms_helper.ko
The drm core shouldn't depend upon any helpers, and we make sure this
doesn't accidentally happen by moving them into the helper-only
drm_kms_helper.ko module.
v2: Don't break the build for vmwgfx, spotted by Matt.
v3: Unbreak the depency loop around CONFIG_FB (not actually a loop
since it involves select). Reported by Chris.
Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Thomas Hellstrom <thellstrom@vmware.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Dave Airlie <airlied@redhat.com>
Daniel Vetter [Thu, 29 May 2014 21:54:47 +0000 (23:54 +0200)]
drm: Split connection_mutex out of mode_config.mutex (v3)
After the split-out of crtc locks from the big mode_config.mutex
there's still two major areas it protects:
- Various connector probe states, like connector->status, EDID
properties, probed mode lists and similar information.
- The links from connector->encoder and encoder->crtc and other
modeset-relevant connector state (e.g. properties which control the
panel fitter).
The later is used by modeset operations. But they don't really care
about the former since it's allowed to e.g. enable a disconnected VGA
output or with a mode not in the probed list.
Thus far this hasn't been a problem, but for the atomic modeset
conversion Rob Clark needs to convert all modeset relevant locks into
w/w locks. This is required because the order of acquisition is
determined by how userspace supplies the atomic modeset data. This has
run into troubles in the detect path since the i915 load detect code
needs _both_ protections offered by the mode_config.mutex: It updates
probe state and it needs to change the modeset configuration to enable
the temporary load detect pipe.
The big deal here is that for the probe/detect users of this lock a
plain mutex fits best, but for atomic modesets we really want a w/w
mutex. To fix this lets split out a new connection_mutex lock for the
modeset relevant parts.
For simplicity I've decided to only add one additional lock for all
connector/encoder links and modeset configuration states. We have
piles of different modeset objects in addition to those (like bridges
or panels), so adding per-object locks would be much more effort.
Also, we're guaranteed (at least for now) to do a full modeset if we
need to acquire this lock. Which means that fine-grained locking is
fairly irrelevant compared to the amount of time the full modeset will
take.
I've done a full audit, and there's just a few things that justify
special focus:
- Locking in drm_sysfs.c is almost completely absent. We should
sprinkle mode_config.connection_mutex over this file a bit, but
since it already lacks mode_config.mutex this patch wont make the
situation any worse. This is material for a follow-up patch.
- omap has a omap_framebuffer_flush function which walks the
connector->encoder->crtc links and is called from many contexts.
Some look like they don't acquire mode_config.mutex, so this is
already racy. Again fixing this is material for a separate patch.
- The radeon hot_plug function to retrain DP links looks at
connector->dpms. Currently this happens without any locking, so is
already racy. I think radeon_hotplug_work_func should gain
mutex_lock/unlock calls for the mode_config.connection_mutex.
- Same applies to i915's intel_dp_hot_plug. But again, this is already
racy.
- i915 load_detect code needs to acquire this lock. Which means the
w/w dance due to Rob's work will be nicely contained to _just_ this
function.
I've added fixme comments everywhere where it looks suspicious but in
the sysfs code. After a quick irc discussion with Dave Airlie it
sounds like the lack of locking in there is due to sysfs cleanup fun
at module unload.
v1: original (only compile tested)
v2: missing mutex_init(), etc (from Rob Clark)
v3: i915 needs more care in the conversion:
- Protect the edp pp logic with the connection_mutex.
- Use connection_mutex in the backlight code due to
get_pipe_from_connector.
- Use drm_modeset_lock_all in suspend/resume paths.
- Update lock checks in the overlay code.
Cc: Alex Deucher <alexdeucher@gmail.com> Cc: Rob Clark <robdclark@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Reviewed-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Fri, 30 May 2014 15:34:01 +0000 (11:34 -0400)]
drm: add extended property types
If we continue to use bitmask for type, we will quickly run out of room
to add new types. Split this up so existing part of bitmask range
continues to function as before, but reserve a chunk of the remaining
space for an integer type-id. Wrap this all up in some type-check
helpers to keep the backwards-compat uglyness contained.
Signed-off-by: Rob Clark <robdclark@gmail.com> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Jani Nikula [Tue, 3 Jun 2014 11:56:19 +0000 (14:56 +0300)]
drm/radeon: replace drm_get_connector_name() with direct name field use
Generated using semantic patch:
@@
expression E;
@@
- drm_get_connector_name(E)
+ E->name
[airlied: regenerated]
Acked-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: David Herrmann <dh.herrmann@gmail.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
David Mansfield [Wed, 4 Jun 2014 02:12:15 +0000 (12:12 +1000)]
drm/qxl: use surface_id 0 for primary surface on all monitors
spice-server and downstream code expect that the primary surface
will always have surface_id = 0, while in reality, once allocated, the
surface_id in qxl.ko is NEVER 0. In a dual head environment, all
monitors render portions of the primary surface.
However, when the monitor config events are generated and sent,
the primary surface is only mapped to the correct identifier
(i.e. 0) for the primary head (where crtc index is 0).
The fix is to look at the "primary" flag in the bo and always
use id 0, irrespective of which head is being configured.
[airlied: qxl hw really needs to be fixed to scanout surfaces]
Christian König [Tue, 3 Jun 2014 22:13:21 +0000 (18:13 -0400)]
drm/radeon: rework page flip handling v4
Instead of trying to flip inside the vblank period when
the buffer is idle, offload blocking for idle to a kernel
thread and program the flip directly into the hardware.
v2: add error handling, fix EBUSY handling
v3: add proper exclusive_lock handling
v4: update crtc->primary->fb when the flip actually happens
Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Tue, 3 Jun 2014 00:34:29 +0000 (10:34 +1000)]
Merge branch 'drm-next-3.16' of git://people.freedesktop.org/~agd5f/linux into drm-next
Highlights:
- GPUVM opimtizations
- HDMI audio cleanups
- Deep color HDMI support
- more bug fixes, cleanups
* 'drm-next-3.16' of git://people.freedesktop.org/~agd5f/linux: (29 commits)
drm/edid: Add quirk for Sony PVM-2541A to get 12 bpc hdmi deep color.
drm/edid: Parse and handle HDMI deep color modes.
drm/radeon: Limit hdmi deep color bit depth to 12 bpc.
drm/radeon: Setup HDMI_CONTROL for hdmi deep color gcp's (v2)
drm/radeon: fix pll setup for hdmi deep color (v7)
drm/radeon: use hw cts/n values for deep color
drm/radeon: only apply hdmi bpc pll flags when encoder mode is hdmi
drm/radeon/atom: fix dithering on certain panels
drm/radeon: optimize CIK VM handling v2
drm/radeon: optimize SI VM handling
drm/radeon: add define for flags used in R600+ GTT
drm/radeon: rework page flip handling v3
drm/radeon: separate vblank and pflip crtc handling
drm/radeon: split page flip and pending callback
drm/radeon: remove drm_vblank_get|put from pflip handling
drm/radeon: remove (pre|post)_page_flip callbacks
drm/radeon/dp: fix lane/clock setup for dp 1.2 capable devices
drm/radeon: fix typo in radeon_connector_is_dp12_capable()
radeon: Remove useless quirk for zx1/FireGL X1 combo introduced with fdo #7770
vgaswitcheroo: switch the mux to the igp on power down when runpm is enabled
...
Mario Kleiner [Fri, 23 May 2014 19:40:55 +0000 (21:40 +0200)]
drm/edid: Add quirk for Sony PVM-2541A to get 12 bpc hdmi deep color.
The Sony PVM-2541A OLED high precision color display supports
both 10 bpc and 12 bpc hdmi deep color input, but its edid
does not signal any deep color support.
Add a quirk to force it being treated as a 12 bpc panel.
Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Mario Kleiner [Thu, 27 Mar 2014 18:59:39 +0000 (19:59 +0100)]
drm/edid: Parse and handle HDMI deep color modes.
Check the HDMI cea block for deep color mode bits. If available,
assign the highest supported bpc for a hdmi display, corresponding
to the given deep color modes.
Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Mario Kleiner [Mon, 5 May 2014 21:03:18 +0000 (23:03 +0200)]
drm/radeon: Limit hdmi deep color bit depth to 12 bpc.
DCE-4/5/6 can't support more than 12 bpc deep color over hdmi,
so clamp to 12 bpc when a hdmi deep color capable display is
connected. This even makes sense on DCE-8+, which could do up
to 16 bpc, as driving with more than 12 bpc would only waste
video bandwidth as long as we don't support framebuffers with
more than 12 bpc depth.
On pre-DCE4 we clamp hdmi bit depth to 8 bpc, as those asics
don't support hdmi deep color.
Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Tue, 22 Apr 2014 02:09:19 +0000 (22:09 -0400)]
drm/radeon: fix pll setup for hdmi deep color (v7)
Need to adjust the pll up for deep color modes.
Additionally, the atom bpc defines were wrong in certain
cases.
v2: set the adjusted clock to the pll clock for hdmi deep
color. This fixes display and audio issues with deep color
as reported by Andy Furniss <adf.lists@gmail.com>
v3: set crtc_clock as well
v4: setcrtcinfo on the adjusted mode
v5: just use the adjusted clock for setting the pll
v6: only use the adjusted clock for hdmi
v7: only DCE5 and DCE6 and bpc > 8
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Tue, 27 May 2014 14:49:22 +0000 (16:49 +0200)]
drm/radeon: rework page flip handling v3
Instead of trying to flip inside the vblank period when
the buffer is idle, offload blocking for idle to a kernel
thread and program the flip directly into the hardware.
Émeric MASCHINO [Fri, 23 May 2014 15:02:24 +0000 (11:02 -0400)]
radeon: Remove useless quirk for zx1/FireGL X1 combo introduced with fdo #7770
Removes useless quirk a7f465f73363fce409870f62173d518b1bc02ae6 introduced with
fdo #7770 as a failed attempt to minimize stability issues with hp zx1 chipset/
ATI FireGL X1 graphics adapter configuration
(see http://marc.info/?l=linux-ia64&m=140077543819871&w=2 for details/reason)
Signed-off-by: Émeric MASCHINO <emeric.maschino@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rafał Miłecki [Fri, 16 May 2014 09:10:29 +0000 (11:10 +0200)]
drm/radeon/hdmi: DCE3: clean ACR control
What initially seemed to be a typo in fglrx (using register 0x740c
instead of 0x74dc) appeared to be a correct behavior. DCE3 has ACR and
CRC registers swapped which explains why we needed
WREG32(HDMI0_AUDIO_CRC_CONTROL + offset, 0x1000);
This has been tested for possible regressions on DCE3 HD3470 (RV620).
Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rafał Miłecki [Fri, 16 May 2014 09:36:24 +0000 (11:36 +0200)]
drm/radeon/hdmi: use separated file for DCE 3.1/3.2 code
DCE 3.1 and 3.2 should be programmed in a different way than DCE 2 and
DCE 3. The order of setting registers and sets of registers are
different.
It's still unsure how we will handle DCE 3.1 vs. DCE 3.2, since they
have few differences as well.
For now separate DCE 2 and DCE 3 path, so we can work on it without a
risk of breaking DCE 3.1+.
This has been tested for possible regressions on DCE32 HD4550 (RV710).
Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Sat, 10 May 2014 10:17:55 +0000 (12:17 +0200)]
drm/radeon: add large PTE support for NI, SI and CIK v5
This patch implements support for VRAM page table entry compression.
PTE construction is enhanced to identify physically contiguous page
ranges and mark them in the PTE fragment field. L1/L2 TLB support is
enabled for 64KB (SI/CIK) and 256KB (NI) PTE fragments, significantly
improving TLB utilization for VRAM allocations.
Linear store bandwidth is improved from 60GB/s to 125GB/s on Pitcairn.
Unigine Heaven 3.0 sees an average improvement from 24.7 to 27.7 FPS
on default settings at 1920x1200 resolution with vsync disabled.
See main comment in radeon_vm.c for a technical description.
v2 (chk): rebased and simplified.
v3 (chk): add missing hw setup
v4 (chk): rebased on current drm-fixes-3.15
v5 (chk): fix comments and commit text
Signed-off-by: Jay Cornwall <jay@jcornwall.me> Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rob Clark [Fri, 30 May 2014 18:47:38 +0000 (14:47 -0400)]
drm/msm: add rd logging debugfs
To ease debugging, add debugfs file which can be cat/tail'd to log
submits, along with fence #. If GPU hangs, you can look at 'gpu'
debugfs file to find last completed fence and current register state,
and compare with logged rd file to narrow down the DRAW_INDX which
triggered the GPU hang.
Dave Airlie [Mon, 2 Jun 2014 09:55:04 +0000 (19:55 +1000)]
Merge tag 'drm-intel-next-2014-05-23' of git://anongit.freedesktop.org/drm-intel into drm-next
- prep refactoring for execlists (Oscar Mateo)
- corner-case fixes for runtime pm (Imre)
- tons of vblank improvements from Ville
- prep work for atomic plane/sprite updates (Ville)
- more chv code, now almost complete (tons of different people)
- refactoring and improvements for drm_irq.c merged through drm-intel-next
- g4x/ilk reset improvements (Ville)
- removal of encoder->mode_set
- moved audio state tracking into pipe_config
- shuffled fb pinning out of the platform crtc modeset callbacks into core code
- userptr support (Chris)
- OOM handling improvements from Chris, with now have a neat oom notifier which
jumps additional debug information.
- topdown allocation of ppgtt PDEs (Ben)
- fixes and small improvements all over
* tag 'drm-intel-next-2014-05-23' of git://anongit.freedesktop.org/drm-intel: (187 commits)
drm/i915: Kill private_default_ctx off
drm/i915: s/i915_hw_context/intel_context
drm/i915: Split the ringbuffers from the rings (3/3)
drm/i915: Split the ringbuffers from the rings (2/3)
drm/i915: Split the ringbuffers from the rings (1/3)
drm/i915: s/intel_ring_buffer/intel_engine_cs
drm/i915: disable GT power saving early during system suspend
drm/i915: fix possible RPM ref leaking during RPS disabling
drm/i915: remove user GTT mappings early during runtime suspend
drm/i915: Implement WaVcpClkGateDisableForMediaReset:ctg, elk
drm/i915: Fix gen2 and hsw+ scanline counter
drm/i915: Draw a picture about video timings
drm/i915: Improve gen3/4 frame counter
drm/i915: Add a small adjustment to the pixel counter on interlaced modes
drm/i915: Hold CRTC lock whilst freezing the planes
drm/i915: Only discard backing storage on releasing the last ref
drm/i915: Wait for pending page flips before enabling/disabling the primary plane
drm/i915: grab the audio power domain when enabling audio on HSW+
drm/i915: don't read HSW_AUD_PIN_ELD_CP_VLD when the power well is off
drm/i915: move bsd dispatch index somewhere better
...
Vincent Stehlé [Sun, 25 May 2014 21:54:14 +0000 (23:54 +0200)]
imx-drm: imx-tve: remove unused variable
Commit f9b0e251dfbf 'drm: make mode_valid callback optional' left variable ret
unused; remove it.
This fixes the following compilation warning:
drivers/staging/imx-drm/imx-tve.c: In function ‘imx_tve_connector_mode_valid’:
drivers/staging/imx-drm/imx-tve.c:252:6: warning: unused variable ‘ret’ [-Wunused-variable]
Signed-off-by: Vincent Stehlé <vincent.stehle@laposte.net> Cc: Andrzej Hajda <a.hajda@samsung.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Ross Zwisler [Wed, 14 May 2014 15:41:12 +0000 (09:41 -0600)]
drm: Missed clflushopt in drm_clflush_virt_range
With this commit:
2a0788dc9bc4 x86: Use clflushopt in drm_clflush_virt_range
If clflushopt is available on the system, we use it instead of clflush
in drm_clflush_virt_range. There were two calls to clflush in this
function, but only one was changed to clflushopt. This patch changes
the other clflush call to clflushopt.
Signed-off-by: Ross Zwisler <ross.zwisler@linux.intel.com> Reported-by: Matthew Wilcox <matthew.r.wilcox@intel.com> Cc: David Airlie <airlied@linux.ie> Cc: dri-devel@lists.freedesktop.org Cc: H Peter Anvin <h.peter.anvin@intel.com> Cc: Ingo Molnar <mingo@kernel.org> Cc: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Thierry Reding [Tue, 13 May 2014 14:58:35 +0000 (16:58 +0200)]
drm/plane: Fix a couple of checkpatch warnings
Code should be indented using tabs rather than spaces (see CodingStyle)
and the canonical form to declare a constant static variable is using
"static const" rather than "const static". Fixes the following warnings
from checkpatch:
$ scripts/checkpatch.pl -f drivers/gpu/drm/drm_plane_helper.c
WARNING: storage class should be at the beginning of the declaration
#40: FILE: drivers/gpu/drm/drm_plane_helper.c:40:
+const static uint32_t safe_modeset_formats[] = {
WARNING: please, no spaces at the start of a line
#41: FILE: drivers/gpu/drm/drm_plane_helper.c:41:
+ DRM_FORMAT_XRGB8888,$
WARNING: please, no spaces at the start of a line
#42: FILE: drivers/gpu/drm/drm_plane_helper.c:42:
+ DRM_FORMAT_ARGB8888,$
Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Thierry Reding [Tue, 13 May 2014 10:47:42 +0000 (12:47 +0200)]
drm/plane: Fix sparse warnings
Include the drm_plane_helper.h header file to fix the following sparse
warnings:
CHECK drivers/gpu/drm/drm_plane_helper.c
drivers/gpu/drm/drm_plane_helper.c:102:5: warning: symbol 'drm_primary_helper_update' was not declared. Should it be static?
drivers/gpu/drm/drm_plane_helper.c:219:5: warning: symbol 'drm_primary_helper_disable' was not declared. Should it be static?
drivers/gpu/drm/drm_plane_helper.c:233:6: warning: symbol 'drm_primary_helper_destroy' was not declared. Should it be static?
drivers/gpu/drm/drm_plane_helper.c:241:30: warning: symbol 'drm_primary_helper_funcs' was not declared. Should it be static?
drivers/gpu/drm/drm_plane_helper.c:259:18: warning: symbol 'drm_primary_helper_create_plane' was not declared. Should it be static?
Doing that makes gcc complain as follows:
CC drivers/gpu/drm/drm_plane_helper.o
drivers/gpu/drm/drm_plane_helper.c:260:19: error: conflicting types for 'drm_primary_helper_create_plane'
struct drm_plane *drm_primary_helper_create_plane(struct drm_device *dev,
^
In file included from drivers/gpu/drm/drm_plane_helper.c:29:0:
include/drm/drm_plane_helper.h:42:19: note: previous declaration of 'drm_primary_helper_create_plane' was here
struct drm_plane *drm_primary_helper_create_plane(struct drm_device *dev,
^
drivers/gpu/drm/drm_plane_helper.c: In function 'drm_primary_helper_create_plane':
drivers/gpu/drm/drm_plane_helper.c:274:11: warning: assignment discards 'const' qualifier from pointer target type
formats = safe_modeset_formats;
^
In file included from include/linux/linkage.h:6:0,
from include/linux/kernel.h:6,
from include/drm/drmP.h:45,
from drivers/gpu/drm/drm_plane_helper.c:27:
drivers/gpu/drm/drm_plane_helper.c: At top level:
drivers/gpu/drm/drm_plane_helper.c:289:15: error: conflicting types for 'drm_primary_helper_create_plane'
EXPORT_SYMBOL(drm_primary_helper_create_plane);
^
include/linux/export.h:57:21: note: in definition of macro '__EXPORT_SYMBOL'
extern typeof(sym) sym; \
^
drivers/gpu/drm/drm_plane_helper.c:289:1: note: in expansion of macro 'EXPORT_SYMBOL'
EXPORT_SYMBOL(drm_primary_helper_create_plane);
^
In file included from drivers/gpu/drm/drm_plane_helper.c:29:0:
include/drm/drm_plane_helper.h:42:19: note: previous declaration of 'drm_primary_helper_create_plane' was here
struct drm_plane *drm_primary_helper_create_plane(struct drm_device *dev,
^
Which can easily be fixed by making the signatures of the implementation
and the prototype match.
Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Takashi Iwai [Fri, 9 May 2014 06:14:15 +0000 (08:14 +0200)]
drm/exynos: Fix double locks at PM resume
The recent commit [3ea87855: drm/helper: lock all around force mode
restore] introduced drm_modeset_lock_all() in
drm_helper_resume_force_mode() itself, while exynos driver takes this
lock before calling it. Move the function call outside the lock for
avoiding a deadlock.
Signed-off-by: Takashi Iwai <tiwai@suse.de> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Takashi Iwai [Fri, 9 May 2014 06:14:14 +0000 (08:14 +0200)]
drm/ast: Fix double lock at PM resume
The recent commit [3ea87855: drm/helper: lock all around force mode
restore] introduced drm_modeset_lock_all() in
drm_helper_resume_force_mode() itself, while ast driver still takes
this lock before calling it. Remove the caller side lock for avoid a
fatal deadlock.
Signed-off-by: Takashi Iwai <tiwai@suse.de> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Daniel Vetter [Wed, 7 May 2014 08:23:55 +0000 (10:23 +0200)]
drm/dp-helper: Deprecate old i2c-over-dp_aux heleprs
Only gma500 is still using this, once that's converted we can kill all
this code. If that conversion doesn't happen soonish I think we should
just move this helper code into the gma500 driver itself to avoid
abuse from new drivers.
Cc: Patrik Jakobsson <patrik.r.jakobsson@gmail.com> Cc: Alan Cox <alan@linux.intel.com> Cc: Thierry Reding <treding@nvidia.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Inki Dae [Thu, 29 May 2014 09:28:02 +0000 (18:28 +0900)]
drm/exynos: consider deferred probe case
This patch makes sure that exynos drm framework handles deferred
probe case correctly.
Sub drivers could be probed before resources, clock, regulator,
phy or panel, are ready for them so we should make sure that exynos
drm core waits until all resources are ready and sub drivers are
probed correctly.
Chagelog v2:
- Make sure that exynos drm core tries to bind sub drivers only in case that
they have a pair: crtc and encoder/connector components should be a pair.
- Remove unnecessary patch:
drm/exynos: mipi-dsi: consider panel driver-deferred probe
- Return error type correctly.
Signed-off-by: Inki Dae <inki.dae@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
YoungJun Cho [Mon, 26 May 2014 08:17:22 +0000 (10:17 +0200)]
drm/exynos: ipp: update comment for struct drm_ipp_buf_info
The attribute gem_objs in struct drm_exynos_ipp_buf_info was
changed to handles. So the comment needs to be updated also.
Signed-off-by: YoungJun Cho <yj44.cho@samsung.com> Acked-by: Seong-Woo Kim <sw0312.kim@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> Tested-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
YoungJun Cho [Mon, 26 May 2014 08:17:21 +0000 (10:17 +0200)]
drm/exynos: ipp: rearrange c_node->event_lock using routine
The c_node->event_list should be protected with
c_node->event_lock.
Signed-off-by: YoungJun Cho <yj44.cho@samsung.com> Acked-by: Seong-Woo Kim <sw0312.kim@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> Tested-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
YoungJun Cho [Mon, 26 May 2014 08:17:20 +0000 (10:17 +0200)]
drm/exynos: ipp: rearrange c_node->mem_lock using routines
The c_node->mem_list[] should be protected with
c_node->mem_lock.
Signed-off-by: YoungJun Cho <yj44.cho@samsung.com> Acked-by: Seong-Woo Kim <sw0312.kim@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> Tested-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
projects / linux-beck.git / log