Olof Johansson [Thu, 9 Jan 2014 06:05:42 +0000 (22:05 -0800)]
Merge tag 'bcm-for-3.14-soc' of git://github.com/broadcom/bcm11351 into next/soc
From Christian Daudt, various defconfig udpates to bcm mobile.
* tag 'bcm-for-3.14-soc' of git://github.com/broadcom/bcm11351:
rename ARCH_BCM to ARCH_BCM_MOBILE (clocksource)
ARM: bcm_defconfig: Unset CONFIG_CRYPTO_ANSI_CPRNG
ARM: bcm_defconfig: Do not expect appended DTB
ARM: bcm_defconfig: CONFIG_OABI_COMPAT default off
Olof Johansson [Thu, 2 Jan 2014 20:10:12 +0000 (12:10 -0800)]
Merge tag 'imx-soc-3.14' of git://git.linaro.org/people/shawnguo/linux-2.6 into next/soc
From Shawn Guo:
i.MX SoC changes for 3.14:
- Add the initial i.MX50 SoC support
- Support device tree boot for i.MX35
- Move imx5 clock driver to use macros for clock ID
- Some random updates and non-critical fixes on clock drivers
- A few defconfig updates and minor cleanups
* tag 'imx-soc-3.14' of git://git.linaro.org/people/shawnguo/linux-2.6: (37 commits)
ARM: imx: improve the comment of CCM lpm SW workaround
ARM: imx: improve status check of clock gate
ARM: imx: add necessary interface for pfd
ARM: imx_v6_v7_defconfig: Select CONFIG_REGULATOR_PFUZE100
ARM: imx_v6_v7_defconfig: Select MX35 and MX50 device tree support
ARM: imx: Add cpu frequency scaling support
ARM i.MX35: Add devicetree support.
ARM: imx: update imx_v6_v7_defconfig
ARM: imx6sl: Add missing spba clock to clock tree
ARM: imx6sl: Add missing pll4_audio_div to the clock tree
ARM: imx6: Derive spdif clock from pll3_pfd3_454m
ARM: imx: use __initconst for const init definition
ARM i.MX5: fix obvious typo in ldb_di0_gate clk definition
ARM i.MX5: set CAN peripheral clock to 24 MHz parent
ARM: imx: pllv1: Fix PLL calculation for i.MX27
ARM i.MX5: fix "shift" value for lp_apm_sel on i.MX50 and i.MX53
ARM: imx: imx53: Add SATA PHY clock
ARM: imx_v6_v7_defconfig: Enable STMPE touchscreen
ARM: imx: rename IMX6SL_CLK_CLK_END to IMX6SL_CLK_END
ARM: imx: select PINCTRL at sub-architecure level
...
Olof Johansson [Thu, 2 Jan 2014 18:35:25 +0000 (10:35 -0800)]
Merge tag 'renesas-soc3-for-v3.14' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc
From Simon Horman:
Third Round of Renesas ARM Based SoC Updates for v3.14
* Global
- Don't set plat_sci_port scbrr_algo_id field
- Declare SCIF register base and IRQ as resources
- Don't define SCIF platform data in an array
- Use macros to declare SCIF devices
* r7s72100 SoC (RZ/A1H)
- Add i2c clocks
* r8a7778 (R-Car M1)
- Add sound SCU clock support
* tag 'renesas-soc3-for-v3.14' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (43 commits)
arm: shmobile: r7s72100: add i2c clocks
ARM: shmobile: r8a7791: Don't set plat_sci_port scbrr_algo_id field
ARM: shmobile: r8a7779: Don't set plat_sci_port scbrr_algo_id field
ARM: shmobile: r8a7790: Don't set plat_sci_port scbrr_algo_id field
ARM: shmobile: r8a7740: Don't set plat_sci_port scbrr_algo_id field
ARM: shmobile: r8a73a4: Don't set plat_sci_port scbrr_algo_id field
ARM: shmobile: r8a7778: Don't set plat_sci_port scbrr_algo_id field
ARM: shmobile: r7s72100: Don't set plat_sci_port scbrr_algo_id field
ARM: shmobile: sh73a0: Don't set plat_sci_port scbrr_algo_id field
ARM: shmobile: r8a7790: Declare SCIF register base and IRQ as resources
ARM: shmobile: r8a7791: Declare SCIF register base and IRQ as resources
ARM: shmobile: r8a7778: Declare SCIF register base and IRQ as resources
ARM: shmobile: sh7372: Don't set plat_sci_port scbrr_algo_id field
ARM: shmobile: r8a7779: Declare SCIF register base and IRQ as resources
ARM: shmobile: r8a7740: Declare SCIF register base and IRQ as resources
ARM: shmobile: r8a73a4: Declare SCIF register base and IRQ as resources
ARM: shmobile: r7s72100: Declare SCIF register base and IRQ as resources
ARM: shmobile: sh73a0: Declare SCIF register base and IRQ as resources
ARM: shmobile: sh7372: Declare SCIF register base and IRQ as resources
ARM: shmobile: r8a7790: Don't define SCIF platform data in an array
...
Stephen Boyd [Fri, 20 Dec 2013 19:09:17 +0000 (11:09 -0800)]
ARM: msm: Simplify ARCH_MSM_DT config
This doesn't need to be a def_bool y. Instead we can have every
DT supported platform select ARCH_MSM_DT and we achieve the same
thing with less chance of conflicts.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: David Brown <davidb@codeaurora.org> Signed-off-by: Olof Johansson <olof@lixom.net>
Rohit Vaswani [Fri, 20 Dec 2013 19:09:15 +0000 (11:09 -0800)]
ARM: msm: Add support for MSM8974 SoC
Add support for the Snapdragon 800 MSM8974 SoC, used on the Dragonboard
and others. Board support added in separate patch.
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org> Acked-by: Kumar Gala <galak@codeaurora.org> Signed-off-by: David Brown <davidb@codeaurora.org>
[olof: split off SoC support in separate patch] Signed-off-by: Olof Johansson <olof@lixom.net>
Josh Cartwright [Fri, 20 Dec 2013 19:09:14 +0000 (11:09 -0800)]
ARM: msm: trout: fix uninit var warning
Fix the following warning when !CONFIG_MMC:
arch/arm/mach-msm/board-trout.c: In function 'trout_init':
arch/arm/mach-msm/board-trout.c:67:6: warning: unused variable 'rc' [-Wunused-variable]
int rc;
^
Also, while we're here, rework explicit printk(KERN_CRIT..) to use
pr_crit.
Signed-off-by: Josh Cartwright <joshc@codeaurora.org> Signed-off-by: David Brown <davidb@codeaurora.org> Signed-off-by: Olof Johansson <olof@lixom.net>
Anson Huang [Tue, 24 Dec 2013 22:19:21 +0000 (17:19 -0500)]
ARM: imx: improve the comment of CCM lpm SW workaround
Improve the comment of SW workaround for CCM lpm issue using
hardware errata description to avoid confusion.
ERR007265: CCM: When improper low-power sequence is used, the SoC
enters low power mode before the ARM core executes WFI.
Software workaround:
1) Software should trigger IRQ #32 (IOMUX) to be always pending
by setting IOMUX_GPR1_GINT.
2) Software should then unmask IRQ #32 in GPC before setting CCM
Low-Power mode.
3) Software should mask IRQ #32 right after CCM Low-Power mode is
set (set bits 0-1 of CCM_CLPCR).
Anson Huang [Tue, 24 Dec 2013 19:21:27 +0000 (14:21 -0500)]
ARM: imx: improve status check of clock gate
For ccm clock gate, both 2b'11 and 2b'01 should be treated
as clock enabled, see below description in CCM, whenver CPU
trys to check clock gate's status, system will be in run mode.
2b'00: clock is off during all modes;
2b'01: clock is on in run mode, but off in wait and stop mode;
2b'10: Not applicable;
2b'11: clock is on during all modes, except stop mode.
Anson Huang [Tue, 24 Dec 2013 19:05:38 +0000 (14:05 -0500)]
ARM: imx: add necessary interface for pfd
Common clk framework will disable unused clks in late init only if
they are enabled by default and no one is using it, so we need to
add is_enabled callback for clk framework to get clks' status.
PFD clocks are enabled by hardware reset, so we need to add
interface for common clk framework to disable those unused ones for
saving power.
Nicolin Chen [Fri, 13 Dec 2013 15:37:52 +0000 (23:37 +0800)]
ARM: imx6: Derive spdif clock from pll3_pfd3_454m
SPDIF can derive a TX clock for playback from one of its clock sources --
spdif root clock to match its supporting sample rates. So this patch set
the spdif root clock's parent to pll3_pfd3_454m since the pll3_pfd3_454m
can approximately meet its sample rate requirement.
Shawn Guo [Mon, 9 Dec 2013 06:04:35 +0000 (14:04 +0800)]
ARM: imx: use __initconst for const init definition
0-DAY kernel build testing backend reports the following.
scripts/checkpatch.pl 0001-ARM-imx-add-support-code-for-IMX50-based-machines.patch
# many are suggestions rather than must-fix
ERROR: Use of const init definition must use __initconst
#80: arch/arm/mach-imx/mach-imx50.c:26:
+static const char *imx50_dt_board_compat[] __initdata = {
While at it, fix the error globally for IMX platform.
ARM i.MX5: set CAN peripheral clock to 24 MHz parent
This patch sets the parent of CAN peripheral clock (a.k.a. CPI clock) to the
lp_apm clock, which has a rate of 24 MHz.
In the CAN world a base clock with multiple of 8 MHz is suited best for all CIA
recommented bit rates. Without this patch the CAN peripheral clock on i.MX53
has a rate of 66.666 MHz which produces quite large bit rate errors.
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Marek Vasut [Fri, 22 Nov 2013 11:05:02 +0000 (12:05 +0100)]
ARM: imx: imx53: Add SATA PHY clock
Add SATA PHY clock which are derived from the USB PHY1 clock. Note that this
patch derives the SATA PHY clock from USB PHY1 clock gate so that the SATA
driver can ungate both the SATA PHY clock and USB PHY1 clock for the SATA to
work correctly.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Richard Zhu <r65037@freescale.com> Cc: Tejun Heo <tj@kernel.org> Cc: Linux-IDE <linux-ide@vger.kernel.org> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Anson Huang [Fri, 15 Nov 2013 18:14:18 +0000 (13:14 -0500)]
ARM: imx: clk: correct arm clock usecount
ARM clock is sourcing from pll1_sw, and pll1_sw can be either from
pll1_sys or step, so we should enable arm clock during clock
initialization instead of pll1_sys, otherwise, arm clock's usecount
would be incorrect and PLL1 will never be disabled even it is not
used.
Olof Johansson [Thu, 26 Dec 2013 19:02:19 +0000 (11:02 -0800)]
Merge tag 'tegra-for-3.14-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/soc
From Stephen Warren:
ARM: tegra: SoC-specific core code changes
This branch contains various miscellaneous changes to code in the
mach-tegra/ directory. It is baased on v3.13-rc1, and shouldn't conflict
with anything else.
* tag 'tegra-for-3.14-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
ARM: tegra: select PINCTRL_TEGRA124 for Tegra124 SoC
ARM: tegra: use section-sized static mappings for LPAE too
ARM: tegra: don't hard-code DEBUG_LL baud rate
ARM: tegra: fix DEBUG_LL combined with LPAE
ARM: tegra: switch FUSE clock on before usage
Olof Johansson [Thu, 26 Dec 2013 18:57:50 +0000 (10:57 -0800)]
Merge tag 'tegra-for-3.14-powergate' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/soc
From Stephen Warren:
ARM: tegra: powergate driver changes
This branch includes all the changes to Tegra's powergate driver for 3.14.
These are separate out, since the Tegra DRM changes for 3.14 rely on the
new APIs introduced here.
A few cleanups and fixes are included, plus additions of Tegra124 SoC
support, and a new API for manipulating Tegra's IO rail deep power down
states.
This branch is based on tag tegra-for-3.14-dmas-resets-rework, in order
to avoid conflicts with the addition of common reset controller support
to the powergate driver.
* tag 'tegra-for-3.14-powergate' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
ARM: tegra: Add IO rail support
ARM: tegra: Special-case the 3D clamps on Tegra124
ARM: tegra: Add Tegra124 powergate support
ARM: tegra: Export tegra_powergate_remove_clamping()
ARM: tegra: Export tegra_powergate_power_off()
ARM: tegra: Rename cpu0 powergate to crail
ARM: tegra: Fix some whitespace oddities
Wolfram Sang [Wed, 18 Dec 2013 21:31:58 +0000 (22:31 +0100)]
arm: shmobile: r7s72100: add i2c clocks
Tested with RIIC2 on a genmai board. Others untested but hopefully
trivial enough to be added.
Signed-off-by: Wolfram Sang <wsa@sang-engineering.com> Acked-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
ARM: shmobile: r8a7790: Don't define SCIF platform data in an array
The SCIF driver is transitioning to platform resources. Board code will
thus need to define an array of resources for each SCIF device. This is
incompatible with the macro-based SCIF platform data definition as an
array. Rework the macro to define platform data as individual
structures.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
ARM: shmobile: r8a7791: Don't define SCIF platform data in an array
The SCIF driver is transitioning to platform resources. Board code will
thus need to define an array of resources for each SCIF device. This is
incompatible with the macro-based SCIF platform data definition as an
array. Rework the macro to define platform data as individual
structures.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
ARM: shmobile: r8a7778: Don't define SCIF platform data in an array
The SCIF driver is transitioning to platform resources. Board code will
thus need to define an array of resources for each SCIF device. This is
incompatible with the macro-based SCIF platform data definition as an
array. Rework the macro to define platform data as individual
structures.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
ARM: shmobile: r7s72100: Don't define SCIF platform data in an array
The SCIF driver is transitioning to platform resources. Board code will
thus need to define an array of resources for each SCIF device. This is
incompatible with the macro-based SCIF platform data definition as an
array. Rework the macro to define platform data as individual
structures.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
ARM: shmobile: r8a73a4: Don't define SCIF platform data in an array
The SCIF driver is transitioning to platform resources. Board code will
thus need to define an array of resources for each SCIF device. This is
incompatible with the macro-based SCIF platform data definition as an
array. Rework the macro to define platform data as individual
structures.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Computing the baud rate register value requires knowledge of the
hardware sampling rate. This information is currently encoded in a baud
rate calculation algorithm ID passed through platform data. However, it
can be derived from the port type directly in most cases.
Compute the sampling rate internally in the driver if the baud rate
calculation algorithm ID isn't specified, and allow platforms to
override the sampling rate through platform data in special cases (this
is only required for SCIFA ports on sh7723 and sh7724, the reason needs
to be investigated).
serial: sh-sci: Compute overrun_bit without using baud rate algo
The overrun bit index is a property of the hardware. It's currently
computed based on a different and unrelated hardware property, the baud
rate calculation algorithm. Compute it using hardware identification
information only.
serial: sh-sci: Move overrun_bit and error_mask fields out of pdata
None of the fields is ever set by board code, and both of them are set
in the driver at probe time. Move them out of struct plat_sci_port to
struct sci_port.
serial: sh-sci: Support resources passed through platform resources
Memory and IRQ resources are currently passed to the driver through
platform data. Support passing them through the standard platform
resources mechanism instead. This deprecates platform data resources.
serial: sh-sci: Remove duplicate interrupt check in verify port op
The driver checks if the interrupt number is greater than nr_irqs and
returns an error in that case. The same check is already performed by
the caller, remove it.
Olof Johansson [Sun, 22 Dec 2013 22:06:14 +0000 (14:06 -0800)]
Merge tag 'samsung-dev' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/soc
From Kukjin Kim:
Samsung updates for v3.14
- Skip eint_init() for pinctrl-exynos because of re-executing
- Use CPU_V6K for S3C64XX(ARM1176JZF-s) instead of CPU_V6
* tag 'samsung-dev' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: S3C64XX: Select CPU_V6K instead of CPU_V6
ARM: SAMSUNG: if detected device tree skip irq init for S5P
Kevin Hilman [Fri, 20 Dec 2013 16:59:45 +0000 (08:59 -0800)]
Merge branch 'keystone/soc' into next/soc
From Santosh Shilimkar:
* keystone/soc:
ARM: keystone: defconfig: enable USB support
ARM: keystone: Avoid calling of_clk_init() twice
ARM: keystone: Make PM bus ready before populating platform devices
ARM: keystone: enable DMA zone for LPAE
ARM: keystone: enable big endian support
Kevin Hilman [Fri, 20 Dec 2013 16:59:04 +0000 (08:59 -0800)]
Merge branch 'efm32/soc' into next/soc
From Uwe Kleine-König:
* efm32/soc: (1003 commits)
ARM: device trees for Energy Micro's EFM32 Cortex-M3 SoCs
ARM: new platform for Energy Micro's EFM32 Cortex-M3 SoCs
+Linux 3.13-rc4
Kevin Hilman [Fri, 20 Dec 2013 16:58:25 +0000 (08:58 -0800)]
Merge branch 'berlin/soc' into next/soc
From Sebastian Hesselbarth:
* berlin/soc:
ARM: add initial support for Marvell Berlin SoCs
ARM: add Armada 1500-mini and Chromecast device tree files
ARM: add Armada 1500 and Sony NSZ-GS7 device tree files
ARM: add Marvell Berlin UART0 lowlevel debug
ARM: add Marvell Berlin SoCs to multi_v7_defconfig
ARM: add Marvell Berlin SoC familiy to Marvell doc
MAINTAINERS: add ARM Marvell Berlin SoC
irqchip: add DesignWare APB ICTL interrupt controller
The koelsch board uses has an SH ethernet controller which uses a Micrel
phy. Select MICREL_PHY for koelsch if SH_ETH is enabled to make use of the
Micrel-specific phy driver rather than relying on the generic phy driver.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Laurent Pinchart [Wed, 11 Dec 2013 14:13:51 +0000 (15:13 +0100)]
ARM: shmobile: rcar-gen2: Initialize CCF before clock sources
When CONFIG_COMMON_CLOCK is enabled, call rcar_gen2_clocks_init() in the
timer init function to initialize the common clock framework before
initializing the clock sources. This will take care of clock
initialization when the r8a779[01] boards will be switched to
multiplatform kernels.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
WingMan Kwok [Wed, 4 Dec 2013 18:51:56 +0000 (13:51 -0500)]
ARM: keystone: defconfig: enable USB support
Enable the USB support (Host mode only) on TI's Keystone platform.
It also enables the support of usb mass storage, FAT and Ext4
filesystems to test rootfs mount over an USB disk.
With commit 4178bac4f {ARM: call of_clk_init from default time_init
handler}, of_clk_init() is always called on machines using default
time_init handler.
So drop the of_clk_init() from keystone code to avoid below
boot errors because of double call.
ARM: keystone: Make PM bus ready before populating platform devices
Keystone PM bus makes use of generic PM clock core backend. Since
generic PM clock core uses platform bus notifiers to track events like
ADD_DEVICE/DEL_DEVICE and to fill clock lists per each device, we need
to initialise Keystone PM domains before the platform devices have been
created.
Hence, fix it by moving keystone_pm_runtime_init() before platform
devices have been populated.
Keystone II peripheral devices support 32-bit DMA and hence can access only
first 2GB of the memory address space. So set the platform dma_zone_size
to handle that case.
Thierry Reding [Fri, 13 Dec 2013 16:31:04 +0000 (17:31 +0100)]
ARM: tegra: Special-case the 3D clamps on Tegra124
A separate register is used to remove the clamps for the GPU on
Tegra124. In order to be able to use the same API, special-case
this particular partition.
Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
Drivers can use the tegra_powergate_remove_clamping() API during
initialization. In order to allow such drivers to be built as modules,
export the symbol.
Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
Dan Carpenter [Mon, 16 Dec 2013 14:02:10 +0000 (17:02 +0300)]
spi: tegra: checking for ERR_PTR instead of NULL
dma_request_slave_channel() returns NULL on error and not ERR_PTRs.
I've fixed this by using dma_request_slave_channel_reason() which does
return ERR_PTRs.
Fixes: a915d150f68d ('spi: tegra: convert to standard DMA DT bindings') Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
projects / karo-tx-linux.git / log