Liu Ying [Sat, 28 Apr 2012 05:24:45 +0000 (13:24 +0800)]
ENGR00181194 IPUv3:Correct pixel clock definition and register
MX6Q has 2 IPUs, each IPU has 2 DIs, so there are totally 4
different pixel clocks. This patch adds maximal pixel clock
number from 2 to 4. Also, the patch fixes potential build
warning caused by the overflow on ipu_lookups structure in case
MXC_IPU_MAX_NUM is 1.
Steve Cornelius [Fri, 20 Apr 2012 00:26:40 +0000 (17:26 -0700)]
ENGR00180943-14: Update internal definition of hardware link table list
Update internal definition of hardware link table list such that it can
work properly on both big and little endian 32-bit configurations. This
required pointer resizing, reserved-field initialization, and the
combination of both buffer-pool ID and offset fields into a common
32-bit value that can burst-read correctly.
Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
Steve Cornelius [Wed, 18 Apr 2012 22:09:09 +0000 (15:09 -0700)]
ENGR00180943-13: Extend for ARM/iMX6 compatibility
Extend for ARM/iMX6 compatibility, including:
- Cache coherence for all streaming buffer mappings
- Initialization from non-OF-dependent lower-level drivers
Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
Steve Cornelius [Wed, 18 Apr 2012 21:38:50 +0000 (14:38 -0700)]
ENGR00180943-12: Extend to include support for ARM targets on iMX6 platforms
Extend to include support for ARM targets on iMX6 platforms, including:
- platform property detection when OF device properties unavailable
- ring entry direction clarification for DMA API access
- cache coherence for rings
Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
Add non-device-tree platform property detection for driver startup and
initialization for iMX6 family, including clock control, job ring
detection and initialization, and interrupt mapping.
Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
Adrian Alonso [Wed, 25 Apr 2012 23:05:44 +0000 (18:05 -0500)]
ENGR00180236-2: spdif clk usecount is 1 when not in use
* Move spdif_core_clk enable from spdif_probe to spdif_startup
function in order to avoid initializing the core clock
when module is not in use.
* At spdif_shutdown disable spdif core_clk.
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
ENGR00180882- MX6DL Add bus frequency scaling support.
Added support for changing DDR frequency on MX6DL.
During system IDLE, DDR freq can drop down to 24MHz
if none of the devices that need high AHB frequency
are active.
Changed the DDR code to handle both MX6Q and MX6DL
DDR and IOMUX settings.
Fixed bug associated incorrect IRAM memory allocation
used to store DDR and IOMUX data.
ENGR00180185: MX6-Add support for low power audio playback
The DDR frequency needs to be at 50MHz for low power audio
playback. So added a new low power mode for audio.
Set the AHB to 25MHz, AXI to 50MHz and DDR to 50MHz in this
mode.
This patch postpones pixel clock and its parent clock(if
the parent clock usecount is 1) disabling time point
until DC/DP/DI enable bits are cleared in IPU_CONF
register to prevent LVDS display channel starvation for
some special LVDS display video mode.
Alan Tull [Wed, 18 Apr 2012 16:40:08 +0000 (11:40 -0500)]
ENGR00180350-2 HDMI set infoframe information
Get speaker allocation data block information from the EDID.
Translate the EDID speaker allocation to audio infoframe
speaker allocation (different bit mapping) given the number
of channels of audio being played.
Set channel count information in HDMI_FC_AUDICONF0.
Set speaker allocation information in HDMI_FC_AUDICONF2.
From CEA-861-D spec:
NOTE—HDMI requires the CT, SS and SF fields to be set to 0 (Refer
to Stream Header) as these items are carried in the audio stream.
Alan Tull [Wed, 18 Apr 2012 16:40:08 +0000 (11:40 -0500)]
ENGR00180350-1 HDMI set infoframe information
Get speaker allocation data block information from the EDID.
Translate the EDID speaker allocation to audio infoframe
speaker allocation (different bit mapping) given the number
of channels of audio being played.
Set channel count information in HDMI_FC_AUDICONF0.
Set speaker allocation information in HDMI_FC_AUDICONF2.
From CEA-861-D spec:
NOTE—HDMI requires the CT, SS and SF fields to be set to 0 (Refer
to Stream Header) as these items are carried in the audio stream.
Jason Liu [Wed, 11 Apr 2012 05:21:15 +0000 (13:21 +0800)]
ENGR00180636: tty/imx: lock check while handle sysrq message
Since the port->lock has already been hold when enter rx_interrupt,
and thus hold it on during handle_sysrq. We need check whether the
current console_write is for the sysrq message output or not and use
the correct lock mechanism.
Wayne Zou [Tue, 24 Apr 2012 00:28:05 +0000 (08:28 +0800)]
ENGR00180618 VDOA: Add vdoa_iram cmdline options and reduce used IRAM size
Add vdoa_iram command line options and reduce used IRAM size
by default to 72KBytes. So by default it only support
partially interleaved 4:2:0 output format.
- Add NAPI methods.
NAPI can improve the performance of high-speed networking,
which can reduce the cpu loading of interrupt generate and
drop packets.
- Enet RX FIFO overruns number has been reduced by NAPI method.
For the standby mode, we force SOC enter STOP mode
and drop the VDDARM_IN and VDDSOC_IN to 0.9V, we need
to disable L1 and L2 cache and invalidate L1 cache when
system resume, as the L1 cache memory's power is dropped
during standby, need to do the invalidation before re-enable
it.
Terry Lv [Mon, 16 Apr 2012 09:44:12 +0000 (17:44 +0800)]
ENGR00179722: MLB: set correct mlb sys clock in mx6dl
In Rigel validatioin, the MLB sys_clock isn't using the right frequency
after boot.
In arik, the register CBCMR controls gpu2d clock, not mlb clock, mlb is
sourced from axi_clock.
But In rigel, the axi clock is lower than in mx6q, so mlb need to find a
new clock root. The gpu2d clock is then root of mlb clock in rigel.
Thus we need to add setting to support this change.
ENGR00172292 usb otg: enable dtds postpone free on mx6
We found this bug occurs again on mx6 when running
CTS with ADB over USB. The system will hang without
any log, and screen a little mess.
It's proved to be a known USB IP issue: USB controller
may access a wrong address for the dTD and then hang.
Re enable this workaround to avoid any system unstability.
Jason Liu [Tue, 17 Apr 2012 11:08:00 +0000 (19:08 +0800)]
ENGR00179851: i.mx6dl: map the MEM mode to STANDBY mode
Due to i.mx6dl TO1.0(TKT094231), Suspend/resume cannot work
stable under deep sleep mode(Dormant, MEM MODE) thus we need
map the MEM mode to STANBY mode(ARM will not power off), this
issue will be fixed on TO1.1
Jason Liu [Tue, 17 Apr 2012 10:53:53 +0000 (18:53 +0800)]
ENGR00179782: i.mx6: consolidate mx6q/dl_revision() support
The idea is to get the soc silicon revision from DIGPROG register Of
ANATOP(USB_ANALOG_DIGPROG), which will make kernel code independent
with bootloader which need pass the system_rev by ATAG.
This patch also will print the chip name and revision when kernel boot
up since this information is important for customer to know.
Liu Ying [Mon, 16 Apr 2012 04:40:37 +0000 (12:40 +0800)]
ENGR00179685 MX6 clock:Cleanup LDB DI parent clock
According to ticket TKT071080, 0b011 for ldb_dix_clk_sel
field in CCM_CS2CDR is changed from pll3_pfd_540M to
mmdc_ch1 when we change from MX6Q TO1.0 to MX6Q TO1.1.
However, MX6DL uses mmdc_ch1 as LDB DI parent clock.
This patch corrects the LDB DI parent clock setting.
ENGR00179696 MX6Q/UART : fix the wrong DMA tranfer direction.
The current SDMA use the new DMA tranfer direction. But the UART still
uses the old. This cause the RX failed.
So use the new DMA transfer direction for UART.
Tony LIU [Mon, 16 Apr 2012 07:47:23 +0000 (15:47 +0800)]
ENGR00179679 Fix usb gadget suspend issue connected to usb charger
- the root cause of this issue is during resume process, USB clock
is not turned on for this USB charger case so that the second
suspend is processed without USB clock, it cause system hang
- in udc resume process, at this situation, we should exit low
power mode to enable the b session valid intrrupt to close the
usb clock when detach from usb charger
Signed-off-by: Tony LIU <junjie.liu@freescale.com>
Liu Ying [Fri, 13 Apr 2012 10:10:14 +0000 (18:10 +0800)]
ENGR00179647 MX6 clock:Correct LDB DI pclk for MX6Q TO1.1
This patch corrects LDB DI clock's parent clock to
be pll2_pfd_352M for both MX6Q TO1.1 and MX6Q TO1.0
according to ticket TKT071080(0b011 for ldb_dix_clk_sel
field in CCM_CS2CDR is changed from pll3_pfd_540M to
mmdc_ch1 when we change from MX6Q TO1.0 to MX6Q TO1.1).
This patch includes some of the clk enable/disable changes from rev2
Check the version of the HDMI IP to determine whether the fifo
threshold needs to be high. The i.Mx6dl version of the HDMI doesn't
need the workaround. All other parts of the workaround are used
for both parts for code simplicity.
----------------------------------------------------------
For i.Mxq, set the Threshold of audio fifo as: FIFO depth - 2 (fixed
and independent of the number of channels actually used).
Use unspecified length ahb bursts (using fixed INCRx will make the
audio dma fail).
Additionally and in order to get it working on all conditions it will
be necessary to run the following sw steps at startup of video and audio
(or when video changes or audio changes):
1-Configure AUD_N1 and AUD_CTS1 registers with final value and let the
AUD_N2, AUD_N3, AUD_CTS2 and AUD_CTS3 to 0s.
2-Configure start and end addresses of audio DMA registers.
3-Start DMA operation
4-Configure the AUD_CTS2 and AUD_CTS3 with the final value.
5-Configure the AUD_N2 and AUD_N3 with final value.
ENGR00179574: MX6- Add bus frequency scaling support
Add support for scaling the bus frequency (both DDR
and ahb_clk).
The DDR and AHB_CLK are dropped to 24MHz when all devices
that need high AHB frequency are disabled and the CORE
frequency is at the lowest setpoint.
The DDR is dropped to 400MHz for the video playback usecase.
In this mode the GPU, FEC, SATA etc are disabled.
To scale the bus frequency, its necessary that all cores
except the core that is executing the DDR frequency change
are in WFE. This is achieved by generating interrupts on
un-used interrupts (Int no 139, 144, 145 and 146).
Wayne Zou [Fri, 13 Apr 2012 00:28:06 +0000 (08:28 +0800)]
ENGR00179513-3 V4L2: Add VDOA tiled format support
Support for VDOA tiled format IPU_PIX_FMT_TILED_NV12 up to 1080p progressive
streams, and IPU_PIX_FMT_TILED_NV12F tiled format up to xga interlaced streams
currently.
b07117 [Wed, 21 Dec 2011 13:32:02 +0000 (21:32 +0800)]
ENGR00170747 gpu driver : add AXI BUS ERROR message
AXI BUS ERROR may occur in very low possibility,
this debug message exist before 4.4.2, but removed in 4.6.x,
need add it back to trace critical gpu issue
Wayne Zou [Fri, 13 Apr 2012 06:16:21 +0000 (14:16 +0800)]
ENGR00179631 MX6 SabreSD: Add MIPI DSI Display support
Add MIPI DSI Display support on mx6 SabreSD board.
MIPI DSI needs pll3_pfd_540M clock source for 540MHz.
if using ldb, the pll3_pfd_540M clock will be changed to 454Mhz.
So add command line option disable_ldb when using MIPI DSI display.
ENGR00179642 Remove a workaround for suspend/resume
Remove a workaround for suspend/resume:
The workaround is turn on clock before gpu entering suspend.
After clock code bug is fixed, this workaround becomes no necessary.
Allen Xu [Tue, 10 Apr 2012 09:02:36 +0000 (17:02 +0800)]
ENGR00179284-4 support ONFI NAND device on mx6q_arm2_pop board
if the NAND chip supports ONFI feature and the board supports ONFI
DDR transfer mode, users could enable ONFI DDR transfer by add command
line parameter "onfi_support"
Robin Gong [Thu, 12 Apr 2012 06:40:42 +0000 (14:40 +0800)]
ENGR00179497-1 ECSPI: disable ecspi clock after probe and spi transfer
before, it enable spi clock after probe, never been disable unless driver
removed. To reduce power, disable clock after probe, and enable it before
every spi transfer and disable it after spi transfer Signed-off-by: Robin Gong <B38343@freescale.com>
Adrian Alonso [Mon, 9 Apr 2012 17:16:53 +0000 (12:16 -0500)]
ENGR00179226: imx-esai remove tx personal reset during record
* Remove transmitter personal reset during stream record
this could potencially block concurrent play/record support.
* Remove receiver personal reset calls, rx is always
operational.
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Jason Liu [Wed, 11 Apr 2012 09:16:36 +0000 (17:16 +0800)]
ENGR00179426-1 i.mx6: iomux: NO_PAD_I/NO_PAD_MUX not defined
NO_PAD_I/NO_PAD_MUX not defined, which will cause build error
According to iomux-v3.h, the NO_PAD_I/NO_PAD_MUX should be 0
for the pins which does not have PAD/MUX config.
Larry Li [Tue, 10 Apr 2012 09:12:51 +0000 (17:12 +0800)]
ENGR00178597 [MX6DL/S] Multi-instance test in GC880 cause system hang
In our code 3d sharder clock uses 3d core clock CCGR field as its
enable bit. That works for MX6Q. But MX6DL uses 3d sharder clock
as 2d core clock, while disable 2d core clock, it will disable 3d
core by mistake.
To fix it, remove the enable bit setting of 3d shader clock in
clock.c file.
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