* pci/host-hv:
PCI: hv: Use vPCI protocol version 1.2
PCI: hv: Add vPCI version protocol negotiation
PCI: hv: Temporary own CPU-number-to-vCPU-number infra
PCI: hv: Use page allocation for hbus structure
PCI: hv: Fix comment formatting and use proper integer fields
* pci/irq-fixups:
arm64: PCI: Drop DT IRQ allocation from pcibios_alloc_irq()
PCI: xilinx-nwl: Move to struct pci_host_bridge IRQ mapping functions
PCI: rockchip: Move to struct pci_host_bridge IRQ mapping functions
PCI: xgene: Move to struct pci_host_bridge IRQ mapping functions
PCI: altera: Drop pci_fixup_irqs()
PCI: versatile: Drop pci_fixup_irqs()
PCI: generic: Drop pci_fixup_irqs()
PCI: faraday: Drop pci_fixup_irqs()
PCI: designware: Drop pci_fixup_irqs()
PCI: iproc: Drop pci_fixup_irqs()
PCI: rcar: Drop pci_fixup_irqs()
PCI: xilinx: Drop pci_fixup_irqs()
PCI: tegra: Drop pci_fixup_irqs()
ARM/PCI: Remove pci_fixup_irqs() call for bios32 host controllers
PCI: Add a call to pci_assign_irq() in pci_device_probe()
OF/PCI: Update of_irq_parse_and_map_pci() comment
PCI: Add pci_assign_irq() function and have pci_fixup_irqs() use it
PCI: Add IRQ mapping function pointers to pci_host_bridge struct
PCI: Build setup-irq.o on all arches
PCI: Remove pci_scan_root_bus_msi()
PCI: xilinx-nwl: Convert PCI scan API to pci_scan_root_bus_bridge()
PCI: rockchip: Convert PCI scan API to pci_scan_root_bus_bridge()
PCI: generic: Convert PCI scan API to pci_scan_root_bus_bridge()
PCI: xgene: Convert PCI scan API to pci_scan_root_bus_bridge()
PCI: xilinx: Convert PCI scan API to pci_scan_root_bus_bridge()
PCI: altera: Convert PCI scan API to pci_scan_root_bus_bridge()
PCI: versatile: Convert PCI scan API to pci_scan_root_bus_bridge()
PCI: iproc: Convert PCI scan API to pci_scan_root_bus_bridge()
PCI: rcar: Convert PCI scan API to pci_scan_root_bus_bridge()
PCI: aardvark: Convert PCI scan API to pci_scan_root_bus_bridge()
PCI: designware: Convert PCI scan API to pci_scan_root_bus_bridge()
ARM/PCI: Convert PCI scan API to pci_scan_root_bus_bridge()
PCI: Make pci_register_host_bridge() PCI core internal
PCI: Add pci_scan_root_bus_bridge() interface
PCI: tegra: Fix host bridge memory leakage
PCI: faraday: Fix host bridge memory leakage
PCI: Add devm_pci_alloc_host_bridge() interface
PCI: Add pci_free_host_bridge() interface
PCI: Initialize bridge release function at bridge allocation
PCI: faraday: Convert IRQ masking to raw PCI config accessors
PCI: iproc: Convert link check to raw PCI config accessors
PCI: xilinx-nwl: Remove nwl_pcie_enable_msi() unused bus parameter
* pci/virtualization:
PCI: Remove __pci_dev_reset() and pci_dev_reset()
PCI: Split ->reset_notify() method into ->reset_prepare() and ->reset_done()
PCI: Protect pci_error_handlers->reset_notify() usage with device_lock()
PCI: Protect pci_driver->sriov_configure() usage with device_lock()
PCI: Mark Intel XXV710 NIC INTx masking as broken
PCI: Restore PRI and PASID state after Function-Level Reset
PCI: Cache PRI and PASID bits in pci_dev
PCI: Split ->reset_notify() method into ->reset_prepare() and ->reset_done()
The pci_error_handlers->reset_notify() method had a flag to indicate
whether to prepare for or clean up after a reset. The prepare and done
cases have no shared functionality whatsoever, so split them into separate
methods.
* pci/portdrv:
PCI/portdrv: Allocate MSI/MSI-X vector for Downstream Port Containment
PCI/portdrv: Support multiple interrupts for MSI as well as MSI-X
* pci/pm:
PCI/PM: Avoid using device_may_wakeup() for runtime PM
x86/PCI: Avoid AMD SB7xx EHCI USB wakeup defect
PCI/PM: Restore the status of PCI devices across hibernation
drm/radeon: make MacBook Pro d3_delay quirk more generic
drm/amdgpu: remove unnecessary save/restore of pdev->d3_delay
PCI/PM: Add needs_resume flag to avoid suspend complete optimization
PCI: imx6: Fix config read timeout handling
switchtec: Fix minor bug with partition ID register
switchtec: Use new cdev_device_add() helper function
PCI: endpoint: Make PCI_ENDPOINT depend on HAS_DMA
* pci/enumeration:
PCI: Enable ECRC only if device supports it
PCI: Add sysfs max_link_speed/width, current_link_speed/width, etc
PCI: Test INTx masking during enumeration, not at run-time
Quentin Schulz [Thu, 8 Jun 2017 08:07:42 +0000 (10:07 +0200)]
PCI: imx6: Add regulator support
Some boards might require to control a regulator to power the PCIe port.
Add support for an optional regulator defined in Device Tree linked in the
PCIe controller under `vpcie-supply`. If present, the regulator will be
disabled and then enabled as part of the PCIe host initialization process
and will be disabled when shutting down.
Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com>
[bhelgaas: use dev_err() instead of pr_err() in
imx6_pcie_assert_core_reset()] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Richard Zhu <hongxing.zhu@nxp.com>
Jork Loeser [Wed, 24 May 2017 20:41:28 +0000 (13:41 -0700)]
PCI: hv: Use vPCI protocol version 1.2
Update the Hyper-V vPCI driver to use the Server-2016 version of the vPCI
protocol, fixing MSI creation and retargeting issues.
Signed-off-by: Jork Loeser <jloeser@microsoft.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: K. Y. Srinivasan <kys@microsoft.com> Acked-by: K. Y. Srinivasan <kys@microsoft.com>
Jork Loeser [Wed, 24 May 2017 20:41:27 +0000 (13:41 -0700)]
PCI: hv: Add vPCI version protocol negotiation
Hyper-V vPCI offers different protocol versions. Add the infra for
negotiating the one to use.
Signed-off-by: Jork Loeser <jloeser@microsoft.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: K. Y. Srinivasan <kys@microsoft.com> Acked-by: K. Y. Srinivasan <kys@microsoft.com>
Jork Loeser [Wed, 24 May 2017 20:41:26 +0000 (13:41 -0700)]
PCI: hv: Temporary own CPU-number-to-vCPU-number infra
To ease parallel effort to centralize CPU-number-to-vCPU-number conversion,
temporarily stand up own version, file-local hv_tmp_cpu_nr_to_vp_nr().
Once the changes have merged, this work-around can be removed, and the
calls replaced with hv_cpu_number_to_vp_number().
Signed-off-by: Jork Loeser <jloeser@microsoft.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: K. Y. Srinivasan <kys@microsoft.com> Acked-by: K. Y. Srinivasan <kys@microsoft.com>
Jork Loeser [Wed, 24 May 2017 20:41:25 +0000 (13:41 -0700)]
PCI: hv: Use page allocation for hbus structure
The hv_pcibus_device structure contains an in-memory hypercall argument
that must not cross a page boundary. Allocate the structure as a page to
ensure that.
Signed-off-by: Jork Loeser <jloeser@microsoft.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: K. Y. Srinivasan <kys@microsoft.com> Acked-by: K. Y. Srinivasan <kys@microsoft.com>
Jork Loeser [Wed, 24 May 2017 20:41:24 +0000 (13:41 -0700)]
PCI: hv: Fix comment formatting and use proper integer fields
Fix comment formatting and use proper integer fields.
Signed-off-by: Jork Loeser <jloeser@microsoft.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: K. Y. Srinivasan <kys@microsoft.com> Acked-by: K. Y. Srinivasan <kys@microsoft.com>
Linus Walleij [Mon, 15 May 2017 17:23:24 +0000 (19:23 +0200)]
PCI: faraday: Add clock handling
Add some optional clock handling to the Faraday FTPCI100. We just get and
prepare+enable the clocks right now, if they exist. We can add more
elaborate clock handling later.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
[bhelgaas: folded in "Make clocks compulsory" fix from
http://lkml.kernel.org/r/20170621085730.28804-1-linus.walleij@linaro.org
Also folded in the clock max/cur speed fixes from
http://lkml.kernel.org/r/20170621162651.25315-1-linus.walleij@linaro.org] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Arvind Yadav [Mon, 19 Jun 2017 09:51:36 +0000 (15:21 +0530)]
PCI: dwc: dra7xx: Use RW1C for IRQSTATUS_MSI and IRQSTATUS_MAIN
Previously, we tried to clear interrupt requests by clearing bits in the
PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI and PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN
registers. But per the TRM, these fields are RW1C, so we must *set* bits
to clear the interrupt bits.
Fixes: 47ff3de911a7 ("PCI: dra7xx: Add TI DRA7xx PCIe driver") Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com>
[bhelgaas: changelog] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
Peter Robinson [Mon, 15 May 2017 12:26:17 +0000 (13:26 +0100)]
PCI: dwc: dra7xx: Depend on appropriate SoC or compile test
The PCI controller attached to a SoC isn't much use if the core SoC isn't
enabled, unless of course it's compile testing, so add appropriate
dependency.
Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
PCI: host: Mark PCIe/PCI (MSI) cascade ISR as IRQF_NO_THREAD
Similar as commit 8ff0ef996ca0 ("PCI: host: Mark PCIe/PCI (MSI) IRQ cascade
handlers as IRQF_NO_THREAD"), we should mark PCIe/PCI (MSI) IRQ cascade
handlers in designware, qcom, and vmd as IRQF_NO_THREAD explicitly.
Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Keith Busch <keith.busch@intel.com> # vmd Acked-by: Jingoo Han <jingoohan1@gmail.com> # pcie-designware-plat.c
arm64: PCI: Drop DT IRQ allocation from pcibios_alloc_irq()
With the introduction of struct pci_host_bridge.map_irq pointer it is
possible to assign IRQs for all devices originating from a PCI host bridge
at probe time; this is implemented through pci_assign_irq() that relies on
the struct pci_host_bridge.map_irq pointer to map IRQ for a given device.
The benefits this brings are twofold:
- the IRQ for a device is assigned once at probe time
- the IRQ assignment works also for hotplugged devices
With all DT based PCI host bridges converted to the struct
pci_host_bridge.{map/swizzle}_irq hooks mechanism the DT IRQ allocation in
ARM64 pcibios_alloc_irq() is now redundant and can be removed.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Will Deacon <will.deacon@arm.com>
PCI: xilinx-nwl: Move to struct pci_host_bridge IRQ mapping functions
struct pci_host_bridge gained hooks to map/swizzle IRQs, so that the IRQ
mapping can be done automatically by PCI core code through the
pci_assign_irq() function instead of resorting to arch-specific
implementation callbacks to carry out the same task which force PCI host
bridge drivers implementation to implement per-arch kludges to carry out a
task that is inherently architecture agnostic.
Add map/swizzle IRQs hooks to the xilinx-nwl PCI host driver to move the
IRQ allocation into core code and stop relying on arch-specific callbacks.
PCI: rockchip: Move to struct pci_host_bridge IRQ mapping functions
struct pci_host_bridge gained hooks to map/swizzle IRQs, so that the IRQ
mapping can be done automatically by PCI core code through the
pci_assign_irq() function instead of resorting to arch-specific
implementation callbacks to carry out the same task which force PCI host
bridge drivers implementation to implement per-arch kludges to carry out a
task that is inherently architecture agnostic.
Add map/swizzle IRQs hooks to the rockchip PCI host driver to move the IRQ
allocation into core code and stop relying on arch-specific callbacks.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Wenrui Li <wenrui.li@rock-chips.com> Cc: Shawn Lin <shawn.lin@rock-chips.com>
PCI: xgene: Move to struct pci_host_bridge IRQ mapping functions
struct pci_host_bridge gained hooks to map/swizzle IRQs, so that the IRQ
mapping can be done automatically by PCI core code through the
pci_assign_irq() function instead of resorting to arch-specific
implementation callbacks to carry out the same task which force PCI host
bridge drivers implementation to implement per-arch kludges to carry out a
task that is inherently architecture agnostic.
Add map/swizzle IRQs hooks to the xgene PCI host driver to move the IRQ
allocation into core code and stop relying on arch-specific callbacks.
Tested-by: Khuong Dinh <kdinh@apm.com> # with e1000e Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Tanmay Inamdar <tinamdar@apm.com>
Since, through struct pci_host_bridge.map/swizzle_irq hooks, IRQs are now
allocated in the pci_assign_irq() callback automatically, PCI host bridge
drivers can stop relying on pci_fixup_irqs() for IRQ allocation.
Drop pci_fixup_irqs() usage from PCI altera host bridge driver.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Ley Foon Tan <lftan@altera.com>
Since, through struct pci_host_bridge.map/swizzle_irq hooks, IRQs are now
allocated in the pci_assign_irq() callback automatically, PCI host bridge
drivers can stop relying on pci_fixup_irqs() for IRQ allocation.
Drop pci_fixup_irqs() usage from PCI versatile host bridge driver.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
[bhelgaas: folded in typo fix from Arnd Bergmann <arnd@arndb.de>:
http://lkml.kernel.org/r/20170621215323.3921382-4-arnd@arndb.de] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Rob Herring <robh@kernel.org>
Since, through struct pci_host_bridge.map/swizzle_irq hooks, IRQs are now
allocated in the pci_assign_irq() callback automatically, PCI host bridge
drivers can stop relying on pci_fixup_irqs() for IRQ allocation.
Drop pci_fixup_irqs() usage from PCI host-common bridge driver.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Will Deacon <will.deacon@arm.com>
Since, through struct pci_host_bridge.map/swizzle_irq hooks, IRQs are now
allocated in the pci_assign_irq() callback automatically, PCI host bridge
drivers can stop relying on pci_fixup_irqs() for IRQ allocation.
Drop pci_fixup_irqs() usage from PCI ftpci100 host bridge driver.
Since, through struct pci_host_bridge.map/swizzle_irq hooks, IRQs are now
allocated in the pci_assign_irq() callback automatically, PCI host bridge
drivers can stop relying on pci_fixup_irqs() for IRQ allocation.
Drop pci_fixup_irqs() usage from PCI designware host bridge driver.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Jingoo Han <jingoohan1@gmail.com> Cc: Joao Pinto <Joao.Pinto@synopsys.com>
Since, through struct pci_host_bridge.map/swizzle_irq hooks, IRQs are now
allocated in the pci_assign_irq() callback automatically, PCI host bridge
drivers can stop relying on pci_fixup_irqs() for IRQ allocation.
Drop pci_fixup_irqs() usage from PCI iproc host bridge driver.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Scott Branden <sbranden@broadcom.com> Cc: Ray Jui <rjui@broadcom.com> Cc: Jon Mason <jonmason@broadcom.com>
Since, through struct pci_host_bridge.map/swizzle_irq hooks, IRQs are now
allocated in the pci_assign_irq() callback automatically, PCI host bridge
drivers can stop relying on pci_fixup_irqs() for IRQ allocation.
Drop pci_fixup_irqs() usage from PCI rcar host bridge driver.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Simon Horman <horms@verge.net.au>
Since, through struct pci_host_bridge.map/swizzle_irq hooks, IRQs are now
allocated in the pci_assign_irq() callback automatically, PCI host bridge
drivers can stop relying on pci_fixup_irqs() for IRQ allocation.
Drop pci_fixup_irqs() usage from PCI xilinx host bridge driver.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Michal Simek <michal.simek@xilinx.com>
Since, through struct pci_host_bridge.map/swizzle_irq hooks, IRQs are now
allocated in the pci_assign_irq() callback automatically, PCI host bridge
drivers can stop relying on pci_fixup_irqs() for IRQ allocation
Drop pci_fixup_irqs() usage from PCI tegra host bridge driver.
ARM/PCI: Remove pci_fixup_irqs() call for bios32 host controllers
Legacy PCI host controllers (ie host controllers that set-up the PCI bus
through the ARM pci_common_init() API) are currently relying on
pci_fixup_irqs() to assign legacy PCI irqs to devices. This is not ideal
in that pci_fixup_irqs() assigns IRQs for all PCI devices present in a given
system some of which may well be enabled by the time pci_fixup_irqs() is
called (ie a system with multiple host controllers). With the introduction
of struct pci_host_bridge.(*map_irq) pointer it is possible to assign IRQs
for all devices originating from a PCI host bridge at probe time; this is
implemented through pci_assign_irq() that relies on the struct
pci_host_bridge.map_irq pointer to map IRQ for a given device.
The benefits this brings are twofold:
- the IRQ for a device is assigned once at probe time
- the IRQ assignment works also for hotplugged devices
Remove pci_fixup_irqs() call from bios32 code and rely on pci_assign_irq()
to carry out the IRQ mapping at device probe time.
The map_irq() and swizzle_irq() struct pci_host_bridge callbacks are set-up
in the struct pci_host_bridge created in the bios32 pcibios_init_hw()
function and mach-* code paths (for PCI mach implementations that require a
specific struct hw_pci.(*scan) function callback).
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
[bhelgaas: folded in fixes from Lorenzo:
http://lkml.kernel.org/r/20170701140629.GC8977@red-moon] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Russell King <linux@armlinux.org.uk> Cc: Andrew Lunn <andrew@lunn.ch>
Matthew Minter [Wed, 28 Jun 2017 20:14:04 +0000 (15:14 -0500)]
PCI: Add a call to pci_assign_irq() in pci_device_probe()
The pci_assign_irq() function allows assignment of an IRQ to devices during
device enable time rather than only at boot. Therefore call it in the
pci_device_probe() function during the enable device code path so this
assignment can be performed.
This patch will do nothing on arches which do not set the IRQ mapping
function pointers and is therefore currently a nop, however as support for
these function pointers is added to arch-specific code this will cause IRQ
assignment to migrate to device enable time allowing the new code paths to
be used.
Signed-off-by: Matthew Minter <matt@masarand.com>
[lorenzo.pieralisi@arm.com: moved pci_assign_irq() call site] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Matthew Minter [Wed, 28 Jun 2017 20:14:02 +0000 (15:14 -0500)]
PCI: Add pci_assign_irq() function and have pci_fixup_irqs() use it
Here we delete the static pdev_fixup_irq() function which is currently what
pci_fixup_irqs() uses to actually assign the IRQs and replace it with the
pci_assign_irq() function which changes the interface and uses the new
function pointers stored in the host bridge structure.
Eventually this will allow pci_fixup_irqs() to be removed entirely and the
new deferred assignment code path will call pci_assign_irq() directly.
However to ensure current users continue to work, a new implementation of
pci_fixup_irqs() is introduced which simply wraps the functionality of
pci_assign_irq().
Signed-off-by: Matthew Minter <matt@masarand.com>
[lorenzo.pieralisi@arm.com: reworked comments/log] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Matthew Minter [Wed, 28 Jun 2017 20:14:02 +0000 (15:14 -0500)]
PCI: Add IRQ mapping function pointers to pci_host_bridge struct
In order to defer IRQ assignment arches must be able to register functions
to map and swizzle interrupts. These registered functions are stored in
the pci_host_bridge struct.
Signed-off-by: Matthew Minter <matt@masarand.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Matthew Minter [Wed, 28 Jun 2017 20:14:02 +0000 (15:14 -0500)]
PCI: Build setup-irq.o on all arches
The functions included in setup-irq.o currently apply only to a selection
of architectures which share common IRQ assignment code. However this code
needs to be generalised for all arches to allow deferred IRQ assignment.
So the first step is to build it on all architectures.
Signed-off-by: Matthew Minter <matt@masarand.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
The pci_scan_root_bus_bridge() function allows passing a parameterized
struct pci_host_bridge and scanning the resulting PCI bus; since the struct
msi_controller is part of the struct pci_host_bridge and the struct
pci_host_bridge can now be passed to pci_scan_root_bus_bridge() explicitly,
there is no need for a scan interface with a MSI controller parameter.
With all PCI host controller drivers and platform code relying on
pci_scan_root_bus_msi() converted over to pci_scan_root_bus_bridge() the
pci_scan_root_bus_msi() becomes obsolete and can be removed.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
PCI: xilinx-nwl: Convert PCI scan API to pci_scan_root_bus_bridge()
The introduction of pci_scan_root_bus_bridge() provides a PCI core API to
scan a PCI root bus backed by an already initialized struct pci_host_bridge
object, which simplifies the bus scan interface and makes the PCI scan root
bus interface easier to generalize as members are added to the struct
pci_host_bridge.
Convert PCI xilinx-nwl host code to pci_scan_root_bus_bridge() to improve
the PCI root bus scanning interface.
PCI: rockchip: Convert PCI scan API to pci_scan_root_bus_bridge()
The introduction of pci_scan_root_bus_bridge() provides a PCI core API to
scan a PCI root bus backed by an already initialized struct pci_host_bridge
object, which simplifies the bus scan interface and makes the PCI scan root
bus interface easier to generalize as members are added to the struct
pci_host_bridge.
Convert PCI rockchip host code to pci_scan_root_bus_bridge() to improve the
PCI root bus scanning interface.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Wenrui Li <wenrui.li@rock-chips.com> Cc: Shawn Lin <shawn.lin@rock-chips.com>
PCI: generic: Convert PCI scan API to pci_scan_root_bus_bridge()
The introduction of pci_scan_root_bus_bridge() provides a PCI core API to
scan a PCI root bus backed by an already initialized struct pci_host_bridge
object, which simplifies the bus scan interface and makes the PCI scan root
bus interface easier to generalize as members are added to the struct
pci_host_bridge.
Convert PCI host-common code to pci_scan_root_bus_bridge() to improve the
PCI root bus scanning interface.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Will Deacon <will.deacon@arm.com>
PCI: xgene: Convert PCI scan API to pci_scan_root_bus_bridge()
The introduction of pci_scan_root_bus_bridge() provides a PCI core API to
scan a PCI root bus backed by an already initialized struct pci_host_bridge
object, which simplifies the bus scan interface and makes the PCI scan root
bus interface easier to generalize as members are added to the struct
pci_host_bridge.
Convert PCI xgene host code to pci_scan_root_bus_bridge() to improve the
PCI root bus scanning interface.
Tested-by: Khuong Dinh <kdinh@apm.com> # with e1000e Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Tanmay Inamdar <tinamdar@apm.com>
PCI: xilinx: Convert PCI scan API to pci_scan_root_bus_bridge()
The introduction of pci_scan_root_bus_bridge() provides a PCI core API to
scan a PCI root bus backed by an already initialized struct pci_host_bridge
object, which simplifies the bus scan interface and makes the PCI scan root
bus interface easier to generalize as members are added to the struct
pci_host_bridge.
Convert PCI xilinx host code to pci_scan_root_bus_bridge() to improve the
PCI root bus scanning interface.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: Michal Simek <michal.simek@xilinx.com>
PCI: altera: Convert PCI scan API to pci_scan_root_bus_bridge()
The introduction of pci_scan_root_bus_bridge() provides a PCI core API to
scan a PCI root bus backed by an already initialized struct pci_host_bridge
object, which simplifies the bus scan interface and makes the PCI scan root
bus interface easier to generalize as members are added to the struct
pci_host_bridge.
Convert PCI altera host code to pci_scan_root_bus_bridge() to improve the
PCI root bus scanning interface.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Ley Foon Tan <lftan@altera.com>
PCI: versatile: Convert PCI scan API to pci_scan_root_bus_bridge()
The introduction of pci_scan_root_bus_bridge() provides a PCI core API to
scan a PCI root bus backed by an already initialized struct pci_host_bridge
object, which simplifies the bus scan interface and makes the PCI scan root
bus interface easier to generalize as members are added to the struct
pci_host_bridge.
Convert PCI versatile host code to pci_scan_root_bus_bridge() to improve
the PCI root bus scanning interface.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
[bhelgaas: folded in fix from Arnd Bergmann <arnd@arndb.de>:
http://lkml.kernel.org/r/20170621215323.3921382-3-arnd@arndb.de] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Rob Herring <robh@kernel.org>
PCI: iproc: Convert PCI scan API to pci_scan_root_bus_bridge()
The introduction of pci_scan_root_bus_bridge() provides a PCI core API to
scan a PCI root bus backed by an already initialized struct pci_host_bridge
object, which simplifies the bus scan interface and makes the PCI scan root
bus interface easier to generalize as members are added to the struct
pci_host_bridge.
Convert PCI iproc host code to pci_scan_root_bus_bridge() to improve the
PCI root bus scanning interface.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Scott Branden <sbranden@broadcom.com> Cc: Ray Jui <rjui@broadcom.com> Cc: Jon Mason <jonmason@broadcom.com>
PCI: rcar: Convert PCI scan API to pci_scan_root_bus_bridge()
The introduction of pci_scan_root_bus_bridge() provides a PCI core API to
scan a PCI root bus backed by an already initialized struct pci_host_bridge
object, which simplifies the bus scan interface and makes the PCI scan root
bus interface easier to generalize as members are added to the struct
pci_host_bridge.
Convert PCI rcar host code to pci_scan_root_bus_bridge() to improve the PCI
root bus scanning interface.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Simon Horman <horms@verge.net.au>
PCI: aardvark: Convert PCI scan API to pci_scan_root_bus_bridge()
The introduction of pci_scan_root_bus_bridge() provides a PCI core API to
scan a PCI root bus backed by an already initialized struct pci_host_bridge
object, which simplifies the bus scan interface and makes the PCI scan root
bus interface easier to generalize as members are added to the struct
pci_host_bridge.
Convert PCI aardvark host code to pci_scan_root_bus_bridge() to improve the
PCI root bus scanning interface.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
PCI: designware: Convert PCI scan API to pci_scan_root_bus_bridge()
The introduction of pci_scan_root_bus_bridge() provides a PCI core API to
scan a PCI root bus backed by an already initialized struct pci_host_bridge
object, which simplifies the bus scan interface and makes the PCI scan root
bus interface easier to generalize as members are added to the struct
pci_host_bridge.
Convert PCI designware host code to pci_scan_root_bus_bridge() to improve
the PCI root bus scanning interface.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Jingoo Han <jingoohan1@gmail.com> Cc: Joao Pinto <Joao.Pinto@synopsys.com>
PCI/PM: Avoid using device_may_wakeup() for runtime PM
pci_target_state() calls device_may_wakeup() which checks whether or not
the device may wake up the system from sleep states, but pci_target_state()
is used for runtime PM too.
Since runtime PM is expected to always enable remote wakeup if possible,
modify pci_target_state() to take additional argument indicating whether or
not it should look for a state from which the device can signal wakeup and
pass either the return value of device_can_wakeup(), or "false" (if the
device itself is not wakeup-capable) to it from the code related to runtime
PM.
While at it, fix the comment in pci_dev_run_wake() which is not about sleep
states.
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Kai-Heng Feng [Fri, 16 Jun 2017 09:40:54 +0000 (17:40 +0800)]
x86/PCI: Avoid AMD SB7xx EHCI USB wakeup defect
On an AMD Carrizo laptop, when EHCI runtime PM is enabled, EHCI ports do
not assert PME# for device plug/unplug events while in D3.
As Alan Stern points out [1], the PME signal is not enabled when controller
is in D3, therefore it's not being woken up when new devices get plugged
in.
Testing shows PME signal works when the EHCI power state is D2.
Clear the PCI_PM_CAP_PME_D3 and PCI_PM_CAP_PME_D3cold bits in
dev->pme_support to indicate the device will not assert PME# from those
states.
Chen Yu [Thu, 25 May 2017 08:49:07 +0000 (16:49 +0800)]
PCI/PM: Restore the status of PCI devices across hibernation
Currently we saw a lot of "No irq handler" errors during hibernation, which
caused the system hang finally:
ata4.00: qc timeout (cmd 0xec)
ata4.00: failed to IDENTIFY (I/O error, err_mask=0x4)
ata4.00: revalidation failed (errno=-5)
ata4: SATA link up 6.0 Gbps (SStatus 133 SControl 300)
do_IRQ: 31.151 No irq handler for vector
According to above logs, there is an interrupt triggered and it is
dispatched to CPU31 with a vector number 151, but there is no handler for
it, thus this IRQ will not get acked and will cause an IRQ flood which
kills the system. To be more specific, the 31.151 is an interrupt from the
AHCI host controller.
After some investigation, the reason why this issue is triggered is because
the thaw_noirq() function does not restore the MSI/MSI-X settings across
hibernation.
The scenario is illustrated below:
1. Before hibernation, IRQ 34 is the handler for the AHCI device, which
is bound to CPU31.
2. Hibernation starts, the AHCI device is put into low power state.
3. All the nonboot CPUs are put offline, so IRQ 34 has to be migrated to
the last alive one - CPU0.
4. After the snapshot has been created, all the nonboot CPUs are brought
up again; IRQ 34 remains bound to CPU0.
5. AHCI devices are put into D0.
6. The snapshot is written to the disk.
The issue is triggered in step 6. The AHCI interrupt should be delivered
to CPU0, however it is delivered to the original CPU31 instead, which
causes the "No irq handler" issue.
Ying Huang has provided a clue that, in step 3 it is possible that writing
to the register might not take effect as the PCI devices have been
suspended.
In step 3, the IRQ 34 affinity should be modified from CPU31 to CPU0, but
in fact it is not. In __pci_write_msi_msg(), if the device is already in
low power state, the low level MSI message entry will not be updated but
cached. During the device restore process after a normal suspend/resume,
pci_restore_msi_state() writes the cached MSI back to the hardware.
But this is not the case for hibernation. pci_restore_msi_state() is not
currently called in pci_pm_thaw_noirq(), although pci_save_state() has
saved the necessary PCI cached information in pci_pm_freeze_noirq().
Restore the PCI status for the device during hibernation. Otherwise the
status might be lost across hibernation (for example, settings for MSI,
MSI-X, ATS, ACS, IOV, etc.), which might cause problems during hibernation.
Suggested-by: Ying Huang <ying.huang@intel.com> Suggested-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by: Chen Yu <yu.c.chen@intel.com>
[bhelgaas: changelog] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Cc: stable@vger.kernel.org Cc: Len Brown <len.brown@intel.com> Cc: Dan Williams <dan.j.williams@intel.com> Cc: Rui Zhang <rui.zhang@intel.com> Cc: Ying Huang <ying.huang@intel.com>
Bjorn Helgaas [Tue, 9 May 2017 15:10:18 +0000 (10:10 -0500)]
drm/radeon: make MacBook Pro d3_delay quirk more generic
The PCI Power Management Spec, r1.2, sec 5.6.1, requires a 10 millisecond
delay when powering on a device, i.e., transitioning from state D3hot to
D0.
Apparently some devices require more time, and d1f9809ed131 ("drm/radeon:
add quirk for d3 delay during switcheroo poweron for apple macbooks") added
an additional delay for the Radeon device in a MacBook Pro. 4807c5a8a0c8
("drm/radeon: add a PX quirk list") made the affected device more explicit.
Add a generic PCI quirk to increase the d3_delay. This means we will use
the additional delay for *all* wakeups from D3, not just those initiated by
radeon_switcheroo_set_state().
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Andreas Boll <andreas.boll.dev@gmail.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> CC: Maarten Lankhorst <maarten.lankhorst@canonical.com>
Bjorn Helgaas [Tue, 9 May 2017 15:08:58 +0000 (10:08 -0500)]
drm/amdgpu: remove unnecessary save/restore of pdev->d3_delay
Remove unnecessary save/restore of pdev->d3_delay.
The only assignments to pdev->d3_delay are in radeon_switcheroo_set_state()
and some quirks, none of which should be relevant in the
amdgpu_switcheroo_set_state() path.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Andreas Boll <andreas.boll.dev@gmail.com> Acked-by: Alex Deucher <alexander.deucher@amd.com>
Bjorn Helgaas [Fri, 19 Aug 2016 08:30:25 +0000 (16:30 +0800)]
PCI: Work around poweroff & suspend-to-RAM issue on Macbook Pro 11
Neither soft poweroff (transition to ACPI power state S5) nor
suspend-to-RAM (transition to state S3) works on the Macbook Pro 11,4 and
11,5.
The problem is related to the [mem 0x7fa00000-0x7fbfffff] space. When we
use that space, e.g., by assigning it to the 00:1c.0 Root Port, the ACPI
Power Management 1 Control Register (PM1_CNT) at [io 0x1804] doesn't work
anymore.
Linux does a soft poweroff (transition to S5) by writing to PM1_CNT. The
theory about why this doesn't work is:
- The write to PM1_CNT causes an SMI
- The BIOS SMI handler depends on something in
[mem 0x7fa00000-0x7fbfffff]
- When Linux assigns [mem 0x7fa00000-0x7fbfffff] to the 00:1c.0 Port, it
covers up whatever the SMI handler uses, so the SMI handler no longer
works correctly
Reserve the [mem 0x7fa00000-0x7fbfffff] space so we don't assign it to
anything.
This is voodoo programming, since we don't know what the real conflict is,
but we've failed to find the root cause.
Bjorn Helgaas [Tue, 21 Mar 2017 18:01:30 +0000 (13:01 -0500)]
PCI: Enable ECRC only if device supports it
John reported that an Intel QuickAssist crypto accelerator didn't work in a
Dell PowerEdge R730. The problem seems to be that we enabled ECRC when the
device doesn't support it:
1302fcf0d03e ("PCI: Configure *all* devices, not just hot-added ones")
exposed the problem because it applies settings from the _HPX method to all
devices, not just hot-added ones. The R730 supplies an _HPX method that
allows the kernel to enable ECRC.
Only enable ECRC if the device advertises support for it.
Link: https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1571798 Fixes: 1302fcf0d03e ("PCI: Configure *all* devices, not just hot-added ones") Reported-by: John Mazzie <john_mazzie@dell.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
ARM/PCI: Convert PCI scan API to pci_scan_root_bus_bridge()
The introduction of pci_scan_root_bus_bridge() provides a PCI core API to
scan a PCI root bus backed by an already initialized struct pci_host_bridge
object, which simplifies the bus scan interface and makes the PCI scan root
bus interface easier to generalize as members are added to the struct
pci_host_bridge.
Convert ARM bios32 code to pci_scan_root_bus_bridge() to improve the PCI
root bus scanning interface.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
[bhelgaas: fold in warning fix from Arnd Bergmann <arnd@arndb.de>:
http://lkml.kernel.org/r/20170621215323.3921382-1-arnd@arndb.de]
[bhelgaas: set bridge->ops for mv78xx0]
[bhelgaas: fold in fixes from Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>:
http://lkml.kernel.org/r/20170701135457.GB8977@red-moon] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Russell King <linux@armlinux.org.uk> Cc: Andrew Lunn <andrew@lunn.ch>
PCI: Make pci_register_host_bridge() PCI core internal
With the introduction of pci_scan_root_bus_bridge() there is no need to
export pci_register_host_bridge() to other kernel subsystems other than the
PCI compilation unit that needs it.
Make pci_register_host_bridge() static to its compilation unit and convert
the existing drivers usage over to pci_scan_root_bus_bridge().
The current pci_scan_root_bus() interface is made up of two main code
paths:
- pci_create_root_bus()
- pci_scan_child_bus()
pci_create_root_bus() is a wrapper function that allows to create a struct
pci_host_bridge structure, initialize it with the passed parameters and
register it with the kernel.
As the struct pci_host_bridge require additional struct members,
pci_create_root_bus() parameters list has grown in time, making it unwieldy
to add further parameters to it in case the struct pci_host_bridge gains
more members fields to augment its functionality.
Since PCI core code provides functions to allocate struct pci_host_bridge,
instead of forcing the pci_create_root_bus() interface to add new
parameters to cater for new struct pci_host_bridge functionality, it is
more suitable to add an interface in PCI core code to scan a PCI bus
straight from a struct pci_host_bridge created and customized by each
specific PCI host controller driver.
Add a pci_scan_root_bus_bridge() function to allow PCI host controller
drivers to create and initialize struct pci_host_bridge and scan the
resulting bus.
When probing the PCI host controller driver, if an error occurs, the probe
function code does not free memory allocated for the struct pci_host_bridge
resulting in memory leakage.
Move the struct pci_host_bridge allocation over to the respective devm
interface to fix the issue.
When probing the PCI host controller driver, if an error occurs, the probe
function code does not free memory allocated for the struct pci_host_bridge
resulting in memory leakage.
Move the struct pci_host_bridge allocation over to the respective devm
interface to fix the issue.
Commit a52d1443bba1 ("PCI: Export host bridge registration interface")
exported the pci_alloc_host_bridge() interface so that PCI host controllers
drivers can make use of it.
Introduce pci_alloc_host_bridge() kernel counterpart to free the host
bridge data structures, pci_free_host_bridge(), export it and update kernel
functions releasing host bridge objects allocated memory to make use of it.
PCI: Initialize bridge release function at bridge allocation
The introduction of pci_register_host_bridge() kernel interface allows PCI
host controller drivers to create the struct pci_host_bridge object,
initialize it and register it with the kernel so that its corresponding PCI
bus can be scanned and its devices probed.
The host bridge device release function pci_release_host_bridge_dev() is a
static function common for all struct pci_host_bridge allocated objects, so
in its current form cannot be used by PCI host bridge controllers drivers
to initialize the allocated struct pci_host_bridge, which leaves struct
pci_host_bridge devices release function uninitialized.
Since pci_release_host_bridge_dev() is a function common to all PCI host
bridge objects, initialize it in pci_alloc_host_bridge() (ie common host
bridge allocation interface) so that all struct pci_host_bridge objects
have their release function initialized by default at allocation time,
removing the need for exporting the common pci_release_host_bridge_dev()
function to other compilation units.
PCI: faraday: Convert IRQ masking to raw PCI config accessors
Current ftpci100 driver host bridge controller driver requires struct
pci_bus to be created in order to mask and clear IRQs using standard PCI
bus config accessors.
This struct pci_bus dependency is fictitious and burdens the driver with
unneeded constraints (eg to use separate APIs to create and scan the root
bus).
Add PCI raw config space accessors to PCIe ftpci100 driver and remove the
fictitious struct pci_bus dependency.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
[bhelgaas: folded in raw PCI read accessor from
http://lkml.kernel.org/r/20170621162651.25315-1-linus.walleij@linaro.org
The clock piece of the above posting goes with the separate "Add clock
handling" patch.] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
PCI: iproc: Convert link check to raw PCI config accessors
The current iproc driver host bridge controller driver requires struct
pci_bus to be created in order to carry out PCI link checks with standard
PCI config space accessors.
This struct pci_bus dependency is fictitious and burdens the driver with
unneeded constraints (eg to use separate APIs to create and scan the root
bus).
Add PCI raw config space accessors to the iproc driver and remove the
fictitious struct pci_bus dependency.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Scott Branden <sbranden@broadcom.com> Cc: Ray Jui <rjui@broadcom.com> Cc: Jon Mason <jonmason@broadcom.com>
Logan Gunthorpe [Thu, 15 Jun 2017 20:12:23 +0000 (14:12 -0600)]
switchtec: Add "running" status flag to fw partition info ioctl
This flag lets userspace know which firmware partitions are currently in
use as opposed to just active. "Active" means they will be in use for the
next reboot, whereas "running" means they are currently in use.
If an old kernel is in use, or the firmware doesn't support these fields,
the new flag will not be set in the output.
Expose PCIe bridges attributes such as secondary bus number, subordinate
bus number, max link speed and link width, current link speed and link
width via sysfs in /sys/bus/pci/devices/...
This information is available via lspci, but that requires root privilege.
Signed-off-by: Wong Vee Khee <vee.khee.wong@ni.com> Signed-off-by: Hui Chun Ong <hui.chun.ong@ni.com>
[bhelgaas: changelog, return errors early to unindent usual case, return
errors with same style throughout] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Gabriele Paoloni [Tue, 23 May 2017 14:23:58 +0000 (15:23 +0100)]
PCI/portdrv: Support multiple interrupts for MSI as well as MSI-X
Root Ports can generate several different interrupts using either MSI or
MSI-X, but we only support that for MSI-X. Ports that support MSI but not
MSI-X are currently limited to sharing a single interrupt.
Rename pcie_port_enable_msix() to pcie_port_enable_irq_vec() and extend it
to support multiple interrupts using either MSI-X (preferred) or MSI.
Piotr Gregor [Fri, 26 May 2017 21:02:25 +0000 (22:02 +0100)]
PCI: Test INTx masking during enumeration, not at run-time
The test for INTx masking via PCI_COMMAND_INTX_DISABLE performed in
pci_intx_mask_supported() should be done before the device can be used.
This is to avoid writing PCI_COMMAND while the driver owns the device, in
case that has any effect on MSI/MSI-X interrupts.
Move the content of pci_intx_mask_supported() to pci_intx_mask_broken() and
call it from pci_setup_device().
The test result can be queried at any time later using the same
pci_intx_mask_supported() interface as before (though with changed
implementation), so callers (uio, vfio) should be unaffected.
Signed-off-by: Piotr Gregor <piotrgregor@rsyncme.org>
[bhelgaas: changelog, remove quirk check, remove locking, move
dev->broken_intx_masking assignment to caller] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Alex Williamson <alex.williamson@redhat.com> Acked-by: Michael S. Tsirkin <mst@redhat.com>
PCI: Protect pci_error_handlers->reset_notify() usage with device_lock()
Every method in struct device_driver or structures derived from it like
struct pci_driver MUST provide exclusion vs the driver's ->remove() method,
usually by using device_lock().
Protect use of pci_error_handlers->reset_notify() by holding the device
lock while calling it.
Note:
- pci_dev_lock() calls device_lock() in addition to blocking user-space
config accesses.
- pci_err_handlers->reset_notify() is used inside
pci_dev_save_and_disable() and pci_dev_restore(). We could hold the
device lock directly in pci_reset_notify(), but we expand the region
since we have several calls following each other.
Without this, ->reset_notify() may race with ->remove() calls, which can be
easily triggered in NVMe.
[bhelgaas: changelog, add pci_reset_notify() comment]
[bhelgaas: fold in fix from Dan Carpenter <dan.carpenter@oracle.com>:
http://lkml.kernel.org/r/20170701135323.x5vaj4e2wcs2mcro@mwanda] Link: http://lkml.kernel.org/r/20170601111039.8913-2-hch@lst.de Reported-by: Rakesh Pandit <rakesh@tuxera.com> Tested-by: Rakesh Pandit <rakesh@tuxera.com> Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Jakub Kicinski [Mon, 22 May 2017 22:50:23 +0000 (15:50 -0700)]
PCI: Protect pci_driver->sriov_configure() usage with device_lock()
Every method in struct device_driver or structures derived from it like
struct pci_driver MUST provide exclusion vs the driver's ->remove() method,
usually by using device_lock().
Protect use of pci_driver->sriov_configure() by holding the device lock
while calling it.
The PCI core sets the pci_dev->driver pointer in local_pci_probe() before
calling ->probe() and only clears it after ->remove(). This means driver's
->sriov_configure() callback will happily race with probe() and remove(),
most likely leading to BUGs, since drivers don't expect this.
Remove the iov lock completely, since we remove the last user.
Sujith Pandel [Tue, 2 May 2017 10:55:40 +0000 (06:55 -0400)]
PCI: Add domain number check to find_smbios_instance_string()
The function find_smbios_instance_string() does not consider the
PCI domain number. As a result, SMBIOS type 41 device type instance
would be exported to sysfs for all the PCI domains which have a
PCI device with same bus/device/function, though PCI bus/device/func
from a specific PCI domain has SMBIOS type 41 device type instance
defined.
Address the issue by making find_smbios_instance_string() check PCI domain
number as well.
Bjorn Helgaas [Fri, 19 May 2017 19:40:50 +0000 (14:40 -0500)]
PCI: Correct PCI_STD_RESOURCE_END usage
PCI_STD_RESOURCE_END is (confusingly) the index of the last valid BAR, not
the *number* of BARs. To iterate through all possible BARs, we need to
include PCI_STD_RESOURCE_END.
Fixes: 9fe373f9997b ("PCI: Increase IBM ipr SAS Crocodile BARs to at least system page size") Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Bjorn Helgaas [Fri, 19 May 2017 19:37:53 +0000 (14:37 -0500)]
efi/fb: Correct PCI_STD_RESOURCE_END usage
PCI_STD_RESOURCE_END is (confusingly) the index of the last valid BAR, not
the *number* of BARs. To iterate through all possible BARs, we need to
include PCI_STD_RESOURCE_END.
Fixes: 55d728a40d36 ("efi/fb: Avoid reconfiguration of BAR that covers the framebuffer") Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Alex Williamson [Wed, 7 Jun 2017 19:00:48 +0000 (13:00 -0600)]
PCI: Mark Intel XXV710 NIC INTx masking as broken
Just like the other XL710 and X710 variants, the XXV710 device IDs appear
to have the same hardware bug, the status register doesn't report pending
interrupts resulting in "irq xx: nobody cared..." errors from the spurious
interrupt handler when we try to use it with device assignment.
Reported-by: Stefan Assmann <sassmann@redhat.com> Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Jesse Brandeburg <jesse.brandeburg@intel.com>
Device drivers need to check if an IOMMU enabled ATS, PRI and PASID in
order to know when they can use the SVM API. Cache PRI and PASID bits in
the pci_dev structure, similarly to what is currently done for ATS.
Imre Deak [Tue, 23 May 2017 19:18:17 +0000 (14:18 -0500)]
PCI/PM: Add needs_resume flag to avoid suspend complete optimization
Some drivers - like i915 - may not support the system suspend direct
complete optimization due to differences in their runtime and system
suspend sequence. Add a flag that when set resumes the device before
calling the driver's system suspend handlers which effectively disables
the optimization.
Needed by a future patch fixing suspend/resume on i915.
Suggested by Rafael.
Signed-off-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Cc: stable@vger.kernel.org
Keith Busch [Fri, 28 Apr 2017 16:02:49 +0000 (12:02 -0400)]
PCI/DPC: Fix control register setting
This driver was OR'ing desired bits from the existing control setting.
That could create an invalid DPC Trigger Enabled configuration if the
platform previously set this to "ERR_FATAL", 01b. The driver currently
wants to set this to ERR_NONFATAL/ERR_FATAL, 10b, and the logical OR of
this gets 11b, which is reserved. Fix that by masking off the fields it is
setting.
Signed-off-by: Keith Busch <keith.busch@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Keith Busch [Fri, 28 Apr 2017 16:02:48 +0000 (12:02 -0400)]
PCI/DPC: Skip DPC event if device is not present
The DPC interupt may be executed on a device that is being removed. Skip
queuing event handling if the status is all 1's, which should be seen only
if the device is not present.
Signed-off-by: Keith Busch <keith.busch@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Lucas Stach [Mon, 22 May 2017 22:06:30 +0000 (17:06 -0500)]
PCI: imx6: Fix config read timeout handling
Commit cc7b0d495589 ("PCI: designware: Update PCI config space remap
function") made PCI configuration requests non-posted, which means we now
get a synchronous abort when the CFG space read to probe for downstream
devices times out.
Synchronous aborts need to be handled differently from the async aborts we
were getting before, in particular the PC needs to be advanced when
resolving the abort. This is mostly a copy of what other PCI drivers do on
ARM to handle those aborts.
[bhelgaas: changelog, "Fixes"] Fixes: cc7b0d495589 ("PCI: designware: Update PCI config space remap function") Tested-by: Fabio Estevam <fabio.estevam@nxp.com> Tested-by: Peter Senna Tschudin <peter.senna@collabora.com> Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Richard Zhu <hongxing.zhu@nxp.com>
projects / karo-tx-linux.git / log