Ethernet performance is downgraded when wait mode on in
100Mbps mode.
wait mode off:
100Mbps mode: tx bandwidth is 94Mbps
rx bandwidth is 94Mbps
wait mode on:
100Mbps mode: tx bandwidth is 30Mbps
rx bandwidth is 94Mbps
After apply the patch:
wait mode on:
100Mbps mode: tx bandwidth is 94Mbps
rx bandwidth is 94Mbps
Wait mode on cause enet interrupt has long latency, which
results in BD entries are full and stop tx queue, so cpus
have more chance to enter wait mode.
Incresing TX BD entries can properly accommodate the blance
between BD request before tx packets and BD release after tx
completion in interrupt process.
Sascha Hauer [Tue, 26 Jun 2012 15:26:16 +0000 (17:26 +0200)]
mtd: gpmi-nand: fix read page when reading to vmalloced area
The gpmi-nand driver uses virt_addr_valid() to check whether a buffer
is suitable for dma. If it's not, a driver allocated buffer is used
instead. Then after a page read the driver allocated buffer must be
copied to the user supplied buffer. This does not happen since commit 7725cc85932bd02dd12c23108e0ef748c551ccba.
This patch fixes the issue. The bug is encountered with UBI which uses a
vmalloced buffer for the volume table.
We now have an interface for notifying the nand_ecc_ctrl functions when OOB
data must be returned to the upper layers and when it may be left untouched.
This patch fills in the 'oob_required' parameter properly from
nand_do_{read,write}_ops. When utilized properly in the lower layers, this
parameter can improve performance and/or reduce complexity for NAND HW and SW
that can simply avoid transferring the OOB data.
Signed-off-by: Brian Norris <computersforpeace@gmail.com> Reviewed-by: Shmulik Ladkani <shmulik.ladkani@gmail.com> Acked-by: Jiandong Zheng <jdzheng@broadcom.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
mtd: nand: add 'oob_required' argument to NAND {read,write}_page interfaces
New NAND controllers can perform read/write via HW engines which don't expose
OOB data in their DMA mode. To reflect this, we should rework the nand_chip /
nand_ecc_ctrl interfaces that assume that drivers will always read/write OOB
data in the nand_chip.oob_poi buffer. A better interface includes a boolean
argument that explicitly tells the callee when OOB data is requested by the
calling layer (for reading/writing to/from nand_chip.oob_poi).
This patch adds the 'oob_required' parameter to each relevant {read,write}_page
interface; all 'oob_required' parameters are left unused for now. The next
patch will set the parameter properly in the nand_base.c callers, and follow-up
patches will make use of 'oob_required' in some of the callee functions.
Note that currently, there is no harm in ignoring the 'oob_required' parameter
and *always* utilizing nand_chip.oob_poi, but there can be
performance/complexity/design benefits from avoiding filling oob_poi in the
common case. I will try to implement this for some drivers which can be ported
easily.
Note: I couldn't compile-test all of these easily, as some had ARCH
dependencies.
[Huang Shijie: I remove the unused code for the other drivers.]
[dwmw2: Merge later 1/0 vs. true/false cleanup] Signed-off-by: Brian Norris <computersforpeace@gmail.com> Reviewed-by: Shmulik Ladkani <shmulik.ladkani@gmail.com> Acked-by: Jiandong Zheng <jdzheng@broadcom.com> Acked-by: Mike Dunn <mikedunn@newsguy.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
If GPU2D used PLL3 as root, we need enable PLL
during GPU power up flow so that we can power up
GPU2D properly.
Till now, this issue can only be duplicated on
Android.
BUILD WARNING:
WARNING: arch/arm/mach-mx6/built-in.o(.data+0x7e44): Section mismatch in
reference from the variable sab_audio_data to the (unknown reference)
.init.rodata:(unknown) The variable sab_audio_data references the
(unknown reference) __initconst (unknown) If the reference is valid then
annotate the variable with __init* or __refdata (see linux/init.h) or
name the variable:
*_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console
In this patch, remove esai_p2p struct with init attribute.
Fix HDMI build warning.
drivers/video/mxc_hdmi.c: In function 'mxc_hdmi_set_mode':
drivers/video/mxc_hdmi.c:1659: warning: assignment discards
qualifiers from pointer target type
drivers/video/mxc_hdmi.c: At top level:
driver/video/mxc_hdmi.c:1398: warning: 'mxc_hdmi_enable_pins'
defined but not used
Remove unused function mxc_hdmi_enable_pins() and mxc_hdmi_disable_pins()
from code. Fix defined but unused function build warning.
Added pointer conversion from const poniter to non-const pointer.
Rong Dian [Mon, 3 Sep 2012 10:37:43 +0000 (18:37 +0800)]
ENGR00222078 power battery:fix charger attach detect missing after resume
1.config gpio dok for AC charger as wake up irq, config gpio uok
for USB charger as wake up irq.
2.add AC/USB charger detect in resume,fix charger detect status update
missing after attach AC/USB charger and resume system
arch/arm/mach-mx6/irq.c: In function 'mx6_init_irq':
arch/arm/mach-mx6/irq.c:106: warning: unused variable 'reg'
arch/arm/mach-mx6/clock_mx6sl.c:1807:
warning: function declaration isn't a prototype
arch/arm/mach-mx6/clock_mx6sl.c:1535:
warning: 'tzasc1_clk' defined but not used
arch/arm/mach-mx6/clock_mx6sl.c:1576:
warning: 'mx6per2_clk' defined but not used
arch/arm/mach-mx6/clock_mx6sl.c:1708:
warning: 'ocram_clk' defined but not used
ENGR00221854 HDMI: suspend/resume hdmi_phy fail to lock.
HDMI PHY init function will been called four times during system resume.
The first call before pixel clock enable, so it will print
PHY PLL unlock message, but the PHY PLL will locked in the next
three times called. It will not affect HDMI PHY function.
ENGR00222900 HDMI AUDIO: fix kernel panic when doing suspend-resume test
In MX6 series, HDMI audio driver is responsible for add IEC header to
audio samples. Driver would maintain variables to cover this work.
The old driver would cause memory access exceeding issue:
1. Resume from an playback. In this case, variable maintained by ALSA is
updated while variable maintained by HDMI driver is not updated. The
mmap copy operation would run into error state due to misalignment.
2. underrun!!! The same error would happens as the items above.
In this patch, add variable check while adding IED header.
Adrian Alonso [Tue, 28 Aug 2012 21:35:20 +0000 (16:35 -0500)]
ENGR00215870-2: board-mx6 sabreauto fix i2c3 pad settings
* Fix i2c3 pad settings, i2c3 conflicts with weim-nor and
spi-nor only in rev b target boards.
* For rev B targets setup extra pads.
* Fix indentation.
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Robin Gong [Mon, 3 Sep 2012 07:17:01 +0000 (15:17 +0800)]
ENGR00222855 MX6 CPUFREQ: support three VDDSOC setpoints
On MX6Q/DL , there is only two set point of VDDSOC/VDDPU, one is 1.25V(1GHz),
another is 1.175V. And in arch/arm/plat-mxc/cpufreq.c will judge whether the
current cpu frequency is the highest set point(1G) or not to set the right
VDDSOC/VDDPU. The logic is also match to dynamic ldo bypass function, since the
change point is the highest set point too. But there is three set points of
VDDSOC/VDDPU in MX6SL , so the logic in cpufreq.c need to change. Now
VDDSOC/VDDPU will track with VDDARM fully.
Steve Cornelius [Thu, 30 Aug 2012 21:15:39 +0000 (14:15 -0700)]
ENGR00215875-2: caam: fix descriptor buffer overrun in hash_digest_key()
HMAC keys often need to be reduced to under the size of a digest to
be used. The driver does this psuedo-synchronously through the use of
hash_digest_key(), which builds a sequence pointered job descriptor to
perform this function.
When this function built the job descriptor, it correctly accounted for the
number of instructions and number of pointers that would go into its
construction. However, it failed to account for the fact that both the
sequence in and out pointers used extended lengths, adding 8 more bytes to
the required job descriptor. This caused the descriptor to overrun the
allocated buffer by that amount, resulting in memory corruptions.
Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com> Signed-off-by: Terry Lv <r65388@freescale.com>
Steve Cornelius [Tue, 14 Aug 2012 22:04:11 +0000 (15:04 -0700)]
ENGR00215875-1: caam: improve initalization for context state saves
Multiple function in asynchronous hashing use a saved-state block,
a.k.a. struct caam_hash_state, which holds a stash of information
between requests (init/update/final). Certain values in this state
block are loaded for processing using an inline-if, and when this
is done, the potential for uninitialized data can pose conflicts.
Therefore, this patch improves initialization of state data to
prevent false assignments using uninitialized data in the state block.
This patch addresses the following traceback, originating in
ahash_final_ctx(), although a problem like this could certainly
exhibit other symptoms:
ENGR00222148 [MX6SL]Shrink GPU reserved memory to 32M
MX6SL only has 512M memory.Shrinking GPU reserved memory to 32M
can help out of memory issue on MX6SL.This patch will increase
96M system memory, so it will help the case which requests lots
of system memory.Like multiple application running, etc.
And MX6SL doesn't have 3D, 32M is recommended by vivante.
ENGR00222835 MX6x-Fix incorrect enabling/disabling of PLL1
PLL1 was enabled without incrementing the usecount, and was
thus not getting disabled under certain conditions.
This causes 2 issues:
1. Increases the power.
2. Causes crashes on MX6SL in audio mode as ARM is switched
to PLL1 assuming its in bypass when entering WAIT mode. But PLL1
is enabled and not in bypass state.
ENGR00222834 MX6x-A9 prefetcher should not access DDR before IO is restored
Add enough nops to suspend code when exiting due to a pending
interrupt. This is required so that we can guarantee that the
prefetch unit will not bring DDR out of self-refresh before
all of the DDR's IO pads are restored.
Liu Ying [Fri, 31 Aug 2012 09:19:24 +0000 (17:19 +0800)]
ENGR00222197 MX6 SabreSD:Set pwm backlight max density to 248
This patch changes pwm backlight max density from 255 to 248
to workaround Hannstar LVDS panel unstable backlight issue
when density is set to 250 or 251.
ENGR00222157 MX6x-Fix bug in transitioning from low_bus to audio_bus mode.
Ensure that the transtion from low bus freq mode to
audio bus freq mode happens instantly. Don't schedule
the delayed work in this case else there will be a pause
in the audio playback.
ENGR00222257 MX6x-Prime TLB entries before DDR enters self-refresh.
Need to ensure that no page table walk occurs in DDR when it is in
self refresh and its IO pads are floated during suspend.
Hence we need to make sure that the translation of all the
addresses that the suspend code will access is in the TLB before
DDR cannot be accessed anymore.
So do a dummy read of IOMUX, MMDC, SRC and ANATOP regsiters.
Also need to add a dsb to drain all the write buffers before
DDR enters self-refresh.
Also ensure that the LDO bypass enable is reset if an interrupt
is pending before the system enters suspend.
ENGR00222134 MX6x - Fix race-conditions in low power code.
Fix couple of race-conditions associated with low power IDLE code:
1. Ensure that bus freq mutex is used in the suspend/resume function
2. Ensure that the usecount of pll2 is incremented/decremented when
ARM is switched to run from PLL2_PFD_400. And PLL2 is enabled/disabled
when necessary.
ENGR00222133 MX6SL - Fix crashes caused by Low power IDLE support
Need to ensure that the ARM_CLK rate stays exactly the same
when moving ARM_CLK from PLL2_PFD_400 to PLL1 when system
enters 24MHz state. Also need to ensure that PLL1 is enabled
before relocking the PLL to the correct rate.
Liu Ying [Thu, 30 Aug 2012 01:39:59 +0000 (09:39 +0800)]
ENGR00221370 IPUv3:Clean up IPUv3 interrupt handler
1) In the interrupt handler, we access sync interrupt
control registers 2 times, and each time with spin
lock being held and then released, which may cause
potential racing on the registers. We see that
as long as the racing happens with two displays
enabled on the same IPU, one IPU display channel
will lose EOF interrupt and it makes its fb's pan
display ioctrl fail with timeout. This patch changes
to hold the spin lock one time for the whole irq
handler, as the handler should return quickly.
Holding and releasing the spin lock unnecessarily
may bring performance penalty as well.
2) We do not need to use spin_lock_irqsave() and
spin_unlock_irqrestore() in the interrupt handler,
as we are already in the hard irq context. Using
spin_lock() and spin_unlock() is enough to protect
the registers.
3) Clear an interrupt control bit as soon as its related
handler finishes.
Liu Ying [Thu, 30 Aug 2012 01:33:01 +0000 (09:33 +0800)]
ENGR00221983 IPUv3:Correct ERR and SYNC interrupt line numbers
As we define ERR interrupt with 0 irq resource id and SYNC
interrupt with 1 irq resource id in platform-imx_ipuv3.c,
we wrongly assign them in IPUv3 driver.
Need to ensure that check for usecount in clk_set_parent
occurs within the protection of the clock mutex. Else
there is a chance that the usecount can be decremented
(and the clock disabled) after the check.
Also add back the code to maintain the correct usecount
for pll2_pfd_400.
ENGR00221974 MX6SL-Fix system hang/crash issue in low power IDLE
Ensure that the pull-up is enabled when the DQS line of LPDDR2
is floated when DDR freq is dropped to 24MHz. This is required
else its possible that the DDR will latch incorrect data when it
exits self-refresh.
CKE line should not be floated as it may cause DDR to incorrectly
exit self-refresh mode.
Also add 25 nops after the code that removes DDR from self-refresh.
We need this to ensure that the prefetcher block in A9 does not
access any instruction from DDR before the DDR exits self-refresh.
The A9 prefetch depth is about 23, hence 25 nops.
ENGR00221970 MX6SL:Fix suspend/resume issue on MX6SLEVK
Make sure the Pull Ups are enabled on the DQS lines of
LPDDR2 memory. Without that its possible that the data
latched by the memory will be incorrect when exiting from
self-refresh mode. So only set the drive strengths to 0
when floating the DDR IO pads before entering suspend.
Also never float the CKE pad, this pin always needs to be
driven, else the DDR may incorrectly exit self-refresh.
Hence remove the line that was setting CKE drive strength
to zero (GRP_CTLDS).
Anson Huang [Wed, 29 Aug 2012 19:10:07 +0000 (03:10 +0800)]
ENGR00221902 [MX6]Fix udelay inaccurate issue during suspend/resume
When system enter suspend, we increase CPUFreq to the highest point
without update the global loops_per_jiffy, it will lead to udelay
inaccurate during the last phase of suspend/resume.
WB counter and RBC counter need at least two 32K cycles to finish,
here we add 80us for safe.
make shi [Tue, 28 Aug 2012 09:12:07 +0000 (17:12 +0800)]
ENGR00221716-01 Mx6 USB host: set disconnect bit should wait for resume finished
For i.MX6DLTO1.1 and i.MX6DQTO1.2, the disconnection-bit can only be set after
the resume finished, otherwise, the remote-wake-up may fail. Because if the
device not switch to High-Speed 45ohm termination resistors mode, when the
disconnection detection bit is set the disconnection detection circuit will
detect a high speed disconnection by mistake.
Chen Liangjun [Tue, 21 Aug 2012 09:28:50 +0000 (17:28 +0800)]
ENGR00182456-3 HDMI VIDEO: abort audio when unblank and plugout
In this patch:
1. Close audio PCM stream when video unblank and plugout event happens.
2. Set HDMI cable and blank state into HDMI core driver when
plug/unplug, blank/unblank events happens.
Chen Liangjun [Tue, 21 Aug 2012 09:25:36 +0000 (17:25 +0800)]
ENGR00182456-1 HDMI: Add interface for HDMI audio management
In this patch, add support for:
1. Interface for HDMI audio to register PCM into HDMI core driver.
2. Interface for HDMI video driver to stop HDMI audio
3. Interface for HDMI video driver to inform the state of HDMI cable and
state of HDMI blank.
Anson Huang [Tue, 28 Aug 2012 09:43:01 +0000 (17:43 +0800)]
ENGR00221643 [MX6]Fix race condition of pfd 400 usecount
We can't modify the usecount of pfd 400M clock when ARM freq
is changed, as when the children of pfd 400M do clock enable/disable,
they will also modify this usecount, these two modification is
out of same lock protection. And this wrong usecount may lead to
pfd 400M or pll2 disabled accidently, and it will cause system hang!
Loren HUANG [Fri, 24 Aug 2012 02:05:30 +0000 (10:05 +0800)]
ENGR00221197-2 Update gpu driver to check Soc temperature
-Update gpu driver to check the SoC temperature, if the thermal_hot flag
is set by thermal driver. GPU3D clock will be slown down to the minimum
value, the clock will be recovery when the flag is cleared by thermal driver.
-This patch depends on ENGR00220848, without it, kernel build can't pass.
Sandor Yu [Mon, 27 Aug 2012 02:25:02 +0000 (10:25 +0800)]
ENGR00221444 HDMI: video mode wrong when bootup without HDMI cable
Bootup Android without HDMI cable plugin, then plugin HDMI cable,
video mode in /sys/class/graphics/fb0/mode not same as actually
HDMI work video mode.
The root cause is in video mode point to one of video mode in
original video modelist, but the modelist will be updated when
HDMI cable plug to new monitor.
If HDMI original worked video mode can work on new monitor,
the HDMI and framebuffer will not updated, so HDMI actually
work mode not same as /sys/class/graphics/fb0/mode
Updated fbi mode pointer even if video mode no changed
in case moselist is updated, the issue will fixed.
ENGR00221161 [MX6SL]- Add audio bus freq mode support.
Set DDR to 50MHz in low power audio playback.
AHB/AXI are at 24MHz.
Also fix correct usecount for PLL1 main clock. If not
it causes issues when pll1_sw_clk's parent is changed.
ENGR00221440 MX6x-Fix race-condition in checking bus_freq variables
Checking of the bus_freq variables and changing of the
bus/ddr frequency should be done under one mutex.
Else there is a race-condition that the variable changed
just after it was checked.
Also ensure that the bus freq is always increased before
the cpu freq is set to anything other than the lowest setpoint.
Else there is a possibility that the ARM is set to run from
PLL1 at higher frequency when bus/DDR are still at 24MHz.
This is dangerous since when system enters WAIT mode in
low bus freq state, PLL1 is set to bypass when ARM is being
sourced from it.
Chen Liangjun [Fri, 24 Aug 2012 04:32:36 +0000 (12:32 +0800)]
ENGR00219933 CS42888: abort delay powerdown if codec is on
CS42888 driver own 2 codec_dai for ESAI and ASRC P2P use. Due to the
delay power down mechanism, if a ASRC P2P stream is played right after
a finish of ESAI stream playback, ASRC P2P stream would be stop.
In this patch, do nothing in the delay powerdown flow if CS42888
codec is on.
make shi [Fri, 24 Aug 2012 05:53:49 +0000 (13:53 +0800)]
ENGR00221317-02 Mx6 USB host: set stop_mode_config when any USB host enabled
The Mx6 phy sometimes work abnormally after system suspend/resume if the 1V1
is off. So we should keep the 1V1 active during the system suspend if any USB
host enabled.
- Add stop_mode_config to 1 with refcount
- Add mutex to protect the refcount and HW_ANADIG_ANA_MISC0 register
- If stop_mode_config is set as 1, the otg vbus wakeup system will be supported
Change AXI_CLK to be sourced from PLL3_PFD1_540MHz, so that it
can run at 270MHz on MX6DL/S. This is required for improving
VPU performance.
Change AXI_CLK to be sourced from periph_clk just before the DDR
freq is going to be dropped to 24MHz/50MHz. Change it back
to PLL3_PFD1_540 when the DDR freq is back at 400MHz.
Peter Chen [Thu, 23 Aug 2012 08:29:55 +0000 (16:29 +0800)]
ENGR00221217 usb: device: fix usb_state incorrect problem after pc sends resume
At pc sends suspend/resume case, the udc_controller->usb_state should
keep unchange during the suspend/resume process, at former code, the
fsl_udc_resume set udc_controller->usb_state to USB_STATE_ATTACHED
unconditionally. In fact, USB_STATE_ATTACHED stands for initial state
and should be set when we try to run controller.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
Robin Gong [Thu, 23 Aug 2012 03:45:22 +0000 (11:45 +0800)]
ENGR00221102-2 MX6Q: increase VPU frequence to 352Mhz
Increase VPU frequency to 352Mhz for TV box, use pll2_pfd_400M.To avoid impact
other code which assume ARM clock sourcing from pll2_pfd_400M, change cpu
setpoint of 396M to 352M. and disable bus freq adjust.
add CONFIG_MX6_VPU_352M to choose it, default is disabled. Signed-off-by: Robin Gong <B38343@freescale.com>
Robin Gong [Thu, 23 Aug 2012 03:43:45 +0000 (11:43 +0800)]
ENGR00221102-1 MX6Q: increase VPU frequence to 352Mhz
Increase VPU frequency to 352Mhz for TV box, use pll2_pfd_400M.To avoid impact
other code which assume ARM clock sourcing from pll2_pfd_400M, change cpu
setpoint of 396M to 352M. and disable bus freq adjust.
add CONFIG_MX6_VPU_352M to choose it, default is disabled.
Sandor Yu [Wed, 22 Aug 2012 02:57:50 +0000 (10:57 +0800)]
ENGR00220538 HDMI: Clock mismatch in suspend&resume when video playback
In suspend/resume and HDMI plugin/plugout stress test,
sometimes fbcon will call fb_set_par with
parameter fb_var_screeninfo that xres anfd yres is zero.
MX frame buffer driver can not correct handle this casue,
it will cause IPU pixel clock gating/ungating mismatch.
Check fb_var_screeninfo parameter in mxcfb_check_var and
mxcfb_set_par function, returned if xres,yres zero.
ENGR00220696 [MX6SL]-Reduce IDLE mode power consumption.
When ARM enters WFI in low power IDLE state, float the DDR
IO pins to drop the power on the VDDHIGH rail.
Need to run WFI code from IRAM since DDR needs to be
put into self-refresh before changing the IO pins.
Drop AHB to 8MHz and DDR to 1MHz when ARM is in WFI when
in IDLE state.
Set IPG_PERCLK to run at 3MHz, since we want to maintain a
1:2.5 ratio between PERCLK to AHB_CLK.
Ryan QIAN [Thu, 2 Aug 2012 01:46:53 +0000 (09:46 +0800)]
ENGR00219601-01: mmc: queue: enlarge the size of bounce buffer for SDMA.
- set bounce buffer to 512KB from 64K, which is hw max seg size for
fsl sd host controller
- by enlarging the size of bounce buffer, it will reduce the number
of irq on writing by merging small requests into a large one, which
will improve writing throughput.
- the side effect is that the reading throughput of 512KB bounce buffer
is lower than the one of 64KB bounce buffer, when cpu freq is at 200Mhz.
Test Env:
1. MX6DL SabreSD board
2. On board eMMC (Sandisk: SDIN5C2-8G) running at 8-bit DDR @ 52Mhz
3. Test commands:
3.1 Writing test command:
# dd if=/dev/zero of=/dev/mmcblk0 bs=1M count=100 conv=fsync
3.2 Reading test command:
# echo 1 > /proc/sys/vm/drop_caches
# echo 1 > /proc/sys/vm/drop_caches
# sleep 1
# dd if=/dev/mmcblk0 of=/dev/null bs=1M count=100
Liu Ying [Mon, 20 Aug 2012 05:59:40 +0000 (13:59 +0800)]
ENGR00220734 IPUv3 fb:Rewind eof irq sync mechanism back
This patch changes to use original sync mechanism for eof
irq, which may improve pan-display or alpha buffer update
performance.
1) Initialize flip_completion and alpha_flip_completion
only once when fb is initialized instead of initializing
it every time when pan display is called.
2) Clear and enable eof irq after selecting buffer ready.
In this way, we have no chance to lose an interrupt, as
selecting a new buffer ready doesn't make the eof irq
come(from the newly selected buffer) before we clear the irq
status and enable the irq. Otherwise, if we clear the irq
status and enable the irq before we doing down in pan-display
or alpha buffer update, we have chance(users call pan-display or
alpha buffer update faster than vsync frequency and blocks at
down()) to clear an unhandled irq, which may cause performance
issue.
Robin Gong [Mon, 20 Aug 2012 11:24:28 +0000 (19:24 +0800)]
ENGR00220776 mx6dl_arm2: ECSPI pin config overlaped by epdc
ECSPI pin MX6DL_PAD_EIM_D17__ECSPI1_MISO is configured overlap by epdc
MX6DL_PAD_EIM_D17__GPIO_3_17, so that SPI-NOR flash can't work normally.
From schematic of ARM2 board, epdc and spi share this pin if plug epdc
daughter board. But SPI-NOR is on ARM2 mother board, so it should be config
well firstly. So we make sure SPI-NOR work successfully by default. But if
enable epdc , SPI-NOR on ARM2 will work fail.
make shi [Tue, 21 Aug 2012 09:51:18 +0000 (17:51 +0800)]
ENGR00220833 mx6sl: USB hsic: enable mx6sl hsic function
- Set MX6SL_PAD_HSIC_DAT and MX6SL_PAD_HSIC_STROBE pad DDR attribute as DDR3
- Add imx6sl_add_fsl_ehci_hs and imx6sl_add_fsl_usb2_hs_wakeup in usb_h2.c
Anson Huang [Sat, 18 Aug 2012 17:12:59 +0000 (01:12 +0800)]
ENGR00220370 [MX6]Fix BUS freq suspend/resume fail in low bus mode
1. BUS freq's set low bus setpoint using delat work, which
didn't have mutex lock, so in some scenarios, set high bus
freq function can be called at the same time, we need to move
mutex lock into these two routine;
2. Using pm notify to make sure bus freq set to high setpoint
before supend and restore after resume.
Rong Dian [Mon, 20 Aug 2012 12:23:00 +0000 (20:23 +0800)]
ENGR00220794 imx6 thermal: add suspend and resume for thermal_sys class
1.Avoiding system wrong reboot caused by error temperature without
cancel_delayed_work before entering into suspend,so to cancel
thermal_zone_device temperature polling temperature delayed_work
before entering into suspend, reenable polling temperature delayed_work
after entering into resume.
2.In anatop_thermal_suspend, turn off alarm firstly
make shi [Tue, 14 Aug 2012 07:02:00 +0000 (15:02 +0800)]
ENGR00218789 mx6: clock: keep PLL3 enable and power bit all the time
In order to support USB remote wake up, we should keep the PLL3 enable
and power bit all the time. We use BM_ANADIG_ANA_MISC2_CONTROL0 to control
the PLL3 power off PLL3's power when PLL3 is not used by other module.
PLL3 power design logic as below:
usb1_pll_480_ctrl_power_int=hw_anadig_usb1_pll_480_ctrl_power && ((disable_480_p
ll_n && ~hw_anadig_ana_misc2_control0 )||pwrctl_otg_wakeup || utmi_otg_suspendm)
There are two basic case:
- If USB is active and USB remote wakeup happen , Pll3 will be turn on.
- If USB is not active and no remote wakeup happen, the PLL3 will be controlled
by hw_anadig_ana_misc2_control0 bit.
ENGR00220818 [MX6SL] - Ensure the Enable bit is set for all the PLLs.
The ENABLE bit is not set for all PLLs by default. Ensure
that the pll_enable() function sets this bit for all PLLs.
The pll_disable() function should not clear this bit
for PLL1, PLL2, PLL3 and PLL7. The output of these PLLs
maybe used even if they are bypassed.
Hongzhang Yang [Mon, 20 Aug 2012 08:11:21 +0000 (16:11 +0800)]
ENGR00220732-1 Remove clk_disable in VPU driver interrupt handling
Original design is VPU lib API StartOneFrame() enables clock, and VPU
driver disables clock after codec done interrupt has been received.
However there are known issues of interrupt handling as below:
- VPU interrupt handling callback is not scheduled in time causing work
queue overflow
- JPU done interrupt is not received because JPU issues it while JPU
buffer empty interrupt is still being served
- VPU finishes a frame (!vpu_IsBusy) but VPU done interrupt is not
received
All above will cause clk_disable in interrupt handling not called,
thus VPU clock count increases by 1.
So I plan to resolve clock unbalance issue first by removing
clk_disable from VPU driver interrupt handling. Interrupt problem
will not affect clock issue any longer.
1. Driver: remove clk_disable from vpu_worker_callback
2.1. Lib: remove clk_enable from API GetOutputInfo
2.2. Lib: avoid disabling VPU clock when VPU is busy in SWReset
3. Test: replace GetOutputInfo with SWReset in decoder_close /
encoder_close
Signed-off-by: Hongzhang Yang <Hongzhang.Yang@freescale.com>
Lionel Xu [Fri, 17 Aug 2012 08:06:32 +0000 (16:06 +0800)]
ENGR00220446 ESAI: channel swapped occasionally when playing stereo wav
There is channel swap happened when playing stereo wav. According to the spec,
the initial words should be written to the ETDR register, at least one word
per enabled transmitter slot, to avoid any potential problem.
Yuxi Sun [Sat, 18 Aug 2012 06:43:26 +0000 (14:43 +0800)]
ENGR00220706 IPU Add more timeout when wait for the csi end of frame
If this timeout is too small, it can't meet the require of some large
frame such as 2592x1944 and 1080p, and the IDMAC maybe in a chaotic
state, so at last access some invalid space caused the system hang.
ENGR00220496 MX6SL:Add low power IDLE mode optimizations.
Add support for DDR freq change code in IRAM.
Change PLL2 to bypass mode so that DDR is running off 24MHz OSC
directly.
ARM is now sourced from PLL1 (running at 800MHz) in this mode.
This is required for the next step in IDLE mode optmization
where all PLLs will be disabled when ARM enters WFI.
projects / karo-tx-linux.git / log