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9 years agopowerpc/mpc85xx: use correct dma compatible for several SoCs
Tudor Laurentiu [Thu, 20 Nov 2014 10:09:31 +0000 (12:09 +0200)]
powerpc/mpc85xx: use correct dma compatible for several SoCs

Newer qoriq socs have an updated dma ip block with a
different compatible. Let's make sure we use the proper
string so that the dmas get their liodn.
In order to have the means to specify the compatible
string, the liodn setting macros were updated to receive
a new parameter for it.
The following SoCs were changed to use the new compatible:
 T1023/4, T1040, T2080/1, T4240, B4860.

Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agoboard/t1024qds: add retimer support on t1024qds
Shengzhou Liu [Mon, 24 Nov 2014 09:18:28 +0000 (17:18 +0800)]
board/t1024qds: add retimer support on t1024qds

Initialize retimer for XFI on t1024qds.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agot1024qds: increase IO drive strength
Shengzhou Liu [Mon, 24 Nov 2014 09:12:00 +0000 (17:12 +0800)]
t1024qds: increase IO drive strength

Increase IO drive strength to fix FCS error on RGMII ports
on T1024QDS.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agonet/phy: enable serdes auto-negotiation for vsc8514 phy
Shengzhou Liu [Mon, 24 Nov 2014 09:11:59 +0000 (17:11 +0800)]
net/phy: enable serdes auto-negotiation for vsc8514 phy

VSC8514 QSGMII PHY requires enabling auto-negotiation,
otherwise it wouldn't work.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agoboard/t1024qds: update pin multiplexing
Shengzhou Liu [Mon, 24 Nov 2014 09:11:58 +0000 (17:11 +0800)]
board/t1024qds: update pin multiplexing

Add multiplexing support among SPI flash, TDM riser card and SDXC.
it routes SPI pins to SPI flash by default.
Route SPI pins to SD slot if "adaptor=sdxc" is set in hwconfig.
Route SPI pins to TDM riser card and do fixup for dts if "pin_mux=tdm"
is set in hwconfig.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Xie Xiaobo <X.Xie@freescale.com>
Signed-off-by: Zhao Qiang <B45475@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agonet/fman: update 10GEC to fit new SoC
Shengzhou Liu [Mon, 24 Nov 2014 09:11:57 +0000 (17:11 +0800)]
net/fman: update 10GEC to fit new SoC

fm_standard_init() initializes each 10G port by FM_TGEC_INFO_INITIALIZER.
but it needs different implementation of FM_TGEC_INFO_INITIALIZER on different SoCs.
on SoCs earlier(e.g. T4240, T2080), the notation between 10GEC and MAC as below:
10GEC1->MAC9, 10GEC2->MAC10, 10GEC3->MAC1, 10GEC4->MAC2
on SoCs later(e.g. T1024, etc), the notation between 10GEC and MAC as below:
10GEC1->MAC1, 10GEC2->MAC2

so we introduce CONFIG_FSL_FM_10GEC_REGULAR_NOTATION to fit the new SoCs on
which 10GEC enumeration is consistent with MAC enumeration.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agopowerpc/t1024rdb: Add T1024 RDB board support
Shengzhou Liu [Mon, 24 Nov 2014 09:11:56 +0000 (17:11 +0800)]
powerpc/t1024rdb: Add T1024 RDB board support

T1024RDB is a Freescale Reference Design Board that hosts the T1024 SoC.

T1024RDB board Overview
-----------------------
- T1024 SoC integrating two 64-bit e5500 cores up to 1.4GHz
- CoreNet fabric supporting coherent and noncoherent transactions with
  prioritization and bandwidth allocation
- 32-/64-bit DDR3L SDRAM memory controller with ECC and interleaving support
- Accelerator: DPAA components consist of FMan, BMan, QMan, DCE and SEC
- Ethernet interfaces:
  - Two 10M/100M/1G RGMII ports on-board
  - one 10Gbps XFI interface
- PCIe: Three PCIe controllers: one PCIe Slot and two Mini-PCIe connectors.
- SerDes: 4 lanes up to 10.3125GHz
- IFC: 128MB NOR Flash, 512MB NAND Flash and CPLD
- eSPI: 64MB N25Q512 SPI flash.
- Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)
- USB: Two  Type-A USB2.0 ports with internal PHY
- eSDHC: Support SD, SDHC, SDXC and MMC/eMMC
- I2C: Four I2C controllers
- UART: Two UART serial ports

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
[York Sun: Fix ft_board_setup() type, fix MAINTAINERS for SECURE_BOOT
   Fix Kconfig by adding SUPPORT_SPL]
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agopowerpc/t1024qds: Add T1024 QDS board support
Shengzhou Liu [Mon, 24 Nov 2014 09:11:55 +0000 (17:11 +0800)]
powerpc/t1024qds: Add T1024 QDS board support

T1024QDS is a high-performance computing evaluation, development and
test platform for T1024 QorIQ Power Architecture processor.

T1024QDS board Overview
-----------------------
- T1024 SoC integrating two 64-bit e5500 cores up to 1.4GHz
- CoreNet fabric supporting coherent and noncoherent transactions with
  prioritization and bandwidth allocation
- 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support
- Accelerator: DPAA components consist of FMan, BMan, QMan, DCE and SEC
- Ethernet interfaces:
  - Two 10M/100M/1G RGMII ports on-board
  - Three 1G/2.5Gbps SGMII ports
  - Four 1Gbps QSGMII ports
  - one 10Gbps XFI or 10Base-KR interface
- SerDes: 4 lanes up to 10.3125GHz Supporting SGMII/QSGMII, XFI, PCIe, SATA and Aurora
- PCIe: Three PCI Express controllers with five PCIe slots.
- IFC: 128MB NOR Flash, 2GB NAND Flash, PromJet debug port and Qixis FPGA
- Video: DIU supports video up to 1280x1024x32 bpp.
  - Chrontel CH7201 for HDMI connection.
  - TI DS90C387R for direct LCD connection.
  - Raw (not encoded) video connector for testing or other encoders.
- QUICC Engine block
  - 32-bit RISC controller for flexible support of the communications peripherals
  - Serial DMA channel for receive and transmit on all serial channels
  - Two universal communication controllers, supporting TDM, HDLC, and UART
- Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)
- eSPI: Three SPI flash devices.
- SATA: one SATA 2.O.
- USB: Two USB2.0 ports with internal PHY (one Type-A + one micro Type mini-AB)
- eSDHC: Support SD, SDHC, SDXC and MMC/eMMC.
- I2C: Four I2C controllers.
- UART: Two UART on board.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
[York Sun: Fix ft_board_setup() type, fix MAINTAINERS for SECURE_BOOT
   Fix Kconfig by adding SUPPORT_SPL]
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agopowerpc/mpc85xx: Add T1024/T1023 SoC support
Shengzhou Liu [Mon, 24 Nov 2014 09:11:54 +0000 (17:11 +0800)]
powerpc/mpc85xx: Add T1024/T1023 SoC support

Add support for Freescale T1024/T1023 SoC.

The T1024 SoC includes the following function and features:
- Two 64-bit Power architecture e5500 cores, up to 1.4GHz
- private 256KB L2 cache each core and shared 256KB CoreNet platform cache (CPC)
- 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support
- Data Path Acceleration Architecture (DPAA) incorporating acceleration
- Four MAC for 1G/2.5G/10G network interfaces (RGMII, SGMII, QSGMII, XFI)
- High-speed peripheral interfaces
  - Three PCI Express 2.0 controllers
- Additional peripheral interfaces
  - One SATA 2.0 controller
  - Two USB 2.0 controllers with integrated PHY
  - Enhanced secure digital host controller (SD/eSDHC/eMMC)
  - Enhanced serial peripheral interface (eSPI)
  - Four I2C controllers
  - Four 2-pin UARTs or two 4-pin UARTs
  - Integrated Flash Controller supporting NAND and NOR flash
- Two 8-channel DMA engines
- Multicore programmable interrupt controller (PIC)
- LCD interface (DIU) with 12 bit dual data rate
- QUICC Engine block supporting TDM, HDLC, and UART
- Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)
- Support for hardware virtualization and partitioning enforcement
- QorIQ Platform's Trust Architecture 2.0

Differences between T1024 and T1023:
  Feature         T1024  T1023
  QUICC Engine:   yes    no
  DIU:            yes    no
  Deep Sleep:     yes    no
  I2C controller: 4      3
  DDR:            64-bit 32-bit
  IFC:            32-bit 28-bit

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agodriver/ddr/fsl: Add workaround for faulty SPD
York Sun [Sat, 15 Nov 2014 01:17:50 +0000 (17:17 -0800)]
driver/ddr/fsl: Add workaround for faulty SPD

Some UDIMMs have faulty SPD with wrong mapping for DQ[36-39].
Using raw card spec in case this error is detected.

Signed-off-by: York Sun <yorksun@freescale.com>
9 years agopowerpc/mpc85xx: Update LIODN entries for T1040
Priyanka Jain [Tue, 18 Nov 2014 05:23:49 +0000 (10:53 +0530)]
powerpc/mpc85xx: Update LIODN entries for T1040

Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agopowerpc/t2080: updating rcw for silicon v1.1
Shengzhou Liu [Fri, 14 Nov 2014 02:31:22 +0000 (10:31 +0800)]
powerpc/t2080: updating rcw for silicon v1.1

T2080 v1.1 requires different MEM_PLL_RAT from previous v1.0,
and also update core frequency to 1.8GHz for v1.1.
We reserve the support for T2080 v1.0 and enable v1.1 by default.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agoB4860QDS: Enable enet port as per fsl_b4860_serdes2 string in hwconfig
Suresh Gupta [Thu, 13 Nov 2014 03:28:09 +0000 (11:28 +0800)]
B4860QDS: Enable enet port as per fsl_b4860_serdes2 string in hwconfig

In B4860QDS board SerDes2 lanes EFGH either go to SFP or AMC riser card
slot2 so either DTSEC3/DTSEC4 or TGEC1/TGEC2 should be accessible. This
Patch enables DTSEC3/DTSEC4 or TGEC1/TGEC2 on bases of user specified
string fsl_b4860_serdes2:sfp_amc=amc or fsl_b4860_serdes2:sfp_amc=sfp
respectively in hwconfig.

Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agopowerpc/b4860qds: add workaround for XFI
Shaohui Xie [Thu, 13 Nov 2014 03:27:49 +0000 (11:27 +0800)]
powerpc/b4860qds: add workaround for XFI

XFI does not work stable on current board, it's due to heat sink issue,
to make it work stable the board needs additional heat sink, enable two
XFI lanes only. Right now we do not have such an erratum for the issue,
so use a define CONFIG_SYS_FSL_B4860QDS_XFI_ERR to identify it.
The workaround will only be used in XFI protocols and only if the
hwconfig indicates that XFI is prefered.

A new VSC3308 config function is used instead of re-use the original
function, to avoid making the function complex and ugly.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agoB4860QDS: Enable SFP or AMC on basis of hwconfig string
Suresh Gupta [Thu, 13 Nov 2014 03:27:32 +0000 (11:27 +0800)]
B4860QDS: Enable SFP or AMC on basis of hwconfig string

SerDes2 lanes EFGH either go to SFP or AMC riser card slot2.
By default AMC will be configured even if no hwconfig is specified.

To enable XFI via SFP use the below hwconfig:
fsl_b4860_serdes2:sfp_amc=sfp

Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@ffeescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agopowerpc/b4860qds: dtb fixup for xfi
Shaohui Xie [Thu, 13 Nov 2014 03:27:12 +0000 (11:27 +0800)]
powerpc/b4860qds: dtb fixup for xfi

Since xfi has no phy, we delete the property "phy-handle" and use
a "fixed-link" property for a xfi port.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agopowerpc/b4860qds: add xfi support
Shaohui Xie [Thu, 13 Nov 2014 03:26:19 +0000 (11:26 +0800)]
powerpc/b4860qds: add xfi support

We need following changes to make xfi work on B4:
1. set cross-point switch VSC3308 to use sfp config when running xfi;
2. add 10G interface check for xfi;
3. set phy address for xfi so the 10G ports can be registered by mdio;

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agoB4860: Add alternate LC VCO serdes protocols support in board file
Shaveta Leekha [Wed, 12 Nov 2014 10:30:44 +0000 (16:00 +0530)]
B4860: Add alternate LC VCO serdes protocols support in board file

Add the support of newly added LC VCO SerDes protocols
for configuration of IDT and VSC crossbar

Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agoB4860QDS: SGMII related updates
Shaveta Leekha [Wed, 12 Nov 2014 10:30:22 +0000 (16:00 +0530)]
B4860QDS: SGMII related updates

- Enable SGMII support for 0x8d Serdes 2 protocol.
    - Correct Phy address for DTSECx for 0x8d/0xb2 Serdes 2 protocol.
    - Updated debug statement
    - Add Alternate LC VCO protocols(0x8d-->0x8c, 0xb2-->0xb1)
    - Rename onboard PHY address defines for more readability
    - Add these new Defines in B4860QDS.h file

Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years ago85xx/b4860: Add alternate serdes protocols for B4860/B4420
Shaveta Leekha [Wed, 12 Nov 2014 10:32:25 +0000 (16:02 +0530)]
85xx/b4860: Add alternate serdes protocols for B4860/B4420

Addded Alternate options with LC VCO for following protocols:
0x02 --> 0x01
0x08 --> 0x07
0x18 --> 0x17
0x1E --> 0x1D
0x49 --> 0x48
0x6F --> 0x6E
0x9A --> 0x99
0x9E --> 0x9D

Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agopowerpc/b4860: Enable law creation of MAPLE
Shaveta Leekha [Wed, 12 Nov 2014 08:53:26 +0000 (14:23 +0530)]
powerpc/b4860: Enable law creation of MAPLE

B4860, B4440, B4420 and B4220 have MAPLE, so enable law creation
for them only. Remove static LAW creation for MAPLE.

Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Sandeep Singh <Sandeep@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agopowerpc/t104x: Convert to use generic board code
vijay rai [Tue, 18 Nov 2014 06:51:13 +0000 (12:21 +0530)]
powerpc/t104x: Convert to use generic board code

Convert T1040QDS and T1040RDB to use generic board code.

Signed-off-by: Vijay Rai <vijay.rai@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agonet/phy: Add support for CS4315/CS4340 PHY
Shengzhou Liu [Mon, 10 Nov 2014 10:32:29 +0000 (18:32 +0800)]
net/phy: Add support for CS4315/CS4340 PHY

Add support for Cortina CS4315/CS4340 10G PHY.
- This driver loads CS43xx firmware from NOR/NAND/SPI/SD device
  to initialize Cortina PHY.
- Cortina PHY has non-standard offset of PHY ID registers, thus
  we define own get_phy_id() to override default get_phy_id().
- To define macro CONFIG_PHY_CORTINA will enable this driver.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agodriver/ddr/fsl: Adjust timing_cfg_0 to better support two DDR slots
York Sun [Fri, 7 Nov 2014 20:14:36 +0000 (12:14 -0800)]
driver/ddr/fsl: Adjust timing_cfg_0 to better support two DDR slots

Increase write-to-write and read-to-read turnaround time for two-slot DDR
configurations. Previously only quad-rank and two dual-rank configurations
have this additional turnaround time. A recent test on two single-rank
DIMMs shows the shorter additional turnaround time is also needed.

Signed-off-by: York Sun <yorksun@freescale.com>
9 years agopowerpc/c29xpcie: Enable configs to use generic board code
Chunhe Lan [Fri, 7 Nov 2014 07:39:56 +0000 (15:39 +0800)]
powerpc/c29xpcie: Enable configs to use generic board code

Add configs:
  o CONFIG_SYS_GENERIC_BOARD
  o CONFIG_DISPLAY_BOARDINFO
in C29XPCIE config header file to use U-boot generic
board code.

Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agopowerpc/p1023rdb: Enable configs to use generic board code
Chunhe Lan [Fri, 7 Nov 2014 07:15:49 +0000 (15:15 +0800)]
powerpc/p1023rdb: Enable configs to use generic board code

Add configs:
  o CONFIG_SYS_GENERIC_BOARD
  o CONFIG_DISPLAY_BOARDINFO
in P1023RDB config header file to use U-boot generic
board code.

Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agompc85xx/p1022ds: convert to generic board
Tang Yuantian [Fri, 7 Nov 2014 06:46:18 +0000 (14:46 +0800)]
mpc85xx/p1022ds: convert to generic board

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agopowerpc, muas3001: remove CONFIG_SYS_RAMBOOT
Heiko Schocher [Thu, 6 Nov 2014 14:20:52 +0000 (15:20 +0100)]
powerpc, muas3001: remove CONFIG_SYS_RAMBOOT

cppcheck reports:

[board/muas3001/muas3001.c:270]: (error) Uninitialized variable: psize

remove the CONFIG_SYS_RAMBOOT define to prevent this error report.

Signed-off-by: Heiko Schocher <hs@denx.de>
Reported-by: Wolfgang Denk <wd@denx.de>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agokm/km82xx: remove CONFIG_SYS_RAMBOOT
Holger Brunck [Thu, 6 Nov 2014 13:54:18 +0000 (14:54 +0100)]
km/km82xx: remove CONFIG_SYS_RAMBOOT

This define is never set in our setup, so we can remove it safely. The
former code causes cppcheck to complain about:
[board/keymile/km82xx/km82xx.c:311]: (error) Uninitialized variable:
psize

Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
cc: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Wolfgang Denk <wd@denx.de>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agoboard/freescale: use generic board architecture for p1010rdb
Ying Zhang [Thu, 6 Nov 2014 05:05:08 +0000 (13:05 +0800)]
board/freescale: use generic board architecture for p1010rdb

Use generic board architecture for p1010rdb, tested with NOR
boot on p1010rdb-pb.

Signed-off-by: Ying Zhang <b40530@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agopowerpc/P5040DS: enable SATA support
Shaohui Xie [Tue, 4 Nov 2014 11:53:30 +0000 (19:53 +0800)]
powerpc/P5040DS: enable SATA support

The define CONFIG_FSL_SATA_V2 is missing, so SATA is not available
in U-boot.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agoboard/freescale: use generic board architecture for p1025-twr
Ying Zhang [Tue, 4 Nov 2014 07:10:46 +0000 (15:10 +0800)]
board/freescale: use generic board architecture for p1025-twr

Use generic board architecture for p1025-twr, tested with NOR
boot and NAND boot on p1025-twr.

Signed-off-by: Ying Zhang <b40530@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agopowerpc/t208xqds: VID support
Ying Zhang [Fri, 31 Oct 2014 10:06:18 +0000 (18:06 +0800)]
powerpc/t208xqds: VID support

The fuse status register provides the values from on-chip
voltage ID efuses programmed at the factory.
These values define the voltage requirements for
the chip. u-boot reads FUSESR and translates the values
into the appropriate commands to set the voltage output
value of an external voltage regulator.

Signed-off-by: Ying Zhang <b40530@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agopowerpc/mpc85xx: modify erratum A007186
Zhao Qiang [Thu, 30 Oct 2014 06:07:39 +0000 (14:07 +0800)]
powerpc/mpc85xx: modify erratum A007186

T2080 v1.0 has this errata while v1.1 has fixed
this errata by hardware, add a new function has_errata_a007186
to check the SVR_SOC_VER, SVR_MAJ and SVR_MIN first,
if the sil has errata a007186, then run the errata code,
if not, doesn't run the code.

Signed-off-by: Zhao Qiang <B45475@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agoboard/t104xrdb: Conditional workaround of errata A-008044
Prabhakar Kushwaha [Wed, 29 Oct 2014 17:03:55 +0000 (22:33 +0530)]
board/t104xrdb: Conditional workaround of errata A-008044

Workaround of Errata A-008044 was implemented without errata number and it is
enabled by default. Errata A-008044 is only valid for T1040 Rev 1.0.

So put errata number and make it conditional.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agopowerpc/mpc85xx:Put errata number for T104x NAND boot issue
Prabhakar Kushwaha [Wed, 29 Oct 2014 17:03:09 +0000 (22:33 +0530)]
powerpc/mpc85xx:Put errata number for T104x NAND boot issue

When device is configured to load RCW from NAND flash IFC_A[16:31] are driven
low after RCW loading. Hence Devices connected on IFC_CS[1:7] and using
IFC_A[16:31] lines are not accessible.

Workaround is already in-place.
Put the errata number to adhere errata handling framework.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agopowerpc/t1040qds: Update DDR option
York Sun [Mon, 27 Oct 2014 18:45:11 +0000 (11:45 -0700)]
powerpc/t1040qds: Update DDR option

Enable interactive debugging by default. Remove DDR controller interleaving
because this SoC only has one controller. Use auto chip-select interleaving
to detect number of ranks.

Signed-off-by: York Sun <yorksun@freescale.com>
CC: Poonam Aggrwal <poonam.aggrwal@freescale.com>
9 years agompc85xx/t2080: Fix parsing DDR ratio for new revision
York Sun [Mon, 27 Oct 2014 18:31:33 +0000 (11:31 -0700)]
mpc85xx/t2080: Fix parsing DDR ratio for new revision

T2080 rev 1.1 changes MEM_RAT in RCW, which requires new parsing for ratio,
the same way as T4240 rev 2.0.

Signed-off-by: York Sun <yorksun@freescale.com>
CC: Shengzhou Liu <Shengzhou.Liu@freescale.com>
9 years agompc85xx/t208xqds: Adjust DDR timing parameters
York Sun [Mon, 27 Oct 2014 18:31:32 +0000 (11:31 -0700)]
mpc85xx/t208xqds: Adjust DDR timing parameters

Adjust timing for dual-rank UDIMM, verified on M3CQ-8GHS3C0E for speed of
1066, 1333, 1600, 1866MT/s. The 1866 timing is copied to 2133 timing in
case such DIMM comes available.

Also update single-rank 1866 timing. Enable interactive debugging as well.

Signed-off-by: York Sun <yorksun@freescale.com>
CC: Shengzhou Liu <Shengzhou.Liu@freescale.com>
9 years agopowerpc/t2080: add serdes2 protocol 0x2e
Shengzhou Liu [Mon, 27 Oct 2014 02:08:16 +0000 (10:08 +0800)]
powerpc/t2080: add serdes2 protocol 0x2e

Add serdes2 protocol 0x2e.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agoFreescale t104x: Do not exclude SGMII
Joakim Tjernlund [Fri, 24 Oct 2014 14:49:02 +0000 (16:49 +0200)]
Freescale t104x: Do not exclude SGMII

fman_port_enet_if() tests if FM1_DTSEC2 or FM1_DTSEC4 uses
RGMII or MII and if not returns PHY_INTERFACE_MODE_NONE.
This excludes testing for SGMII further down.

Remove the unconditional "else return PHY_INTERFACE_MODE_NONE"
so SGMII can be tested too.

Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agocommon: spl: Add interactive DDR debugger support for SPL image
Alison Wang [Wed, 3 Dec 2014 07:00:44 +0000 (15:00 +0800)]
common: spl: Add interactive DDR debugger support for SPL image

To support interactive DDR debugger, cli_simple.o, cli.o, cli_readline.o,
command.o, s_record.o, xyzModem.o and cmd_disk.o are all needed for
drivers/ddr/fsl/interactive.c.

In current common/Makefile, the above .o files are only produced when
CONFIG_SPL_BUILD is disabled.

For LS102xA, interactive DDR debugger is needed in SD/NAND boot too, and
I enabled CONFIG_FSL_DDR_INTERACTIVE. But according to the current
common/Makfile, all the above .o files are not produced in SPL part
because CONFIG_SPL_BUILD is enabled in SPL part, the following error
will be shown,

drivers/ddr/fsl/built-in.o: In function `fsl_ddr_interactive':
/home/wangh/layerscape/u-boot/drivers/ddr/fsl/interactive.c:1871:
undefined reference to `cli_readline_into_buffer'
/home/wangh/layerscape/u-boot/drivers/ddr/fsl/interactive.c:1873:
undefined reference to `cli_simple_parse_line'
make[1]: *** [spl/u-boot-spl] Error 1
make: *** [spl/u-boot-spl] Error 2

So this patch fixed this issue and the above .o files will be produced
no matter CONFIG_SPL_BUILD is enabled or disabled.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agoMerge branch 'master' of git://git.denx.de/u-boot-mips
Tom Rini [Thu, 27 Nov 2014 15:49:38 +0000 (10:49 -0500)]
Merge branch 'master' of git://git.denx.de/u-boot-mips

9 years agoMIPS: bootm: remove unused or redundant header files
Daniel Schwierzeck [Sun, 16 Nov 2014 00:27:23 +0000 (01:27 +0100)]
MIPS: bootm: remove unused or redundant header files

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
9 years agoMIPS: bootm: add missing initramfs relocation
Daniel Schwierzeck [Sun, 16 Nov 2014 00:27:23 +0000 (01:27 +0100)]
MIPS: bootm: add missing initramfs relocation

The initramfs is currently only relocated if the user calls
the bootm ramdisk subcommand. If bootm should be used without
subcommands, the arch-specific bootm code needs to implement
the relocation.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
9 years agoMIPS: remove board.c
Daniel Schwierzeck [Sat, 15 Nov 2014 22:46:58 +0000 (23:46 +0100)]
MIPS: remove board.c

After all MIPS boards are switched to generic-board, the
MIPS specific board.c can be removed.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
9 years agoMIPS: vct: switch to generic board
Daniel Schwierzeck [Sat, 15 Nov 2014 22:30:01 +0000 (23:30 +0100)]
MIPS: vct: switch to generic board

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Acked-by: Stefan Roese <sr@denx.de>
9 years agoMIPS: qemu_mips: switch to generic board
Daniel Schwierzeck [Sat, 15 Nov 2014 22:30:01 +0000 (23:30 +0100)]
MIPS: qemu_mips: switch to generic board

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
9 years agoMIPS: pb1x00: switch to generic board
Daniel Schwierzeck [Sat, 15 Nov 2014 22:30:01 +0000 (23:30 +0100)]
MIPS: pb1x00: switch to generic board

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
9 years agoMIPS: dbau1x00: switch to generic board
Daniel Schwierzeck [Sat, 15 Nov 2014 22:30:01 +0000 (23:30 +0100)]
MIPS: dbau1x00: switch to generic board

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
9 years agoMIPS: fix setup of initial stack frame
Daniel Schwierzeck [Thu, 20 Nov 2014 22:55:32 +0000 (23:55 +0100)]
MIPS: fix setup of initial stack frame

To get correct stack walking and backtrace functionality in gdb,
registers fp and ra should be initialized before calling board_init_f
or board_init_r. Thus allocating stack space and zeroing it as it is
currently done in board.c becomes obsolete.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
9 years agomtd: nand: s3c: Unify the register definition and naming
Marek Vasut [Sat, 11 Oct 2014 16:42:52 +0000 (18:42 +0200)]
mtd: nand: s3c: Unify the register definition and naming

Merge struct s3c2410_nand and struct s3c2440_nand into one unified
struct s3c24x0_nand. While at it, fix up and rename the functions
to retrieve the NAND base address and fix up the s3c NAND driver to
reflect this change.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Vladimir Zapolskiy <vz@mleia.com>
9 years agomtd/nand/vf610_nfc: Disable subpage writes
Sanchayan Maity [Mon, 24 Nov 2014 05:33:59 +0000 (11:03 +0530)]
mtd/nand/vf610_nfc: Disable subpage writes

This patch disables subpage writes for vf610_nfc nand
driver. This is required, as without this fix, writing
unaligned u-boot images with DFU results in a hang.
Trying to write unalgined binary images also results
in a hang, without disabling subpage writes.

Patch has been tested on a Colibri VF61 module.

Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
9 years agomtd: denali: set some registers after nand_scan_ident()
Masahiro Yamada [Thu, 13 Nov 2014 11:31:51 +0000 (20:31 +0900)]
mtd: denali: set some registers after nand_scan_ident()

Some but not all of implementations of the Denali NAND controller
have hardware circuits to detect the device parameters such as
page_size, erase_size, etc.  Even on those SoCs with such hardware
supported, the hardware is known to detect wrong parameters for some
nasty (almost buggy) NAND devices.  The device parameters detected
during nand_scan_ident() are more trustworthy.

This commit sets some hardware registers to mtd->pagesize,
mtd->oobsize, etc. in the code between nand_scan_ident() and
nand_scan_tail().

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Chin Liang See <clsee@altera.com>
9 years agomtd: denali: use CONFIG_SYS_NAND_SELF_INIT
Masahiro Yamada [Thu, 13 Nov 2014 11:31:50 +0000 (20:31 +0900)]
mtd: denali: use CONFIG_SYS_NAND_SELF_INIT

Some variants of the Denali NAND controller need some registers
set up based on the device information that has been detected during
nand_scan_ident().

CONFIG_SYS_NAND_SELF_INIT has to be defined to insert code between
nand_scan_ident() and nand_scan_tail().  It is also helpful to reduce
the difference between this driver and its Linux counterpart because
this driver was ported from Linux.  Moreover, doc/README.nand recommends
to use CONFIG_SYS_NAND_SELF_INIT.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Chin Liang See <clsee@altera.com>
9 years agonand: reinstate lazy bad block scanning
Rostislav Lisovy [Wed, 22 Oct 2014 11:40:44 +0000 (13:40 +0200)]
nand: reinstate lazy bad block scanning

Commit ff94bc40af3481d47546595ba73c136de6af6929
("mtd, ubi, ubifs: resync with Linux-3.14")
accidentally reverted part of the commit
13f0fd94e3cae6f8a0d9fba5d367e311edc8ebde
("NAND: Scan bad blocks lazily.").

Reinstate the change as by commit
fb49454b1b6c7c6e238ac3c0b1e302e73eb1a1ea
("nand: reinstate lazy bad block scanning")

Signed-off-by: Rostislav Lisovy <lisovy@merica.cz>
Acked-by: Heiko Schocher <hs@denx.de>
9 years agoMerge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq
Tom Rini [Tue, 25 Nov 2014 21:51:47 +0000 (16:51 -0500)]
Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq

9 years agoMerge branch 'master' of git://git.denx.de/u-boot-mpc85xx
Tom Rini [Wed, 26 Nov 2014 16:22:29 +0000 (11:22 -0500)]
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

Conflicts:
drivers/mmc/fsl_esdhc.c

Signed-off-by: Tom Rini <trini@ti.com>
9 years agospl: Fix SPL EXT support
Guillaume GARDET [Tue, 25 Nov 2014 14:34:16 +0000 (15:34 +0100)]
spl: Fix SPL EXT support

Commit 9f12cd0e062614e19734b2ab37842d387457c5e5 has broken SPL EXT support.
This patch update error code check to get SPL EXT support working again.

Tested on a Pandaboard (rev. A3).

Reviewed-by: Suriyan Ramasami <suriyan.r@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Guillaume GARDET <guillaume.gardet@free.fr>
Cc: Tom Rini <trini@ti.com>
9 years agoMerge branch 'master' of http://git.denx.de/u-boot-samsung
Tom Rini [Tue, 25 Nov 2014 16:10:01 +0000 (11:10 -0500)]
Merge branch 'master' of http://git.denx.de/u-boot-samsung

9 years agoMerge branch 'master' of http://git.denx.de/u-boot-sunxi
Tom Rini [Tue, 25 Nov 2014 16:09:48 +0000 (11:09 -0500)]
Merge branch 'master' of http://git.denx.de/u-boot-sunxi

9 years agoMerge git://git.denx.de/u-boot-fdt
Tom Rini [Tue, 25 Nov 2014 16:08:52 +0000 (11:08 -0500)]
Merge git://git.denx.de/u-boot-fdt

9 years agosun7i: Set ARMV7_BOOT_SEC_DEFAULT when OLD_SUNXI_KERNEL_COMPAT is set
Hans de Goede [Fri, 24 Oct 2014 18:12:04 +0000 (20:12 +0200)]
sun7i: Set ARMV7_BOOT_SEC_DEFAULT when OLD_SUNXI_KERNEL_COMPAT is set

Old kernels cannot handle booting in non-secure (hyp) mode, so when
OLD_SUNXI_KERNEL_COMPAT is set, also set ARMV7_BOOT_SEC_DEFAULT.

Note that whether to booting secure or non-secure can always be overriden
using the bootm_boot_mode environment variable.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
9 years agosun7i: Drop CONFIG_ARMV7_PSCI_NR_CPUS
Hans de Goede [Fri, 24 Oct 2014 14:38:05 +0000 (16:38 +0200)]
sun7i: Drop CONFIG_ARMV7_PSCI_NR_CPUS

It is not used anywhere.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
9 years agosun6i: Drop some "unknown magic" from dram init
Hans de Goede [Sat, 15 Nov 2014 22:19:42 +0000 (23:19 +0100)]
sun6i: Drop some "unknown magic" from dram init

Allwinner tells us that this bit of code is the rtc ram being used to detect
coming out of "super-standby" mode, and if that is the case, going out of
self-refresh mode.

Since we do not support "super-standby" mode, this can be dropped.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
9 years agosun6i: Add gmac support for sun6i boards
Hans de Goede [Fri, 21 Nov 2014 16:19:45 +0000 (17:19 +0100)]
sun6i: Add gmac support for sun6i boards

Hookup the gmac found on the sun6i / A31 SoCs.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
9 years agosun6i: Correct Mele M9 Vbus gpio settings
Hans de Goede [Sun, 23 Nov 2014 11:33:20 +0000 (12:33 +0100)]
sun6i: Correct Mele M9 Vbus gpio settings

I noticed that the kernel and u-boot settings were different, double checking
has confirmed that the kernel settings are correct.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
9 years agosunxi: ahci: Add a delay after enabling target power
Hans de Goede [Fri, 14 Nov 2014 15:27:07 +0000 (16:27 +0100)]
sunxi: ahci: Add a delay after enabling target power

If the target power is connected through a gpio, then give the target some
time to power up before continuing with ahci / sata probing, this avoids
link timeouts, without penalizing other boards where there is no target
power gpio.

Why 500 ms ? I started with 200, that was not enough, then I went to 500 which
worked, lowering it to 350 broke things again, so 500 seems the minimum my
vertex2 needs to be ready to get probed.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
9 years agosunxi: Add usb keyboard Kconfig option
Hans de Goede [Thu, 18 Sep 2014 19:03:34 +0000 (21:03 +0200)]
sunxi: Add usb keyboard Kconfig option

For use together with the hdmi console.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ian.campbell@citrix.com>
9 years agosunxi: video: Add simplefb support
Luc Verhaegen [Wed, 13 Aug 2014 05:55:07 +0000 (07:55 +0200)]
sunxi: video: Add simplefb support

Add simplefb support, note this depends on the kernel having support for
the clocks property which has recently been added to the simplefb devicetree
binding.

Signed-off-by: Luc Verhaegen <libv@skynet.be>
[hdegoede@redhat.com: Use pre-populated simplefb node under /chosen as
 disussed on the devicetree list]
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>.
9 years agocommon/lcd: Make lcd_dt_simplefb_configure_node use fdt_setup_simplefb_node
Hans de Goede [Wed, 19 Nov 2014 12:53:27 +0000 (13:53 +0100)]
common/lcd: Make lcd_dt_simplefb_configure_node use fdt_setup_simplefb_node

Change lcd_dt_simplefb_configure_node into a wrapper around the new generic
fdt_setup_simplefb_node helper function.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Tested-by: Stephen Warren <swarren@wwwdotorg.org>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agofdt_support: Add a fdt_setup_simplefb_node helper function
Hans de Goede [Mon, 17 Nov 2014 14:29:11 +0000 (15:29 +0100)]
fdt_support: Add a fdt_setup_simplefb_node helper function

Add a generic helper to fill and enable simplefb nodes.

The first user of this will be the sunxi display code.

lcd_dt_simplefb_configure_node is also a good candidate to be converted
to use this, but that requires someone to run some tests first, as
lcd_dt_simplefb_configure_node does not honor #address-cells and #size-cells,
but simply assumes 1 and 1 for both.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Tested-by: Stephen Warren <swarren@wwwdotorg.org>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agosunxi: video: Add sun6i support
Hans de Goede [Fri, 14 Nov 2014 16:42:14 +0000 (17:42 +0100)]
sunxi: video: Add sun6i support

Besided needing the usual sun6i specific ahb1_reset bits poking, it turns out
that sun6i also needs the drc to be taken out of reset and clocked even though
it is in pass-through mode.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Anatolij Gustschin <agust@denx.de>
9 years agosunxi: video: Add cfb console driver for sunxi
Luc Verhaegen [Wed, 13 Aug 2014 05:55:06 +0000 (07:55 +0200)]
sunxi: video: Add cfb console driver for sunxi

This adds a fixed mode hdmi driver for the sunxi platform. The fixed
mode is a relatively safe 1024x768, more complete EDID handling is
currently not provided. Only HDMI is supported today.

This code is enabled when HPD detects an attached monitor.

Current config is such that 8MB is shaved off at the top of the RAM.
This avoids several memory handling issues, most significant is the fact
that on linux on ARM you are not allowed to remap known RAM as IO. A
clued in display driver will be able to recycle this reserved RAM in
future though.

cfbconsole was chosen as it provides the most important functionality: a
working u-boot console, allowing for the debugging of certain issues
without the need for a UART.

Signed-off-by: Luc Verhaegen <libv@skynet.be>
[hdegoede@redhat.com: Major cleanups and some small bugfixes]
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
9 years agosunxi: Add video pll clock functions
Hans de Goede [Sat, 8 Nov 2014 13:07:27 +0000 (14:07 +0100)]
sunxi: Add video pll clock functions

This is a preparation patch for adding support for HDMI out.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
9 years agosun4i: Rename dram_clk_cfg to dram_clk_gate
Hans de Goede [Sun, 9 Nov 2014 11:24:55 +0000 (12:24 +0100)]
sun4i: Rename dram_clk_cfg to dram_clk_gate

The data sheet just calls it DRAM_CLK_REG, and on sun6i we've both a
dram_clk_cfg and dram_clk_gate, and the sun4i reg matches dram_clk_gate on
sun6i, so name it the same on sun4i.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
9 years agoORIGEN: Enhance origen config to be more flexible on boot.
Guillaume GARDET [Wed, 8 Oct 2014 13:04:38 +0000 (15:04 +0200)]
ORIGEN: Enhance origen config to be more flexible on boot.

This patch enhances the boot of origen board by adding support to ext2, bootz, initrd, bootenv loading and boot script.
It still keeps the previous mmc load command if boot script fails.

Signed-off-by: Guillaume GARDET <guillaume.gardet@free.fr>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
9 years agoRevert "common/board_f: add setup of initial stack frame for MIPS"
Tom Rini [Mon, 24 Nov 2014 22:20:46 +0000 (17:20 -0500)]
Revert "common/board_f: add setup of initial stack frame for MIPS"

Daniel discovered a better solution to the problem this was solving, so
don't do what this patch was doing anymore.

This reverts commit 666ba8444e81c3785a427ae6922e2feededab9a3.

Signed-off-by: Tom Rini <trini@ti.com>
9 years agoPrepare v2015.01-rc2
Tom Rini [Mon, 24 Nov 2014 22:08:47 +0000 (17:08 -0500)]
Prepare v2015.01-rc2

Signed-off-by: Tom Rini <trini@ti.com>
9 years agoMerge branch 'master' of git://git.denx.de/u-boot-arm
Tom Rini [Mon, 24 Nov 2014 22:05:11 +0000 (17:05 -0500)]
Merge branch 'master' of git://git.denx.de/u-boot-arm

9 years agoarm: ls102xa: Select ge2_clk125 for eTSEC clock muxing
Alison Wang [Fri, 17 Oct 2014 07:26:36 +0000 (15:26 +0800)]
arm: ls102xa: Select ge2_clk125 for eTSEC clock muxing

EC1 pins in RCW can be selected as RGMII1, GPIO3, CAN1/2, FTM1 or
SAI1/2. There is a bug that EC3 RGMII could not work when selecting EC1
as other functionality except RGMII. The workaround is to select
ge2_clk125 for eTSEC clock muxing in register SCFG_ETSECCMCR.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agoarm: ls102xa: Add SystemID EEPROM support for LS1021ATWR board
Alison Wang [Fri, 17 Oct 2014 07:26:35 +0000 (15:26 +0800)]
arm: ls102xa: Add SystemID EEPROM support for LS1021ATWR board

SystemID information could be read through I2C1 from EEPROM
on LS1021ATWR board.

As LS1 is a little-endian processor, getting the version ID by
be32_to_cpu() is wrong. Fix it by using e.version directly.
This change will be compatible for both ARM and PowerPC.

As there is an errata that I2C1 could not work in SD boot,
reading EEPROM through I2C1 is disabled too in SD boot.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agols102xa: ifc: nor: fix the write issue when bytes unaligned
Yuan Yao [Fri, 17 Oct 2014 07:26:34 +0000 (15:26 +0800)]
ls102xa: ifc: nor: fix the write issue when bytes unaligned

Add define CONFIG_SYS_WRITE_SWAPPED_DATA.
For LS1021AQDS and LS1021QTWR nor flash write should swap the
bytes when handle unaligned tail bytes.

Because of the ending, if the date bus width is 16-bits and the
number of bytes is odd, we should swap the byte when write the
last one.

Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agoarm: ls102xa: Remove bit reversing for SCFG registers
Alison Wang [Fri, 17 Oct 2014 07:26:33 +0000 (15:26 +0800)]
arm: ls102xa: Remove bit reversing for SCFG registers

SCFG_SCFGREVCR is SCFG bit reverse register. This register
must be written with 0xFFFFFFFF before writing to any other
SCFG register. Then other SCFG register could be written in
big-endian mode.

Address: 157_0000h base + 200h offset = 157_0200h
Bit   0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15|16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
W/R                                   SCFGREV
Reset 0 0 0 0 0 0 0 0 0 0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0
0-31
SCFGREV SCFG Bit Reverse Control Filed
32'h 0000_0000 - No bit reverse is applied
32'h FFFF_FFFF - Bit reverse is applied; so 31:0 will be stored/read as
0:31

This patch removes the bit reversing for SCFG registers in
u-boot. It will be implemented through PBI commands in RCW
.pbi
write 0x570200, 0xffffffff
.end
So other SCFG register could be written in big-endian mode
in u-boot or kernel directly.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agoarm: ls102xa: Add snoop disable for slave port 0, 1 and 2
Jason Jin [Fri, 17 Oct 2014 07:26:32 +0000 (15:26 +0800)]
arm: ls102xa: Add snoop disable for slave port 0, 1 and 2

Disable the snoop for slave interface 0, 1 and 2
to avoid the interleaving on the CCI400 BUS.

Signed-off-by: Jason Jin <Jason.Jin@freescale.com>
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agols1: config: Enable USB EHCI Host on LS1021AQDS
Nikhil Badola [Fri, 17 Oct 2014 06:07:25 +0000 (11:37 +0530)]
ls1: config: Enable USB EHCI Host on LS1021AQDS

Enable USB EHCI Host on LS1021AQDS

Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agodrivers: usb: fsl: Define USB configs for LS102XA
Nikhil Badola [Fri, 17 Oct 2014 06:05:46 +0000 (11:35 +0530)]
drivers: usb: fsl: Define USB configs for LS102XA

Define USB configs for LS1021XA such as CONFIG_SYS_FSL_USB1_ADDR,
CONFIG_USB_MAX_CONTROLLER_COUNT

Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agodrivers : usb: fsl: Implement usb Erratum A007798 workaround
Nikhil Badola [Fri, 17 Oct 2014 03:42:07 +0000 (09:12 +0530)]
drivers : usb: fsl: Implement usb Erratum A007798 workaround

Set TXFIFOTHRESH to adjust ddr pipeline delay for successful large
usb writes

Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agoRevert "hush: fix segfault on syntax error"
Rabin Vincent [Fri, 21 Nov 2014 22:05:22 +0000 (23:05 +0100)]
Revert "hush: fix segfault on syntax error"

128059b92 ("hush: fix segfault on syntax error") attempted to fix a
segfault on syntax errors, but it broke Ctrl-C handling, and the
assumption that it made, that rcode could not be -1, is incorrect.
Revert this change.

Reported-by: Stephen Warren <swarren@wwwdotorg.org>
Reported-by: Przemyslaw Marczak <p.marczak@samsung.com>
Signed-off-by: Rabin Vincent <rabin@rab.in>
9 years agoMerge branch 'master' of git://www.denx.de/git/u-boot-imx
Tom Rini [Mon, 24 Nov 2014 17:02:12 +0000 (12:02 -0500)]
Merge branch 'master' of git://www.denx.de/git/u-boot-imx

9 years agoMerge git://git.denx.de/u-boot-dm
Tom Rini [Mon, 24 Nov 2014 17:01:48 +0000 (12:01 -0500)]
Merge git://git.denx.de/u-boot-dm

Conflicts:
drivers/serial/serial-uclass.c

Signed-off-by: Tom Rini <trini@ti.com>
9 years agoMerge git://git.denx.de/u-boot-x86
Tom Rini [Mon, 24 Nov 2014 17:00:00 +0000 (12:00 -0500)]
Merge git://git.denx.de/u-boot-x86

Conflicts:
arch/x86/cpu/Makefile

Signed-off-by: Tom Rini <trini@ti.com>
9 years agomx6boards: Fix error handling in board_mmc_init()
Fabio Estevam [Fri, 21 Nov 2014 18:42:58 +0000 (16:42 -0200)]
mx6boards: Fix error handling in board_mmc_init()

When an invalid USDHC port is passed we should return -EINVAL instead of 0.

Also, return the error immediately on fsl_esdhc_initialize() failure.

Cc: Eric Benard <eric@eukrea.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
9 years agonitrogen6x: Fix error handling in board_mmc_init()
Fabio Estevam [Fri, 21 Nov 2014 18:42:57 +0000 (16:42 -0200)]
nitrogen6x: Fix error handling in board_mmc_init()

When an invalid USDHC port is passed we should return -EINVAL instead of 0.

Also, return the error immediately on fsl_esdhc_initialize() failure.

Cc: Eric Nelson <eric.nelson@boundarydevices.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
9 years agoot1200: Fix error handling in board_mmc_init()
Fabio Estevam [Fri, 21 Nov 2014 18:42:56 +0000 (16:42 -0200)]
ot1200: Fix error handling in board_mmc_init()

When an invalid USDHC port is passed we should return -EINVAL instead of 0.

Also, return the error immediately on fsl_esdhc_initialize() failure.

Cc: Christian Gmeiner <christian.gmeiner@gmail.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
9 years agoarm: imx: stop sata on boot
Nikita Kiryanov [Fri, 21 Nov 2014 10:47:26 +0000 (12:47 +0200)]
arm: imx: stop sata on boot

Ideally, the Linux kernel should get the hardware in its most
untouched state. For the most part, U-Boot does not reset the various
subsystems it touches before boot, and usually Linux deals with it, but
on some boards (cm_fx6) the Linux kernel fails to detect the ssd
correctly if sata is used by U-Boot.

Power off sata on OS boot so that Linux will have a clean state to work
with.

Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Stefano Babic <sbabic@denx.de>
9 years agoarm: mx6: cm_fx6: implement board specific sata stop
Nikita Kiryanov [Fri, 21 Nov 2014 10:47:25 +0000 (12:47 +0200)]
arm: mx6: cm_fx6: implement board specific sata stop

Provide board specific implementation for sata stop command for
cm_fx6.

Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Stefano Babic <sbabic@denx.de>
9 years agocmd_sata: implement sata stop command
Nikita Kiryanov [Fri, 21 Nov 2014 10:47:24 +0000 (12:47 +0200)]
cmd_sata: implement sata stop command

Implement sata stop command.
This introduces the __sata_stop() weak function, which mirrors
the weak __sata_initialize() function, giving users the option of
undoing the custom steps performed in overrides of sata_initialize().

Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@ti.com>
9 years agosata: implement reset_sata for dwc_ahsata
Nikita Kiryanov [Fri, 21 Nov 2014 10:47:23 +0000 (12:47 +0200)]
sata: implement reset_sata for dwc_ahsata

Add reset_sata() to the sata driver interface and implement it
for dwc_ahsata. This function cleans up after sata_init(), and
therefore accepts a device number like sata_init() does.
A dummy implementation is provided for the rest of the drivers.

Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefano Babic <sbabic@denx.de>
9 years agoarm: mx6: introduce disable_sata_clock
Nikita Kiryanov [Fri, 21 Nov 2014 10:47:22 +0000 (12:47 +0200)]
arm: mx6: introduce disable_sata_clock

Implement disable_sata_clock for mx6 SoCs.

Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Stefano Babic <sbabic@denx.de>