Anson Huang [Wed, 3 Aug 2011 01:47:32 +0000 (09:47 +0800)]
ENGR00154211 [MX6]Add workaround for wdog errata
Errata number:TKT039676
WDOG sw reset is generated by writing to its
control register. WDOG's reset is activated by
ipg_clk_s, and is de-activated (later) by a
synchronized CKIL (32KHz clock). On the other
hand SRC samples the WDOG reset with an
unsynchronized CKIL clock. If the write to WDOG
control register happens between the edges of
unsynchronized and synchronized CKIL clocks SRC
will miss the wdog reset pulse.
Anson Huang [Tue, 2 Aug 2011 09:24:15 +0000 (17:24 +0800)]
ENGR00154056-2 [MX6]Enable dormant mode in suspend
1. Enable dormant mode in suspend, which means arm
core will be powered off when enter wfi, the latest
command for stop mode and dormant mode are as below:
echo standby > /sys/power/state
-> stop mode with arm core power on
echo mem > /sys/power/state
-> stop mode with arm core power off
Sammy He [Thu, 28 Jul 2011 11:50:31 +0000 (19:50 +0800)]
ENGR00153830-2 vpu: Add VPU_IOC_REQ_VSHARE_MEM ioctl for shared memory
Add vmalloced memory for multi-instances shared memory, vpu lib
will call mmap for accessing the memory.
VPU_IOC_GET_SHARE_MEM ioctl is still reserved for some time since
vpu lib still uses it for mx5x now. Will remove it after mx5x changes
to this new added memory later.
ENGR00153913: MX6x - Fix bug in set_parent and set_rate functions in clock code
Some set_parent() functions in clock code were using incorrect mask
resulting in wrong parent being set for the clocks.
Fix by using the correct mask.
The pre and post dividers for certain clocks were set incorrectly,
fix this by using the correct number of bits for the dividers.
Fix the set_rate function for ipu1_di1_clk.
Jason Chen [Wed, 27 Jul 2011 08:16:46 +0000 (16:16 +0800)]
ENGR00153785 ipuv3: use ipu internal divider for external di clock
on imx6q, pll5 can only provide rate >=650M, and ipu_di_clk only has max
divider 8, so need use ipu internal clock divider for some low resolution
case. For example 640x480p60 need 25.2MHz pixel clock.
Jason Chen [Wed, 27 Jul 2011 06:13:58 +0000 (14:13 +0800)]
ENGR00153761 imx6q ipuv3: improve display quality
to avoid ipu starvation issue.
1. enable IPU AXI cache in uboot
2. set Qos to 7 for IPU to highest priority in uboot.
3. set AXI id to 0 for high priority IDMA channel in linux.
Jason Chen [Wed, 27 Jul 2011 06:06:18 +0000 (14:06 +0800)]
ENGR00153757 mxc_hdmi: fix build error of mxc_hdmi.c
Fix build error of below:
`mxc_hdmi_remove' referenced in section
`.data' of drivers/built-in.o: defined in discarded section
`.exit.text' of drivers/built-in.o`
Danny Nold [Tue, 26 Jul 2011 03:01:15 +0000 (22:01 -0500)]
ENGR00153670-4 - MXC HDMI: Add support for basic HDMI operation
- Add MXC HDMI to kconfig and makefile
- Add initial mxc_hdmi.c file to provide basic HDMI functionality:
- Basic HDMI output functional
- Support for reading EDID via I2C and registering
video modes with IPU
- Support for output from IPU1 DI0
- These features not yet added:
- Hotplug support
- Dual display with LVDS
- Power management
- Support for FB notifications
- Changes to IPU to allow HDMI to use source clocks that it needs
Signed-off-by: Danny Nold <dannynold@freescale.com>
Danny Nold [Tue, 26 Jul 2011 02:39:50 +0000 (21:39 -0500)]
ENGR00153670-2 - mach-mx6: Add support for MXC HDMI
- Add MXC HDMI initialization structures and calls to SABRE board file.
- Add HDMI clock definitions and functions for PLL5 (main video clock
used by HDMI).
Signed-off-by: Danny Nold <dannynold@freescale.com>
ENGR00153651-1 ESAI: Prepare MSL support for esai/cs42888 audio codec driver
1) Add machine specific code for esai/cs42888 driver support, including pad
control, clk setting, i2c setting, etc.
2) Enable audio support in default config.
Richard Zhu [Tue, 19 Jul 2011 05:42:29 +0000 (13:42 +0800)]
ENGR00153275-1 ahci L2638 add the standalone ahci temperature monitor
based on the 2.6.38 kernel mainline, refer to linux lm-sensors
architeture, add the standalone ahci temperature monitor driver
on fsl i.mx53 platforms.
Less than half sencond is used in one temperature read operation.
usage:
Use the following cmd to cat the i.mx53 soc temperature after
boot up i.mx53 system in user space.
for example:
...$ cat /sys/class/hwmon/hwmon1/device/temp1_input
61000
or run the following cmd after configure the lm-sensors
...$ sensors
imx-ahci-hwmon-isa-0000
Adapter: ISA adapter
temp1: +58.0 C
1. Copy mx6_secondary_startup to iRAM;
2. CPU0 reset CPUx, then waiting CPUx reset OK, and
clear CPUx's boot_entry;
3. CPUx reset OK, waiting CPU0 to clear its parameter;
4. All these steps done, CPUx go on boot;
Tony Lin [Fri, 15 Jul 2011 02:59:38 +0000 (10:59 +0800)]
ENGR00153160 fix card interrupt issue on uSDHC and eSDHC
uSDHC: card interrupt storm if we do not clear card interrupt
status by sw.
eSDHC: card interrupt will be lost if we do not set D3CD bit.
apply the workarounds in sdhci-esdhc-imx.c to avoid adding new
QUIRKs.
Mx6 not works when connnect to a 1G switch.
This is caused by phy_dev->supported != PHY_GBIT_FEATURES, more bits
will set to phy_dev->supported when negotiation complete.
Terry Lv [Tue, 21 Jun 2011 06:29:52 +0000 (14:29 +0800)]
ENGR00139235-3: IIM(OCOPT): Enable IIM driver for iMX6Q
Add a new driver for On-Chip OTP controller. The driver
will register all the register names of all the banks to /sys/.
You can use the following commands to manipulate the OTP banks:
Tony Lin [Tue, 12 Jul 2011 03:09:29 +0000 (11:09 +0800)]
ENGR00152547-04 [MX6Q]add SDHC3.0 support on uSDHC controller
modify host controller driver to meet SD3.0 spec.
including voltage switch, and tuning control.
add a function pointer for bus driver to do tuning preparation,
in case some host controller like uSDHC does not tune automatically.
it needs change delay line before tuning.
Tony Lin [Tue, 12 Jul 2011 03:08:57 +0000 (11:08 +0800)]
ENGR00152547-03 [MX6Q]add SDHC3.0 support on uSDHC controller
add voltage switch function due to SDHC3.0 spec requirement
add tuning function due to SDHC3.0 spec requirement
extend some functions to support SDR50 & SDR104 speed mode
Tony Lin [Tue, 12 Jul 2011 03:04:35 +0000 (11:04 +0800)]
ENGR00152547-01 [MX6Q]add SDHC3.0 support on uSDHC controller
enable uSDHC slot 3 in board file
add parameter in platform data to indicate whether the slot
supports 1.8 voltage
add pinmux to support voltage switch between 1.8V and 3.3V
Jason Chen [Wed, 13 Jul 2011 04:02:43 +0000 (12:02 +0800)]
ENGR00152845-1 MSL plat-mxc: ipuv3 display support in imx6q
1. work for multiple ipu instance
2. add mxc_dispdrv support
A display device driver could call mxc_dispdrv_register(drv) in its
dev_probe() function.
- Move all dev_probe() things into mxc_dispdrv_driver->init(), init()
function should init and feedback setting;
- Move all dev_remove() things into mxc_dispdrv_driver->deinit();
- Move all dev_suspend() things into fb_notifier for SUSPEND, if there is;
- Move all dev_resume() things into fb_notifier for RESUME, if there is;
ipuv3 fb driver would call mxc_dispdrv_init(drv_name, setting) before a
fb need be added, with fbi param passing by setting, after mxc_dispdrv_init()
return, FB driver should get the basic setting about fbi info and ipuv3-hw
(ipu_id and disp_id).
there are many display interfaces on imx5x or imx6x platform, all of them
are connected with ipuv3-DI, mxc_dispdrv can register display device as:
"lcd" -- display extend port for lcdif
"ldb" -- lvds bridge on chip (imx5x or imx6x)
"tve" -- tve for tveout on chip (imx5x)
"vga" -- vga through tve on chip (imx5x)
"hdmi" -- hdmi on platform with ddc support
(sii902x on imx53 - not enable yet)
hdmi on chip with ddc support
(imx6x - not enable yet)
"dvi" -- dvi port with ddc support (not enable yet)
take tvout as example, a dispdrv structure and register flow could like below:
"mxcfb0" means setting for fb0 device, ipuv3 fb driver will request setting
from registered dispdrv, these setting include what's the ipu and what's the
DI number this dev used. Normally, if one IPU is first used, ipuv3 fb driver
will create one overlay fb right after current fb driver create.
Take above cmdline as an example,
/dev/fb0 will be first fb device on 800x480 lcd.
/dev/fb1 will be overlay fb device on 800x480 lcd.
/dev/fb2 will be second fb device on VGA-XGA vga.
"dev=" means which display device(lcd,ldb,vga etc) you want choose for this fb.
"800x480M@55 or VGA-XGA" means the mode_str of video mode you want.
"if=" means the display device hw interface format.
such setting could be passed by platform data as a default value, cmdline
option will replace these values if there are.
3. modify ldb/tve driver and add mxc_lcdif driver.
For ldb driver, there are below modes could be set by cmdline options:
"ldb=spl0/1" -- split mode on DI0/1
"ldb=dul0/1" -- dual mode on DI0/1
"ldb=sin0/1" -- single mode on DI0/1
"ldb=sep" -- separate mode
there are two LVDS channels(LVDS0 and LVDS1) which can transfer video datas,
there two channels can be used as split/dual/single/separate mode.
split mode means display data from DI0 or DI1 will send to both channels
LVDS0+LVDS1.
dual mode means display data from DI0 or DI1 will be duplicated on LVDS0 and
LVDS1, it said, LVDS0 and LVDS1 has the same content.
single mode means only work for DI0->LVDS0 or DI1->LVDS1.
separate mode means you can make DI0->LVDS0 and DI1->LVDS1 work at the same
time.
Signed-off-by: Jason Chen <jason.chen@freescale.com>
Peter Chen [Mon, 11 Jul 2011 10:24:50 +0000 (18:24 +0800)]
ENGR00152915-1 mx6q-usb: refine usb phy usage
(Fixed the bug that PLL7 lock failed after usb enters low power mode)
After confirming with IC guys, the phy clock should be used
like below:
- OTG phy clock
EN_USB_CLKS: should be also enabled
PLL3 power: Enable/Disable on the fly
- Host1 phy clock
EN_USB_CLKS and PLL7 power should be also enabled at the initialization
PLL7 power will be totally controller by IC
Signed-off-by: Peter Chen <peter.chen@freescale.com>
Peter Chen [Fri, 8 Jul 2011 00:49:53 +0000 (08:49 +0800)]
ENGR00152842 mx5x-usb: fix build error
As well as some warnings for compiling
Fix the build error reported by Alan Tull, the error message is:
arch/arm/mach-mx5/usb_dr.c: In function 'mx5_usb_dr_init':
arch/arm/mach-mx5/usb_dr.c:309: error: implicit
declaration of function 'machine_is_mx53_loco'
The below warning message output when compiling mx5x kenrel:
arch/arm/plat-mxc/include/mach/arc_otg.h:36:7:
warning: "CONFIG_ARCH_MX6" is not defined
Signed-off-by: Peter Chen <peter.chen@freescale.com>
Danny Nold [Tue, 5 Jul 2011 19:26:49 +0000 (14:26 -0500)]
ENGR00152681 - EPDC fb: Updates may be shifted right by 1 column
- Fixed PxP input left coordinate value. Was previously being incorrectly
computed such that the value would be incorrect when using 16bpp RGB and an
X coordinate that is offset from 4-pixel alignment by 1 (e.g. x=1, x=5).
The resulting effect was that updates meeting this criteria would be
drawn to the EPD panel shifted to the right by 1 pixel.
Signed-off-by: Danny Nold <dannynold@freescale.com>