Arnd Bergmann [Tue, 10 May 2016 20:18:14 +0000 (22:18 +0200)]
Merge tag 'tegra-for-4.7-gm20b' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/dt64
Merge "arm64: tegra: Enable GM20B GPU on Tegra210" from Thierry Reding:
Complement the GM20B GPU device tree node on Tegra210 with missing
properties to make it usable.
* tag 'tegra-for-4.7-gm20b' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
arm64: tegra: Add IOMMU node to GM20B on Tegra210
arm64: tegra: Add reference clock to GM20B on Tegra210
dt-bindings: Add documentation for GM20B GPU
dt-bindings: gk20a: Document iommus property
dt-bindings: gk20a: Fix typo in compatible name
Arnd Bergmann [Tue, 10 May 2016 20:14:52 +0000 (22:14 +0200)]
Merge tag 'mvebu-dt64-4.7-1' of git://git.infradead.org/linux-mvebu into next/dt64
Merge "mvebu dt64 for 4.7" from Gregory CLEMENT:
- switch to label in the mvebu arm64 device tree
- use new clock binding on Armada 7K/8K
- improve SPI and I2C description on Armada 7K/8k
- add CP110 block adding PCIe, SATA and USB3
- add XOR support on Armada 3700
- few more little fix
* tag 'mvebu-dt64-4.7-1' of git://git.infradead.org/linux-mvebu:
arm64: dts: marvell: add XOR node for Armada 3700 SoC
arm64: dts: marvell: Use a SoC-specific compatible for xHCI on Armada37xx
arm64: dts: marvell: Rename armada-37xx USB node
arm64: dts: marvell: Clean up armada-3720-db
arm64: dts: marvell: enable several CP interfaces on Armada 7040-DB
arm64: dts: marvell: initial DT description of Armada 7K/8K CP110 master
arm64: dts: marvell: use the proper I2C controller compatible string for 7K/8K
arm64: dts: marvell: improve SPI flash description on Armada 7040-DB
arm64: dts: marvell: use new clock binding on Armada AP806
arm64: dts: marvell: add UART aliases and define stdout-path
arm64: dts: marvell: rename armada-ap806 XOR nodes
arm64: dts: marvell: clean up armada-7040-db
Arnd Bergmann [Tue, 10 May 2016 20:06:49 +0000 (22:06 +0200)]
Merge tag 'v4.7-rockchip-dts64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt64
Merge "Rockchip dts64 updates for v4.7 - part2" from Heiko Stübner:
Adding the new rk3399 core devicetree support as well as a board
dts for the evaluation board of this chip and similar to the arm32
side also move the rk3368 thermal data into the core soc dtsi, as
there really is no need to keep it separate.
* tag 'v4.7-rockchip-dts64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
dt-bindings: document rockchip rk3399-evb board
arm64: dts: rockchip: add dts file for RK3399 evaluation board
arm64: dts: rockchip: add core dtsi file for RK3399 SoCs
dt-bindings: rockchip-dw-mshc: add description for rk3399
clk: rockchip: export some necessary rk3399 clock ids
clk: rockchip: rename rga clock-id on rk3399
clk: rockchip: add general gpu soft-reset on rk3399
arm64: dts: rockchip: move the rk3368 thermal data into rk3368.dtsi
clk: rockchip: fix checkpatch errors in rk3399 dt-binding header
clk: rockchip: add dt-binding header for rk3399
arm64: dts: rockchip: add core dtsi file for RK3399 SoCs
This patch adds core dtsi file for Rockchip RK3399 SoCs.
The RK3399 has big/little architecture, which needs a separate
node for the PMU of each microarchitecture, for now it missing
the pmu node since the old one could not work well.
Merge tag 'hip0x-dt-for-4.7' of git://github.com/hisilicon/linux-hisi into next/dt64
Merge "ARM64: DT: Hisilicon hip05 and hip06 updates for 4.7" Wei Xu:
- Fix its node without msi-cells for hip05
- Add nor flash node for hip05 D02 board
- Add initial dts for hip06 D03 board
- Reorder and add the hip06 D03 binding in the binding document
* tag 'hip0x-dt-for-4.7' of git://github.com/hisilicon/linux-hisi:
Documentation: arm64: Add Hisilicon Hip06 D03 dts binding
arm64: dts: Add initial dts for Hisilicon Hip06 D03 board
arm64: dts: hip05: Add nor flash support
arm64: dts: hip05: fix its node without msi-cells
arm64: dts: marvell: Use a SoC-specific compatible for xHCI on Armada37xx
Even if the Armada 37xx does not any specific setup, the device tree
binding documentation requires to use a SoC-specific version
corresponding to the platform first followed by the generic version.
This patch introduce this new compatible string and updates the
documentation accordingly.
Andreas Färber [Wed, 23 Mar 2016 22:24:19 +0000 (23:24 +0100)]
arm64: dts: marvell: Rename armada-37xx USB node
No need to reflect the USB version in the node name.
Cc: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
[gregory.clement@free-electrons.com: drop Fixes tag as it is not a bug fix.]
Andreas Färber [Wed, 23 Mar 2016 22:24:18 +0000 (23:24 +0100)]
arm64: dts: marvell: Clean up armada-3720-db
Instead of duplicating the SoC's node hierarchy, including a bus node
named "internal-regs", reference the actually desired nodes by label,
like Berlin already does. Add labels where necessary.
Drop an inconsistent white line while at it. Cc: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
[gregory.clement@free-electrons.com: drop Fixes tag as it is not a bug fix.]
Kefeng Wang [Fri, 8 Apr 2016 07:27:11 +0000 (15:27 +0800)]
arm64: dts: Add initial dts for Hisilicon Hip06 D03 board
The Hip06 soc has same cpu topology compared with Hip05, four clusters
and each cluster has quard Cortex-A57, but with different IO part,
like HNS, SAS and PCI, they are all upgraded. There are also not same
in ITS, MBIGEN and SMMU, etc.
This patch adds the initial dts for hip06 d03 board.
Note, there is no serial, because the soc use LPC uart, the serial node
is not needed.
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
clk_get() on a disabled clock node will return -EPROBE_DEFER, which can
cause drivers to be deferred forever if such clocks are referenced in
their devices' clocks properties.
Update the various disabled external clock nodes to default to a
frequency of 0, but don't disable them, to prevent this.
Thomas Petazzoni [Tue, 26 Apr 2016 07:58:36 +0000 (09:58 +0200)]
arm64: dts: marvell: initial DT description of Armada 7K/8K CP110 master
This commit adds an initial Device Tree description for the CP110
master that is found in the Armada 7K and 8K SoCs. This initial
description describes:
- the system controller (to provide clocks)
- three PCIe interfaces
- the SATA interface
- the I2C controllers
- the SPI controllers
For the record, the organization of the SoCs is as follows:
- 7020: dual-core AP, one CP110 (master)
- 7040: quad-core AP, one CP110 (master)
- 8020: dual-core AP, two CP110s (master and slave)
- 8040: quad-core AP, two CP110s (master and slave)
For this reason, all of the 7020, 7040, 8020 and 8040 include
armada-cp110-master.dtsi. When support for the second CP110 (slave)
used in 8020 and 8040 will be added, the .dtsi files for those SoCs
will in addition include armada-cp110-slave.dtsi.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Thomas Petazzoni [Tue, 26 Apr 2016 07:58:35 +0000 (09:58 +0200)]
arm64: dts: marvell: use the proper I2C controller compatible string for 7K/8K
The I2C controller found in the Marvell Armada 7K/8K provides the
bridge/offloading features, so the Device Tree should use the
marvell,mv78230-i2c compatible string instead of marvell,mv64xxx-i2c.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Thomas Petazzoni [Tue, 26 Apr 2016 07:58:32 +0000 (09:58 +0200)]
arm64: dts: marvell: add UART aliases and define stdout-path
This commit adds the necessary UART aliases to the main Armada 7K/8K
.dtsi file, and uses them to define the /chosen/stdout-path property
on the Armada 7040 DB board.
Suggested-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Node names should not contain an instance number, the unit address
serves to distinguish nodes of the same name. So rename the XOR nodes
to just xor@<address>.
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
[Thomas:
- remove labels, they are really not needed for XOR engines.
- remove the Fixes: tag, as this is not a fix.] Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Andreas Färber [Tue, 26 Apr 2016 07:58:30 +0000 (09:58 +0200)]
arm64: dts: marvell: clean up armada-7040-db
Instead of duplicating the node hierarchy, reference the nodes by label,
adding labels where necessary.
Drop some trailing or inconsistent white lines while at it.
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
[Thomas: drop Fixes tag as it is not a bug fix.] Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
clk_get() on a disabled clock node will return -EPROBE_DEFER, which can
cause drivers to be deferred forever if such clocks are referenced in
their devices' clocks properties.
Update the disabled external scif clock node so that it
is not disabled to prevent this.
Reported-by: Jürg Billeter <j@bitron.ch> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
[simon: fix for v4.6 extracted from a larger patch targeted at v4.7] Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Merge tag 'arm-soc/for-4.7/devicetree-arm64' of http://github.com/Broadcom/stblinux into next/dt64
Pull "Broadcom ARM64-based SoC Device Tree changes" from Florian Fainelli:
- Anup enables a bunch of standard peripherals in the Northstar 2 DTS: PL330
DMA, GIC maintenance interrupt, PL022 SPI controller
- Anup also re-orgnanizes the clock Device Tree fragments into a separate file
for consistency with how other Broadcom SoCs are doing this
- Luke switches the SMP enable-method and reboot from a spin-table + syscon to
the standard PSCI 1.0 firmware interface
* tag 'arm-soc/for-4.7/devicetree-arm64' of http://github.com/Broadcom/stblinux:
arm64: dts: NS2 secondary core enablement via PSCI
arm64: dts: Add ARM PL022 SPI DT nodes for NS2
arm64: dts: Move NS2 clock DT nodes to separate DT file
arm64: dts: Add maintenance interrupt for GIC in NS2 DT
arm64: dts: Add ARM PL330 DMA DT node for NS2
Merge tag 'xgene-dts-for-v4.7-part1' of https://github.com/AppliedMicro/xgene-next into next/dt64
Merge "First part of X-Gene DTS changes queued for v4.7" from Duc Dang:
This patch set only includes a single change to
fix the compatible string for SATA controllers on
X-Gene v2 SOC platforms.
* tag 'xgene-dts-for-v4.7-part1' of https://github.com/AppliedMicro/xgene-next:
arm64: dts: apm: Fix compatible string for X-Gene 2 SATA controller DTS node
Merge tag 'hi6220-dt-for-4.7' of git://github.com/hisilicon/linux-hisi into next/dt64
Pull "ARM64: DT: Hisilicon Hi6220 soc and hikey board updates for 4.7" from Wei Xu
- Reserve memory regions for Hi6220
- Add sp804 timer node for Hi6220
- Add cpu and cluster level's low power state for Hi6220
- Add gpio configuration nodes for Hi6220
- Add pinctrl configuration nodes for Hi6220
- Add spi related nodes for Hi6220
- Add i2c nodes for Hi6220
- Add i2c nodes to work with mezzanine boards
- Add usb nodes for Hi6220
- Add mailobx node for Hi6220
- Add SRAM node and stub clock node for Hi6220
- Add pinctrl nodes for uarts and enable them
- Add LED nodes for hi6220-hikey board
- Add hi655x pmic node for Hi6220
- Add dwmmc nodes for Hi6220
- Add wifi nodes support for Hi6220-Hikey board
- Register thermal sensor for Hi6220
- Register Hi6220's thermal zone for power allocator
- Add L2 cache topology for Hi6220
* tag 'hi6220-dt-for-4.7' of git://github.com/hisilicon/linux-hisi:
arm64: dts: Add L2 cache topology to Hi6220
arm64: dts: register Hi6220's thermal zone for power allocator
arm64: dts: register Hi6220's thermal sensor
arm64: dts: add wifi nodes support for hi6220-hikey
arm64: dts: add dwmmc nodes for hi6220
arm64: dts: hikey: Add hi655x pmic dts node
arm64: dts: add LED nodes for hi6220-hikey
arm64: dts: hi6220: add pinctrl for uarts and enable them
arm64: dts: add Hi6220's stub clock node
arm64: dts: add mailbox node for Hi6220
arm64: dts: Add hi6220 usb node
arm64: dts: hikey: enable i2c0 and i2c1 for working with mezzanine boards
arm64: dts: add all hi6220 i2c nodes
arm64: dts: add Hi6220 spi configuration nodes
arm64: dts: add Hi6220 pinctrl configuration nodes
arm64: dts: Add Hi6220 gpio configuration nodes
arm64: dts: enable idle states for Hi6220
arm64: dts: add sp804 timer node for Hi6220
arm64: dts: Reserve memory regions for hi6220
Merge tag 'juno-for-v4.7/dt-updates' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into next/dt64
Pull "ARMv8 Juno DT updates for v4.7" from Sudeep Holla:
Just one update: Support for external expansion bus useful for
additional hardware e.g.LogicTile Express daughterboards (Brian Starkey)
* tag 'juno-for-v4.7/dt-updates' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
arm64: dts: juno: Add external expansion bus to DT
Merge tag 'tegra-for-4.7-arm64' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/dt64
Merge "arm64: tegra: Changes for v4.7-rc1" from Thierry Reding
A couple of cleanups and fixes to various device trees, enable power and
volume keys on Jetson TX1, use stdout-path to define the serial port (so
it doesn't have to be specified on the kernel command-line) and add
Google Pixel C (a.k.a. Smaug) support.
* tag 'tegra-for-4.7-arm64' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
arm64: tegra: Enable cros-ec and charger on Smaug
arm64: tegra: Add pinmux for Smaug board
arm64: tegra: Add stdout-path for various boards
arm64: tegra: Remove unused #power-domain-cells property
arm64: tegra: Add gpio-keys nodes for Smaug
arm64: tegra: Enable power and volume keys on Jetson TX1
arm64: tegra: Add support for Google Pixel C
arm64: tegra: Replace legacy *,wakeup property with wakeup-source
arm64: tegra: Fix copy/paste typo in several DTS includes
arm64: tegra: Remove 0, prefix from unit-addresses
Merge tag 'samsung-dt64-4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/dt64
Merge "Samsung Device Tree ARM64 updates and improvements for v4.7" from Krzysztof Kozlowski:
1. Add PL330 DMA controller and Thermal Management Unit to Exynos 7.
* tag 'samsung-dt64-4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
arm64: dts: Add nodes for pdma0 and pdma1 for exynos7
arm64: dts: exynos: Add TMU node for exynos7
The rga clock supplying the working clock on the rk3399 is actually
called rga-core in the manual. As the clock id has neither been
assigned nor released with a full kernel release, we can still change
the id to the more appropriate naming.
Luke Starrett [Wed, 20 Apr 2016 17:40:02 +0000 (13:40 -0400)]
arm64: dts: NS2 secondary core enablement via PSCI
Declare PSCI-1.0 node and enable CPU_ON method via PSCI. Spin-table
memreserve has been removed as well as syscon based reset, as PSCI-1.0
expects reset implementation in firmware.
Signed-off-by: Luke Starrett <luke.starrett@broadcom.com> Acked-by: Scott Branden <scott.branden@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Stephen Warren [Tue, 12 Apr 2016 17:46:37 +0000 (11:46 -0600)]
ARM: tegra: Add DT binding for Tegra186 GPIO controllers
Tegra186 contains two separate but mostly similar GPIO controllers.
Register layout differs significantly from previous Tegra generations,
and so a new binding is required to describe them in device tree. This
patch adds that binding.
Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
Stephen Warren [Tue, 5 Apr 2016 19:25:07 +0000 (13:25 -0600)]
ARM: tegra: Fix naming in GPIO DT binding header
According to the Tegra TRM, GPIOs are aggregated into /ports/ of 8 GPIOs,
not into /banks/. Fix <dt-bindings/gpio/tegra-gpio.h> to correctly reflect
this naming convention. While this seems like silly churn, it will become
slightly more important once we introduce the GPIO binding for upcoming
Tegra chips.
ARM: shmobile: timer: Fix preset_lpj leading to too short delays
On all shmobile ARM SoCs, loop-based delays may complete early, which
can be after only 1/3 (Cortex A9) or 1/2 (Cortex A7 or A15) of the
minimum required time.
This is caused by calculating preset_lpj based on incorrect assumptions
about the number of clock cycles per loop:
- All of Cortex A7, A9, and A15 run __loop_delay() at 1 loop per
CPU clock cycle,
- As of commit 11d4bb1bd067f9d0 ("ARM: 7907/1: lib: delay-loop: Add
align directive to fix BogoMIPS calculation"), Cortex A8 runs
__loop_delay() at 1 loop per 2 instead of 3 CPU clock cycles.
On SoCs with Cortex A7 and/or A15 CPU cores, this went unnoticed, as
delays use the ARM arch timer if available. R-Car Gen2 doesn't work if
the arch timer is disabled. However, APE6 can be used without the arch
timer.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Revert "ARM: dts: porter: Enable SCIF_CLK frequency and pins"
This reverts commit 19417bd9c511 ("ARM: dts: porter: Enable SCIF_CLK
frequency and pins") as according to
http://elinux.org/File:R-CarM2-KOELSCH_PORTER-B_PORTER_C_Comparison.pdf
the external oscillator for SCIF_CLK is not mounted on the porter boards.
clk_get on a disabled clock node will return EPROBE_DEFER, which can
cause drivers to be deferred forever if such clocks are referenced in
their clocks property.
Update the various disabled external clock nodes to default to a
frequency of 0, but don't disable them to prevent this.
Leo Yan [Tue, 12 Apr 2016 23:55:37 +0000 (07:55 +0800)]
arm64: dts: Reserve memory regions for hi6220
On Hi6220, below memory regions in DDR have specific purpose:
0x05e0,0000 - 0x05ef,ffff: For MCU firmware using at runtime;
0x06df,f000 - 0x06df,ffff: For mailbox message data;
0x0740,f000 - 0x0740,ffff: For MCU firmware's section;
0x3e00,0000 - 0x3fff,ffff: For OP-TEE.
This patch reserves these memory regions in DT.
Signed-off-by: Leo Yan <leo.yan@linaro.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Olof Johansson [Wed, 13 Apr 2016 19:00:41 +0000 (12:00 -0700)]
Merge tag 'renesas-arm64-cleanup-for-v4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt64
Renesas ARM64 Based SoC Cleanup for v4.7
* Use generic pinctrl properties in DT for salvator-x board
* tag 'renesas-arm64-cleanup-for-v4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
arm64: dts: salvator-x: use generic pinctrl properties
Anup Patel [Tue, 29 Mar 2016 07:27:34 +0000 (12:57 +0530)]
arm64: dts: Add ARM PL022 SPI DT nodes for NS2
We have two ARM PL022 SPI instances in NS2 SoC. On NS2 SVK,
one of the ARM PL022 SPI host has Silabs si3226x slic connected
to chip-select #0 whereas second ARM PL022 SPI host has Atmel
AT25 EEPROM connected to chip-select #0.
This patch adds ARM PL022, Silabs si3226x, and Atmel AT25
DT nodes in NS2 DT and NS2 SVK DT respectively.
Signed-off-by: Anup Patel <anup.patel@broadcom.com> Reviewed-by: Ray Jui <rjui@broadcom.com> Reviewed-by: Scott Branden <sbranden@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Olof Johansson [Wed, 13 Apr 2016 17:19:35 +0000 (10:19 -0700)]
Merge tag 'gxbb-dt64' of https://github.com/carlocaione/linux-meson into next/dt64
Add support for a few more Amlogic S905/GXBB based boards: Hardkernel ODROID-C2
and Amlogic P200/P201 boards.
We also fix the memory nodes on the Vega S95 DTS.
* tag 'gxbb-dt64' of https://github.com/carlocaione/linux-meson:
ARM64: dts: amlogic: Add P200/P201 boards
ARM64: dts: amlogic: add Hardkernel ODROID-C2
Documentation: devicetree: amlogic: Document P20x and ODROID-C2 boards
ARM64: dts: amlogic: update serial aliases
ARM64: dts: amlogic: Clean up Vega S95 /memory nodes
Jon Hunter [Tue, 9 Feb 2016 13:52:00 +0000 (13:52 +0000)]
arm64: tegra: Add stdout-path for various boards
For Tegra boards, the device-tree alias serial0 is used for the console
and so add the stdout-path information so that the console no longer
needs to be passed via the kernel boot parameters.
For tegra132-norrin the alias serial0 is not defined and so add this.
This has been tested on tegra132-norrin and tegra210-p2371-0000.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
Rhyland Klein [Thu, 3 Mar 2016 19:54:25 +0000 (14:54 -0500)]
arm64: tegra: Add gpio-keys nodes for Smaug
Add gpio-keys nodes for the volumn controls, lid switch, tablet mode and
power button.
Signed-off-by: Rhyland Klein <rklein@nvidia.com> Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
[treding@nvidia.com: use symbolic names for input types and codes]
[treding@nvidia.com: use wakeup-source instead of gpio-key,wakeup] Signed-off-by: Thierry Reding <treding@nvidia.com>
Sudeep Holla [Mon, 8 Feb 2016 21:55:43 +0000 (21:55 +0000)]
arm64: tegra: Replace legacy *,wakeup property with wakeup-source
Though the keyboard and other driver will continue to support the legacy
"gpio-key,wakeup", "nvidia,wakeup-source" boolean property to enable the
wakeup source, "wakeup-source" is the new standard binding.
This patch replaces all the legacy wakeup properties with the unified
"wakeup-source" property in order to avoid any further copy-paste
duplication.
Thierry Reding [Wed, 27 Jan 2016 14:02:20 +0000 (15:02 +0100)]
arm64: tegra: Fix copy/paste typo in several DTS includes
The comment about the 8250 vs. APB DMA-enabled UART devices that was
added for Tegra20 and Tegra30 in commit b6551bb933f9 ("ARM: tegra: dts:
add aliases and DMA requestor for serial controller") introduced a typo
that has since spread to various other DTS include files. Fix all
occurrences of this typo.
arm64: tegra: Remove 0, prefix from unit-addresses
When Tegra124 support was first merged the unit-addresses of all devices
were listed with a "0," prefix to encode the reg property's second cell.
It turns out that this notation is not correct, and the "," separator is
only used to separate fields in the unit address (such as the device and
function number in PCI devices), not individual cells for addresses with
more than one cell.
Merge tag 'mmc-v4.6-rc1' of git://git.linaro.org/people/ulf.hansson/mmc
Pull MMC fixes from Ulf Hansson:
"Here are a couple of mmc fixes intended for v4.6 rc3:
MMC host:
- sdhci: Fix regression setting power on Trats2 board
- sdhci-pci: Add support and PCI IDs for more Broxton host controllers"
* tag 'mmc-v4.6-rc1' of git://git.linaro.org/people/ulf.hansson/mmc:
mmc: sdhci-pci: Add support and PCI IDs for more Broxton host controllers
mmc: sdhci: Fix regression setting power on Trats2 board