]> git.karo-electronics.de Git - karo-tx-linux.git/log
karo-tx-linux.git
11 years agoENGR00180229-1 V4L2: Fix a bug when doing tiled format deinterlaced
Wayne Zou [Wed, 18 Apr 2012 08:30:28 +0000 (16:30 +0800)]
ENGR00180229-1 V4L2: Fix a bug when doing tiled format deinterlaced

Initialize paddr_n when doing vdoa+vdi deinterlaced,
when doing tiled format deinterlaced.

Signed-off-by: Wayne Zou <b36644@freescale.com>
11 years agoENGR00180231 mx6q arm2 ONFI NAND clock change
Allen Xu [Thu, 19 Apr 2012 06:26:16 +0000 (14:26 +0800)]
ENGR00180231 mx6q arm2 ONFI NAND clock change

change clock source to enfc clock on mx6q arm2 lpddr board for ONFI nand
when enable ddr mode

Signed-off-by: Allen Xu <allen.xu@freescale.com>
11 years agoENGR00172292 usb otg: enable dtds postpone free on mx6
Xinyu Chen [Thu, 19 Apr 2012 09:04:57 +0000 (17:04 +0800)]
ENGR00172292 usb otg: enable dtds postpone free on mx6

We found this bug occurs again on mx6 when running
CTS with ADB over USB. The system will hang without
any log, and screen a little mess.
It's proved to be a known USB IP issue: USB controller
may access a wrong address for the dTD and then hang.
Re enable this workaround to avoid any system unstability.

Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
11 years agoENGR00180055 Steer configuration to enable AUD5_RXD signal
Alejandro Sierra [Tue, 17 Apr 2012 19:40:48 +0000 (14:40 -0500)]
ENGR00180055 Steer configuration to enable AUD5_RXD signal

Steer configuration to enable AUD5_RXD signal

Signed-off-by: Alejandro Sierra <b18039@freescale.com>
11 years agoENGR00180230 MX6 PCIE: enlarge the eye diagram and force to GEN1
Richard Zhu [Tue, 17 Apr 2012 02:24:50 +0000 (10:24 +0800)]
ENGR00180230 MX6 PCIE: enlarge the eye diagram and force to GEN1

* Adjust the parameters, enlarge the eye diagram.
* Force to the PCIE GEN1 speed.

Signed-off-by: Richard Zhu <r65037@freescale.com>
11 years agoENGR00180096 change NAND clock source to pll2_pfd_400M
Allen Xu [Wed, 18 Apr 2012 02:15:27 +0000 (10:15 +0800)]
ENGR00180096 change NAND clock source to pll2_pfd_400M

change clock source explicitly by calling set_parent() function

Signed-off-by: Allen Xu <allen.xu@freescale.com>
11 years agoENGR00180075 MX6: change CLKO source to pll4_audio_main_clk
Gary Zhang [Wed, 18 Apr 2012 04:38:37 +0000 (12:38 +0800)]
ENGR00180075 MX6: change CLKO source to pll4_audio_main_clk

change CLKO source to pll4_audio_main_clk for low power
mode consideration

Signed-off-by: Gary Zhang <b13634@freescale.com>
11 years agoENGR00179851: i.mx6dl: map the MEM mode to STANDBY mode
Jason Liu [Tue, 17 Apr 2012 11:08:00 +0000 (19:08 +0800)]
ENGR00179851: i.mx6dl: map the MEM mode to STANDBY mode

Due to i.mx6dl TO1.0(TKT094231), Suspend/resume cannot work
stable under deep sleep mode(Dormant, MEM MODE) thus we need
map the MEM mode to STANBY mode(ARM will not power off), this
issue will be fixed on TO1.1

Signed-off-by: Jason Liu <r64343@freescale.com>
11 years agoENGR00179782: i.mx6: consolidate mx6q/dl_revision() support
Jason Liu [Tue, 17 Apr 2012 10:53:53 +0000 (18:53 +0800)]
ENGR00179782: i.mx6: consolidate mx6q/dl_revision() support

The idea is to get the soc silicon revision from DIGPROG register Of
ANATOP(USB_ANALOG_DIGPROG), which will make kernel code independent
with bootloader which need pass the system_rev by ATAG.

This patch also will print the chip name and revision when kernel boot
up since this information is important for customer to know.

on i.mx6q TO1.1, it will print as the following:

CPU identified as i.MX6Q, silicon rev 1.1

Signed-off-by: Jason Liu <r64343@freescale.com>
11 years agoENGR00179127 Audio integration for AMFM module to ARD platform
Alejandro Sierra [Tue, 17 Apr 2012 18:52:34 +0000 (13:52 -0500)]
ENGR00179127 Audio integration for AMFM module to ARD platform

Audio integration of AMFM module to ARD platform IMX6Q and IMX6DL
rev A and rev B boards. Supported on ALSA for kernel 3.0.15.

Signed-off-by: Alejandro Sierra <b18039@freescale.com>
11 years agoENGR00179800 V4L2: Add VDOA tiled format post-processing support
Wayne Zou [Mon, 16 Apr 2012 09:48:31 +0000 (17:48 +0800)]
ENGR00179800 V4L2: Add VDOA tiled format post-processing support

Add VDOA tiled format post-processing support

Signed-off-by: Wayne Zou <b36644@freescale.com>
11 years agoENGR00179725 WM8962: remove 64KHz sample rate support
Gary Zhang [Tue, 17 Apr 2012 03:17:18 +0000 (11:17 +0800)]
ENGR00179725 WM8962: remove 64KHz sample rate support

because wm8962 codec does not support 64KHz sample
rate, no longer declare to support 64KHz:

Signed-off-by: Gary Zhang <b13634@freescale.com>
11 years agoENGR00179804 change NAND clock source from pll2_pfd_352M to pll2_pfd_400M
Allen Xu [Tue, 17 Apr 2012 06:53:22 +0000 (14:53 +0800)]
ENGR00179804 change NAND clock source from pll2_pfd_352M to pll2_pfd_400M

Due to pll2_pfd_352M would be used for LVDS, change NAND clock source to
pll2_pfd_400M.

Signed-off-by: Allen Xu <allen.xu@freescale.com>
11 years agoENGR00179685 MX6 clock:Cleanup LDB DI parent clock
Liu Ying [Mon, 16 Apr 2012 04:40:37 +0000 (12:40 +0800)]
ENGR00179685 MX6 clock:Cleanup LDB DI parent clock

According to ticket TKT071080, 0b011 for ldb_dix_clk_sel
field in CCM_CS2CDR is changed from pll3_pfd_540M to
mmdc_ch1 when we change from MX6Q TO1.0 to MX6Q TO1.1.
However, MX6DL uses mmdc_ch1 as LDB DI parent clock.
This patch corrects the LDB DI parent clock setting.

Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
11 years agoENGR00179747: MX6DL-Fix boot failure
Ranjani Vaidyanathan [Mon, 16 Apr 2012 18:30:36 +0000 (13:30 -0500)]
ENGR00179747: MX6DL-Fix boot failure

Fix the boot failure caused by:
8f0c21e06d4f7d0c7c078d6261ccd75f2a45c3ab
MX6- Add bus frequency scaling support

There is no SATA on MX6DL. Accessing SATA PHYs early in the boot
process causes the system to crash.

Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
11 years agoENGR00179696 MX6Q/UART : fix the wrong DMA tranfer direction.
Huang Shijie [Mon, 16 Apr 2012 02:54:12 +0000 (10:54 +0800)]
ENGR00179696 MX6Q/UART : fix the wrong DMA tranfer direction.

The current SDMA use the new DMA tranfer direction. But the UART still
uses the old. This cause the RX failed.
So use the new DMA transfer direction for UART.

Signed-off-by: Huang Shijie <b32955@freescale.com>
11 years agoENGR00179679 Fix usb gadget suspend issue connected to usb charger
Tony LIU [Mon, 16 Apr 2012 07:47:23 +0000 (15:47 +0800)]
ENGR00179679 Fix usb gadget suspend issue connected to usb charger

- the root cause of this issue is during resume process, USB clock
 is not turned on for this USB charger case so that the second
 suspend is processed without USB clock, it cause system hang
- in udc resume process, at this situation, we should exit low
 power mode to enable the b session valid intrrupt to close the
 usb clock when detach from usb charger

Signed-off-by: Tony LIU <junjie.liu@freescale.com>
11 years agoIMX/DMA : set the DMA direction in the sdma_control()
Huang Shijie [Fri, 18 Nov 2011 08:38:02 +0000 (16:38 +0800)]
IMX/DMA : set the DMA direction in the sdma_control()

Set the right DMA direction in the sdma_control(), else
we will get the wrong log when enable the DYNAMIC_DEBUG.

Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
11 years agoENGR00179647 MX6 clock:Correct LDB DI pclk for MX6Q TO1.1
Liu Ying [Fri, 13 Apr 2012 10:10:14 +0000 (18:10 +0800)]
ENGR00179647 MX6 clock:Correct LDB DI pclk for MX6Q TO1.1

This patch corrects LDB DI clock's parent clock to
be pll2_pfd_352M for both MX6Q TO1.1 and MX6Q TO1.0
according to ticket TKT071080(0b011 for ldb_dix_clk_sel
field in CCM_CS2CDR is changed from pll3_pfd_540M to
mmdc_ch1 when we change from MX6Q TO1.0 to MX6Q TO1.1).

Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
11 years agoENGR00179575 only set color depth if TV supports deep color
Alan Tull [Mon, 9 Apr 2012 19:36:07 +0000 (14:36 -0500)]
ENGR00179575 only set color depth if TV supports deep color

If TV's EDID indicates that deep color is not supported, then
write color depth field of HDMI_VP_PR_CD register to zero.

Signed-off-by: Alan Tull <r80115@freescale.com>
11 years agoENGR00179601 Synopsys approved hdmi fifo workaround - rev 3
Alan Tull [Thu, 5 Apr 2012 18:27:49 +0000 (13:27 -0500)]
ENGR00179601 Synopsys approved hdmi fifo workaround - rev 3

This patch includes some of the clk enable/disable changes from rev2

Check the version of the HDMI IP to determine whether the fifo
threshold needs to be high.  The i.Mx6dl version of the HDMI doesn't
need the workaround.  All other parts of the workaround are used
for both parts for code simplicity.

----------------------------------------------------------
For i.Mxq, set the Threshold of audio fifo as: FIFO depth - 2 (fixed
and independent of the number of channels actually used).

Use unspecified length ahb bursts (using fixed INCRx will make the
audio dma fail).

Additionally and in order to get it working on all conditions it will
be necessary to run the following sw steps at startup of video and audio
(or when video changes or audio changes):

1-Configure AUD_N1 and AUD_CTS1 registers with final value and let the
  AUD_N2, AUD_N3, AUD_CTS2 and AUD_CTS3 to 0s.
2-Configure start and end addresses of audio DMA registers.
3-Start DMA operation
4-Configure the AUD_CTS2 and AUD_CTS3 with the final value.
5-Configure the AUD_N2 and AUD_N3 with final value.

Signed-off-by: Alan Tull <r80115@freescale.com>
11 years agoENGR00179574: MX6- Add bus frequency scaling support
Ranjani Vaidyanathan [Tue, 7 Feb 2012 20:34:13 +0000 (14:34 -0600)]
ENGR00179574: MX6- Add bus frequency scaling support

Add support for scaling the bus frequency (both DDR
and ahb_clk).
The DDR and AHB_CLK are dropped to 24MHz when all devices
that need high AHB frequency are disabled and the CORE
frequency is at the lowest setpoint.
The DDR is dropped to 400MHz for the video playback usecase.
In this mode the GPU, FEC, SATA etc are disabled.

To scale the bus frequency, its necessary that all cores
except the core that is executing the DDR frequency change
are in WFE. This is achieved by generating interrupts on
un-used interrupts (Int no 139, 144, 145 and 146).

Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
11 years agoENGR00179582 MX6: Bypass PLL1 during WAIT
Ranjani Vaidyanathan [Thu, 23 Feb 2012 18:19:23 +0000 (12:19 -0600)]
ENGR00179582 MX6: Bypass PLL1 during WAIT

    When system is going to enter WAIT mode, set PLL1 to 24MHz
    so that ARM is running at 24MHz. This is a SW workaround for
    the WAIT mode issue.

Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
11 years agoENGR00179513-3 V4L2: Add VDOA tiled format support
Wayne Zou [Fri, 13 Apr 2012 00:28:06 +0000 (08:28 +0800)]
ENGR00179513-3 V4L2: Add VDOA tiled format support

Support for VDOA tiled format IPU_PIX_FMT_TILED_NV12 up to 1080p progressive
streams, and IPU_PIX_FMT_TILED_NV12F tiled format up to xga interlaced streams
currently.

Signed-off-by: Wayne Zou <b36644@freescale.com>
11 years agoENGR00179513-2 IPU: Add TILED_NV12_FRAME_SIZE macro for consistency
Wayne Zou [Fri, 13 Apr 2012 00:19:46 +0000 (08:19 +0800)]
ENGR00179513-2 IPU: Add TILED_NV12_FRAME_SIZE macro for consistency

VPU needs 4K align buffer address for tiled format data output.
Use this macro for IPU/V4L2/Apps to calculate the frame/field size.

Signed-off-by: Wayne Zou <b36644@freescale.com>
11 years agoENGR00179513-1 VDOA: update software state before start vdoa
Wayne Zou [Fri, 13 Apr 2012 00:16:05 +0000 (08:16 +0800)]
ENGR00179513-1 VDOA: update software state before start vdoa

Fix a bug when vdoa interrupt happens
before software state updated.

Signed-off-by: Wayne Zou <b36644@freescale.com>
11 years agoENGR00170747 gpu driver : add AXI BUS ERROR message
b07117 [Wed, 21 Dec 2011 13:32:02 +0000 (21:32 +0800)]
ENGR00170747 gpu driver : add AXI BUS ERROR message

AXI BUS ERROR may occur in very low possibility,
this debug message exist before 4.4.2, but removed in 4.6.x,
need add it back to trace critical gpu issue

Signed-off-by: Li Xianzhong <b07117@freescale.com>
Signed-off-by: Loren Huang <b02279@freescale.com>
Acked-by: Lily Zhang
11 years agoENGR00179631 MX6 SabreSD: Add MIPI DSI Display support
Wayne Zou [Fri, 13 Apr 2012 06:16:21 +0000 (14:16 +0800)]
ENGR00179631 MX6 SabreSD: Add MIPI DSI Display support

Add MIPI DSI Display support on mx6 SabreSD board.
MIPI DSI needs pll3_pfd_540M clock source for 540MHz.
if using ldb, the pll3_pfd_540M clock will be changed to 454Mhz.
So add command line option disable_ldb when using MIPI DSI display.

Signed-off-by: Wayne Zou <b36644@freescale.com>
11 years agoENGR00179642 Remove a workaround for suspend/resume
Loren Huang [Fri, 13 Apr 2012 10:14:02 +0000 (18:14 +0800)]
ENGR00179642 Remove a workaround for suspend/resume

Remove a workaround for suspend/resume:
The workaround is turn on clock before gpu entering suspend.
After clock code bug is fixed, this workaround becomes no necessary.

Signed-off-by: Loren Huang <b02279@freescale.com>
Acked-by: Lily Zhang
11 years agoENGR00179628-2 MX6: add ssi info in sdma
Gary Zhang [Fri, 13 Apr 2012 08:32:07 +0000 (16:32 +0800)]
ENGR00179628-2 MX6: add ssi info in sdma

add ssi dual-fifo info in sdma structure

Signed-off-by: Gary Zhang <b13634@freescale.com>
11 years agoENGR00179628-1 SSI: enable dual-fifo feature as default
Gary Zhang [Fri, 13 Apr 2012 08:30:54 +0000 (16:30 +0800)]
ENGR00179628-1 SSI: enable dual-fifo feature as default

enable SSI dual-fifo feature as default setting

Signed-off-by: Gary Zhang <b13634@freescale.com>
11 years agoENGR00179621 MX6 PCIE: bring up PCIE on i.MX6 SD board
Richard Zhu [Thu, 12 Apr 2012 01:54:30 +0000 (09:54 +0800)]
ENGR00179621 MX6 PCIE: bring up PCIE on i.MX6 SD board

* Bring up the PCIE on i.MX6 SD board
* Add the PCIE PHY access routines
* Wrapper the board related codes by register one
  platform driver and data

Signed-off-by: Richard Zhu <r65037@freescale.com>
11 years agoENGR00179498-2 SDMA: fix p2p sdma script error
Chen Liangjun [Thu, 12 Apr 2012 06:55:55 +0000 (14:55 +0800)]
ENGR00179498-2 SDMA: fix p2p sdma script error

Update p2p script firmware address in plat-imx-dma.c for MX6Q.

Signed-off-by: Chen Liangjun <b36089@freescale.com>
11 years agoENGR00179498-1 SDMA: fix p2p sdma script error
Chen Liangjun [Thu, 12 Apr 2012 06:47:19 +0000 (14:47 +0800)]
ENGR00179498-1 SDMA: fix p2p sdma script error

The p2p script in SDMA binary file is invalid. The ESAI call ASRC
can't work properly with this firmware.

Update the firmware and script address.

Signed-off-by: Chen Liangjun <b36089@freescale.com>
11 years agoENGR00179485 fix CTS hang up issue
Richard Liu [Fri, 13 Apr 2012 01:03:37 +0000 (09:03 +0800)]
ENGR00179485 fix CTS hang up issue

fix random hang up issue especially run CTS provided by Viv

Signed-off-by: Richard Liu <r66033@freescale.com>
Acked-by: Lily Zhang
11 years agoENGR00179510 ipu capture: fix system hang when running capture
Yuxi Sun [Thu, 12 Apr 2012 07:23:08 +0000 (15:23 +0800)]
ENGR00179510 ipu capture: fix system hang when running capture

Add _ipu_get() and _ipu_put() when calling ipu_csi_get_sensor_protocol
function.

Signed-off-by: Yuxi Sun <b36102@freescale.com>
11 years agoENGR00179284-4 support ONFI NAND device on mx6q_arm2_pop board
Allen Xu [Tue, 10 Apr 2012 09:02:36 +0000 (17:02 +0800)]
ENGR00179284-4 support ONFI NAND device on mx6q_arm2_pop board

if the NAND chip supports ONFI feature and the board supports ONFI
DDR transfer mode, users could enable ONFI DDR transfer by add command
line parameter "onfi_support"

Signed-off-by: Allen Xu <allen.xu@freescale.com>
11 years agoENGR00179284-3 support ONFI NAND device on mx6q_arm2_pop board
Allen Xu [Tue, 10 Apr 2012 09:01:07 +0000 (17:01 +0800)]
ENGR00179284-3 support ONFI NAND device on mx6q_arm2_pop board

Add bch and gpmi register define for ONFI ddr feature

Signed-off-by: Allen Xu <allen.xu@freescale.com>
11 years agoENGR00179284-2 support ONFI NAND device on mx6q_arm2_pop board
Allen Xu [Tue, 10 Apr 2012 08:56:38 +0000 (16:56 +0800)]
ENGR00179284-2 support ONFI NAND device on mx6q_arm2_pop board

enable ONFI NAND feature by command line parameter "onfi_support"

Signed-off-by: Allen Xu <allen.xu@freescale.com>
11 years agoENGR00179284-1 support ONFI NAND device on mx6q_arm2_pop board
Allen Xu [Tue, 10 Apr 2012 08:53:01 +0000 (16:53 +0800)]
ENGR00179284-1 support ONFI NAND device on mx6q_arm2_pop board

Add a platform data to indicate whether the board support ONFI nand

Signed-off-by: Allen Xu <allen.xu@freescale.com>
11 years agoENGR00179497-2 MX6Q SabreSD: fix SPI nor flash pin config
Robin Gong [Thu, 12 Apr 2012 06:44:40 +0000 (14:44 +0800)]
ENGR00179497-2 MX6Q SabreSD: fix SPI nor flash pin config

Default SPI nor flash pin config is wrong, correct it for SabreSD RevB
Signed-off-by: Robin Gong <B38343@freescale.com>
11 years agoENGR00179497-1 ECSPI: disable ecspi clock after probe and spi transfer
Robin Gong [Thu, 12 Apr 2012 06:40:42 +0000 (14:40 +0800)]
ENGR00179497-1 ECSPI: disable ecspi clock after probe and spi transfer

before, it enable spi clock after probe, never been disable unless driver
removed. To reduce power, disable clock after probe, and enable it before
every spi transfer and disable it after spi transfer
Signed-off-by: Robin Gong <B38343@freescale.com>
11 years agoENGR00179408 MX6DL:Increasing CPU voltage for 800MHz/400MHz/200MHz work points
Lin Fuzhen [Thu, 12 Apr 2012 01:45:10 +0000 (09:45 +0800)]
ENGR00179408 MX6DL:Increasing CPU voltage for 800MHz/400MHz/200MHz work points

It need add 25mV to 800MHz/400MHz/200MHz work points for MX6DL,
otherwise system will crash when cpu freq switch to these work points

Signed-off-by: Lin Fuzhen <fuzhen.lin@freescale.com>
11 years agoENGR00179367: cs42888 record fix damp routing settings
Adrian Alonso [Tue, 10 Apr 2012 16:04:10 +0000 (11:04 -0500)]
ENGR00179367: cs42888 record fix damp routing settings

* Fix cs42888 record DAMP routing settings for ADCx

Signed-off-by: Adrian Alonso <aalonso@freescale.com>
11 years agoENGR00179226: imx-esai remove tx personal reset during record
Adrian Alonso [Mon, 9 Apr 2012 17:16:53 +0000 (12:16 -0500)]
ENGR00179226: imx-esai remove tx personal reset during record

* Remove transmitter personal reset during stream record
  this could potencially block concurrent play/record support.
* Remove receiver personal reset calls, rx is always
  operational.

Signed-off-by: Adrian Alonso <aalonso@freescale.com>
11 years agoENGR00179426-2: i.mx6q: iomux: code clean up
Jason Liu [Wed, 11 Apr 2012 09:21:46 +0000 (17:21 +0800)]
ENGR00179426-2: i.mx6q: iomux: code clean up

Remove the dead definiton which never used by iomux-v3 framework

Signed-off-by: Jason Liu <r64343@freescale.com>
11 years agoENGR00179426-1 i.mx6: iomux: NO_PAD_I/NO_PAD_MUX not defined
Jason Liu [Wed, 11 Apr 2012 09:16:36 +0000 (17:16 +0800)]
ENGR00179426-1 i.mx6: iomux: NO_PAD_I/NO_PAD_MUX not defined

NO_PAD_I/NO_PAD_MUX not defined, which will cause build error
According to iomux-v3.h, the NO_PAD_I/NO_PAD_MUX should be 0
for the pins which does not have PAD/MUX config.

Signed-off-by: Jason Liu <r64343@freescale.com>
11 years agoENGR00178597 [MX6DL/S] Multi-instance test in GC880 cause system hang
Larry Li [Tue, 10 Apr 2012 09:12:51 +0000 (17:12 +0800)]
ENGR00178597 [MX6DL/S] Multi-instance test in GC880 cause system hang

In our code 3d sharder clock uses 3d core clock CCGR field as its
enable bit. That works for MX6Q. But MX6DL uses 3d sharder clock
as 2d core clock, while disable 2d core clock, it will disable 3d
core by mistake.
To fix it, remove the enable bit setting of 3d shader clock in
clock.c file.

Signed-off-by: Larry Li <b20787@freescale.com>
11 years agoENGR00177241-4 mx6 close APBH DMA clock when no I/O operation
Allen Xu [Tue, 10 Apr 2012 03:39:11 +0000 (11:39 +0800)]
ENGR00177241-4 mx6 close APBH DMA clock when no I/O operation

Select APBH DMA automatically when enable GPMI NAND module.

Signed-off-by: Allen Xu <allen.xu@freescale.com>
11 years agoENGR00177241-3 mx6 close APBH DMA clock when no I/O operation
Allen Xu [Tue, 10 Apr 2012 03:38:24 +0000 (11:38 +0800)]
ENGR00177241-3 mx6 close APBH DMA clock when no I/O operation

When there is no NAND I/O operation, close all the reference
clock, include GPMI,BCH and APBH clock.

Signed-off-by: Allen Xu <allen.xu@freescale.com>
11 years agoENGR00177241-2 mx6 close APBH DMA clock when no I/O operation
Allen Xu [Tue, 10 Apr 2012 03:37:37 +0000 (11:37 +0800)]
ENGR00177241-2 mx6 close APBH DMA clock when no I/O operation

When there is no NAND I/O operation, close all the reference
clock, include GPMI,BCH and APBH clock.

Signed-off-by: Allen Xu <allen.xu@freescale.com>
11 years agoENGR00177241-1 mx6 close APBH DMA clock when no I/O operation
Allen Xu [Tue, 10 Apr 2012 03:35:31 +0000 (11:35 +0800)]
ENGR00177241-1 mx6 close APBH DMA clock when no I/O operation

When there is no NAND I/O operation, close all the reference
clock, include GPMI,BCH and APBH clock.

Signed-off-by: Allen Xu <allen.xu@freescale.com>
11 years agoENGR00179230: imx-esai add record support for S24_LE format
Adrian Alonso [Mon, 9 Apr 2012 17:18:08 +0000 (12:18 -0500)]
ENGR00179230: imx-esai add record support for S24_LE format

* Add record support for S24_LE and
  S20_3LE bit format.

Signed-off-by: Adrian Alonso <aalonso@freescale.com>
11 years agoENGR00179122 Fix SRCR configuration on SSI interface
Alejandro Sierra [Tue, 10 Apr 2012 17:26:49 +0000 (12:26 -0500)]
ENGR00179122 Fix SRCR configuration on SSI interface

SRCR was bad configured on the DAI format
configuration function on the imx-ssi.c file.
When SSI was configured as master.

Signed-off-by: Alejandro Sierra <b18039@freescale.com>
11 years agoENGR00179123 AMFM I2C module to ARD platform for IMX6Q and IMX6DL
Alejandro Sierra [Sat, 7 Apr 2012 01:32:55 +0000 (20:32 -0500)]
ENGR00179123 AMFM I2C module to ARD platform for IMX6Q and IMX6DL

Basic I2C module integration of AMFM module to ARD platform IMX6Q
and IMX6DL rev A and rev B boards. Supported for kernel 3.0.15.

Signed-off-by: Alejandro Sierra <b18039@freescale.com>
11 years agoENGR00179129 Board support for I2C AMFM module for IMX6Q and IMX6DL
Alejandro Sierra [Sat, 7 Apr 2012 01:48:22 +0000 (20:48 -0500)]
ENGR00179129 Board support for I2C AMFM module for IMX6Q and IMX6DL

Modifications in ARD board file to support the Audio for AMFM
module for IMX6Q and IMX6DL (REV A and REV B) Supported for
kernel 3.0.15. Also it contains the I2C configuration for
the AMFM module.

Signed-off-by: Alejandro Sierra <b18039@freescale.com>
11 years agofutex: Simplify return logic
Thomas Gleixner [Wed, 15 Feb 2012 11:17:09 +0000 (12:17 +0100)]
futex: Simplify return logic

No need to assign ret in each case and break. Simply return the result
of the handler function directly.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Darren Hart <dvhart@linux.intel.com>
Signed-off-by: Huang Shijie <b32955@freescale.com>
11 years agoENGR00177317 - EPDC fb: Add clean-up for new EPDC buffer allocation scheme
Danny Nold [Tue, 20 Mar 2012 03:17:00 +0000 (22:17 -0500)]
ENGR00177317 - EPDC fb: Add clean-up for new EPDC buffer allocation scheme

- Added clean-up for new PxP output buffer allocation scheme.  Clean-up
covers cases where probe fails and where module is removed.

Signed-off-by: Danny Nold <dannynold@freescale.com>
11 years agoENGR00175572 add NAND write verify support
Allen Xu [Tue, 28 Feb 2012 10:01:30 +0000 (18:01 +0800)]
ENGR00175572 add NAND write verify support

Add NAND write verify support in NAND code

Signed-off-by: Allen Xu <allen.xu@freescale.com>
11 years agoENGR00179178 [RTC]Enable both wakealarm and common power wakeup
Anson Huang [Mon, 9 Apr 2012 07:43:40 +0000 (15:43 +0800)]
ENGR00179178 [RTC]Enable both wakealarm and common power wakeup

For RTC driver, as not all RTCs support alarm and wakeup, so the
framework only support alarm or wakeup, not both of them, as our
rtc can support alarm and wakeup function, to simplify the unit
test interface for power off and wakeup, we add both wakealarm and
common power wakeup sysfs interface to our RTC driver.

Signed-off-by: Anson Huang <b20788@freescale.com>
11 years agoENGR00179130 Setting 480p Hsync and Vsync polarity is incorrect
Sandor Yu [Sat, 7 Apr 2012 08:34:15 +0000 (16:34 +0800)]
ENGR00179130 Setting 480p Hsync and Vsync polarity is incorrect

Fix IPU DI registr DI_GENERAL incorrect initialize.

Signed-off-by: Sandor Yu <R01008@freescale.com>
11 years agoENGR00178612 ESAI:add support for esai call asrc
Chen Liangjun [Wed, 28 Mar 2012 05:36:18 +0000 (13:36 +0800)]
ENGR00178612 ESAI:add support for esai call asrc

ESAI can call ASRC for sample rate convert if the input sample rate
is not support.
1 ESAI will decide whether to use ASRC for sample rate convert in
  imx-cs42888.c. If ASRC is need, the asrc_enable will be set.
2 In imx-pcm-dma-mx2.c, according to the value of asrc_enable, the
  dma driver would decide whether to alloc another p2p dma channel to
  support MEMORY-->ASRC_INPUT-->ASRC_OUTPUT-->ESAI_TX_FIFO route.
3 The code support 2 channel,24/32 bit audio file playback.

Signed-off-by: Chen Liangjun <b36089@freescale.com>
11 years agoENGR00178875-3 VDOA: Add VDOA driver support on i.MX6
Wayne Zou [Thu, 5 Apr 2012 12:03:29 +0000 (20:03 +0800)]
ENGR00178875-3 VDOA: Add VDOA driver support on i.MX6

VDOA needs to sync with IPU.
Add VDOA driver support under IPU drivers.

Signed-off-by: Wayne Zou <b36644@freescale.com>
11 years agoENGR00178875-2 VDOA: Add vdoa support on i.MX6 SOC platform
Wayne Zou [Wed, 4 Apr 2012 12:42:18 +0000 (20:42 +0800)]
ENGR00178875-2 VDOA: Add vdoa support on i.MX6 SOC platform

Add tiled format macros: IPU_PIX_FMT_TILED_NV12 and
IPU_PIX_FMT_TILED_NV12F

Signed-off-by: Wayne Zou <b36644@freescale.com>
11 years agoENGR00178875-1 VDOA: Add vdoa support on i.MX6 SOC platform
Wayne Zou [Wed, 4 Apr 2012 12:38:37 +0000 (20:38 +0800)]
ENGR00178875-1 VDOA: Add vdoa support on i.MX6 SOC platform

Add vdoa support on i.MX6 SOC platform

Signed-off-by: Wayne Zou <b36644@freescale.com>
11 years agoENGR00172303 - FEC : fix 'eth0: tx queue full!' issue.
Fugang Duan [Fri, 6 Apr 2012 04:59:36 +0000 (12:59 +0800)]
ENGR00172303 - FEC : fix 'eth0: tx queue full!' issue.

The issue is hard to reproduce in normal envrionment. And
the reproduce rate is about 40% when doing VTE auto test.

while the driver did report being busy when the link is down
or no transmission buffers are available, it did not stop the
queue, causing instant retries. furthermore, transmission being
triggered with link down was caused by unconditional queue
wakes, especially on timeouts.

Now, wake queue only if link is up and transmission buffers
are available, and dont forget to wake queue when link has
been adjusted. next, add stop queue notification upon driver
induced transmission problems, so network stack has a chance
to handle the situation.

Signed-off-by: Fugang Duan <B38611@freescale.com>
11 years agoENGR00177235-2 SDMA: add p2p dma mode
Chen Liangjun [Sat, 31 Mar 2012 06:25:23 +0000 (14:25 +0800)]
ENGR00177235-2 SDMA: add p2p dma mode

Add code to support p2p dma mode.Add membership in imx_dma_data
struct to support P2P dma script. Because the P2P dma script
need 2 dma request to trigger DMA burst.

Signed-off-by: Chen Liangjun <b36089@freescale.com>
11 years agoENGR00177235-1 SDMA: add p2p dma mode
Chen Liangjun [Tue, 20 Mar 2012 05:18:25 +0000 (13:18 +0800)]
ENGR00177235-1 SDMA: add p2p dma mode

Add support for p2p(peripheral to peripheral) dma mode in SDMA
module.
1 Add p2p script membership in struct sdma_channel to support
  device to device tranfer.
2 P2P dma script need more configure information then memory to
  peripheral or peripheral to memory script. we configure these
  information into watermark_level.

Signed-off-by: Chen Liangjun <b36089@freescale.com>
11 years agoENGR00179077 ASRC:delete unused variable
Chen Liangjun [Fri, 6 Apr 2012 09:22:34 +0000 (17:22 +0800)]
ENGR00179077 ASRC:delete unused variable

Delete unused variable busy_lock in mxc_asrc.h.

Signed-off-by: Chen Liangjun <b36089@freescale.com>
11 years agoENGR00179059 RTC: enable wakealarm attribute
Frank Li [Fri, 6 Apr 2012 04:58:40 +0000 (12:58 +0800)]
ENGR00179059 RTC: enable wakealarm attribute

Set 10s wake alarm from now by below command

echo +10 > /sys/class/rtc/rtc0/wakealarm

Signed-off-by: Frank Li <Frank.Li@freescale.com>
11 years agoARM: assembler.h: Add string declaration macro
Dave Martin [Thu, 23 Jun 2011 16:10:05 +0000 (17:10 +0100)]
ARM: assembler.h: Add string declaration macro

Declaring strings in assembler source involves a certain amount of
tedious boilerplate code in order to annotate the resulting symbol
correctly.

Encapsulating this boilerplate in a macro should help to avoid some
duplication and the occasional mistake.

Signed-off-by: Dave Martin <dave.martin@linaro.org>
Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
Signed-off-by: Huang Shijie <b32955@freescale.com>
11 years agoARM: 7301/1: Rename the T() macro to TUSER() to avoid namespace conflicts
Catalin Marinas [Wed, 25 Jan 2012 10:38:13 +0000 (11:38 +0100)]
ARM: 7301/1: Rename the T() macro to TUSER() to avoid namespace conflicts

This macro is used to generate unprivileged accesses (LDRT/STRT) to user
space.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Huang Shijie <b32955@freescale.com>
11 years agoENGR00178939 [mx6] usb host, msleep may be called in atomic context
Tony LIU [Thu, 5 Apr 2012 06:11:13 +0000 (14:11 +0800)]
ENGR00178939 [mx6] usb host, msleep may be called in atomic context

- change msleep(1) to udelay(500)
- msleep may be called in atomic context, which will cause
  warning message

Signed-off-by: Tony LIU <junjie.liu@freescale.com>
11 years agoENGR00178916: imx-esai improve dump regs format
Adrian Alonso [Wed, 4 Apr 2012 15:01:09 +0000 (10:01 -0500)]
ENGR00178916: imx-esai improve dump regs format

* Improve dump regs format to easily correlate
  register content.
* Update copyrigth year.

Signed-off-by: Adrian Alonso <aalonso@freescale.com>
11 years agoENGR00178915: imx6 clock fix build warnings
Adrian Alonso [Tue, 3 Apr 2012 21:01:23 +0000 (16:01 -0500)]
ENGR00178915: imx6 clock fix build warnings

* Fix build warnings
* clock.c: In function '_clk_pll1_enable':
  warning: no return statement in function returning non-void
* clock.c: In function 'mx6_clocks_init':
  warning: unused variable 'reg'

Signed-off-by: Adrian Alonso <aalonso@freescale.com>
11 years agoENGR00178951-2 SYSRQ: enable CONFIG_MAGIC_SYSRQ by default
Jason Liu [Thu, 5 Apr 2012 07:29:57 +0000 (15:29 +0800)]
ENGR00178951-2 SYSRQ: enable CONFIG_MAGIC_SYSRQ by default

SYSRQ is very useful for kernel debug thus enable it by default.

SYSRQ support serial port, we can send the command via minicom:

CTRL A + F (send BRK) + T: to dump the task information

Enable SYSRQ by default will not involve any performance drop

Signed-off-by: Jason Liu <r64343@freescale.com>
11 years agoENGR00178951-1 serial/imx: dead lock dedected when handle sysrq
Jason Liu [Sun, 1 Apr 2012 08:33:25 +0000 (16:33 +0800)]
ENGR00178951-1 serial/imx: dead lock dedected when handle sysrq

imx_rxint -> spin_lock_irqsave(&sport->port.lock, flags);

And then it will call the following functions:

uart_handle_sysrq_char -> handle_sysrq -> printk ->
__call_console_write_drivers -> imx_console_write ->

Here the imx_console_write function will call:
spin_lock_irqsave(&sport->port.lock, flags);

The A-A deadlock happens. We need spin_unlock before handle sysrq char
and spin_lock again after it.

Signed-off-by: Jason Liu <r64343@freescale.com>
11 years agoserial/imx: support to handle break character
Hui Wang [Wed, 24 Aug 2011 09:41:47 +0000 (17:41 +0800)]
serial/imx: support to handle break character

The imx UART hardware controller can identify BREAK character and the
imx_set_termios() can accept BRKINT set by users, but current existing
imx_rxint() can't pass BREAK character and TTY_BREAK to the tty layer
as other serial drivers do (8250.c omap_serial.c).

Here add code to handle BREAK character and pass it to tty layer.

To detect error occurrence, i use URXD_ERR to replace (URXD_OVRRUN |
URXD_FRMERR | ...) because any kind of error occurs, URXD_ERR will
always be set to 1.

I put the URXD_BRK to the first place to check since when BREAK error
occurs, not only URXD_BRK is set to 1, but also URXD_PRERR and
URXD_FRMERR are all set to 1. This arrangement can filter out fake
parity and frame errors when BREAK error occurs.

Signed-off-by: Hui Wang <jason77.wang@gmail.com>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Alan Cox <alan@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
(cherry picked from commit 019dc9ea8d528eb3640bbba604e1e5a2f6994b1f)

11 years agoENGR00178932 USB: fix two USB otg common bug for i.MX6
make shi [Thu, 5 Apr 2012 05:09:18 +0000 (13:09 +0800)]
ENGR00178932 USB: fix two USB otg common bug for i.MX6

 - Built in gadget device driver, plug in USB cable  with no response,
  the reason is USB VBUS wakeup is not enable after OTG switch,make
  sure pdata->port_enables is 1 even if the pdata is otg device pdata.

 -Without modprobe or built in  gadget device driver,after plug out
  the USB otg cable,will output "wait otg vbus change timeout!".The
  reason is we get error otgsc data  after USB enter low power mode.

Signed-off-by: make shi <b15407@freescale.com>
11 years agoENGR00177281-5 WM8962: add record feature
Gary Zhang [Thu, 5 Apr 2012 08:23:39 +0000 (16:23 +0800)]
ENGR00177281-5 WM8962: add record feature

1. add amic and dmic support.
2. update wm8962 codec driver

Signed-off-by: Gary Zhang <b13634@freescale.com>
11 years agoENGR00177581-4 MX6: add wm8962 mic support
Gary Zhang [Thu, 5 Apr 2012 08:19:32 +0000 (16:19 +0800)]
ENGR00177581-4 MX6: add wm8962 mic support

1. add amic_detect pin
2. add dmic_gpio init

Signed-off-by: Gary Zhang <b13634@freescale.com>
11 years agoENGR00160472 - MX6: add Ethernet ANSI/IEEE 802.2 LLC support in defconfig.
Fugang Duan [Thu, 5 Apr 2012 09:15:30 +0000 (17:15 +0800)]
ENGR00160472 - MX6: add Ethernet ANSI/IEEE 802.2 LLC support in defconfig.

- Add Ethernet ANSI/IEEE 802.2 LLC support. And the packet with
  IP head "ETH_P_802_2" will be processed in Ethernet stack L3 layer.
- If disable the feature, ethernet stack will drop the LLC packets.

Signed-off-by: Fugang Duan <B38611@freescale.com>
11 years agoENGR00178646-2 [MX6]Add SD1 and SD2 to interactive governor
Anson Huang [Sun, 1 Apr 2012 10:37:10 +0000 (18:37 +0800)]
ENGR00178646-2 [MX6]Add SD1 and SD2 to interactive governor

Different have different SD ports, need to add all SD irqs to
be condition of CPUfreq change and adjust the default irq threshold.

Signed-off-by: Anson Huang <b20788@freescale.com>
11 years agoENGR00178646-1 [CPUFreq]Fix interactive governor bug
Anson Huang [Sun, 1 Apr 2012 10:33:58 +0000 (18:33 +0800)]
ENGR00178646-1 [CPUFreq]Fix interactive governor bug

1. When system not boot up all cores, interactive governor
   will not work;
2. Adjust the default timer_rate to 50ms instead of 20ms to
   avoid too many freq up/down change.

Signed-off-by: Anson Huang <b20788@freescale.com>
11 years agoENGR00175724-2 IPU: change ipu_device thread process mode to interrupt mode.
Wayne Zou [Wed, 29 Feb 2012 08:39:58 +0000 (16:39 +0800)]
ENGR00175724-2 IPU: change ipu_device thread process mode to interrupt mode.

IPU: change ipu_device thread process method to interrupt drive mode
to get better IPU post-processing load balance.

Signed-off-by: Wayne Zou <b36644@freescale.com>
11 years agoENGR00175724-1 IPU: change ipu_device thread process mode to interrupt mode.
Wayne Zou [Wed, 29 Feb 2012 08:38:00 +0000 (16:38 +0800)]
ENGR00175724-1 IPU: change ipu_device thread process mode to interrupt mode.

IPU: change ipu_device thread process method to interrupt drive mode
to get better IPU post-processing load balance.

Signed-off-by: Wayne Zou <b36644@freescale.com>
11 years agoENGR00178763: MX6-Fix TO1.0 boot-fail issue
Ranjani Vaidyanathan [Mon, 2 Apr 2012 21:19:29 +0000 (16:19 -0500)]
ENGR00178763: MX6-Fix TO1.0 boot-fail issue

TO1.0 parts donot boot properly after the following commit:
88d3af87222b37e454acd6a8de3b0cf18180da32
MX6-Switch ARM_CLK to PLL2_400MHz when ARM freq
is below 400MHz.

Correct gpt_clk was not getting enabled. Fix by adding the
appropriate gpt_clk.

Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
11 years agoENGR00178584 uart3 pins configuration
Alejandro Sierra [Mon, 2 Apr 2012 20:28:38 +0000 (15:28 -0500)]
ENGR00178584 uart3 pins configuration

Uart 3 and NFC pins are shared.
Uart 3 enablement is done by passing an early parameter
called "uart3" from uboot. Both interfaces (Uart3 and NFC)
can NOT coexist on the same configuration at the same time.

Signed-off-by: Alejandro Sierra <b18039@freescale.com>
11 years agoENGR00178642-1 gpu-viv: fix suspend/resume issue for #304
Richard Zhao [Sun, 1 Apr 2012 08:49:30 +0000 (16:49 +0800)]
ENGR00178642-1 gpu-viv: fix suspend/resume issue for #304

Signed-off-by: Richard Zhao <richard.zhao@freescale.com>
Acked-by: Lily Zhang
11 years agoENGR00178631 MX6: fix audmux build error
Gary Zhang [Sun, 1 Apr 2012 05:37:55 +0000 (13:37 +0800)]
ENGR00178631 MX6: fix audmux build error

fix the build error for audmux located at
drivers\mxc\dam

Signed-off-by: Gary Zhang <b13634@freescale.com>
11 years agoENGR00178629 i.MX6 sabresd:support software power off by SNVS setting
Robin Gong [Sun, 1 Apr 2012 04:38:22 +0000 (12:38 +0800)]
ENGR00178629 i.MX6 sabresd:support software power off by SNVS setting

On sabresd board, PMIC_ON_REQ control pmic power on/off, we can set TOP and
DP_EN of SNVS_LPCR to implement power off by software. On this way,SNVS RTC
alarm can work after power off. The description of register can be found on
other SNVS block document which provided by IC team, not i.MX6 RM.

Signed-off-by: Robin Gong <B38343@freescale.com>
11 years agoENGR00178582 Remove uart2 early parameter
Alejandro Sierra [Sat, 31 Mar 2012 02:08:21 +0000 (20:08 -0600)]
ENGR00178582 Remove uart2 early parameter

UART2 and CAN interface do not have pins in common.
Therefore uart2 early parameter is not required.

Signed-off-by: Alejandro Sierra <b18039@freescale.com>
11 years agoENGR00178581 - EPDC fb: Fix regulator-related EPDC failure on SabreSD
Danny Nold [Fri, 30 Mar 2012 20:25:33 +0000 (15:25 -0500)]
ENGR00178581 - EPDC fb: Fix regulator-related EPDC failure on SabreSD

Remove call to regulator_has_full_constraints() from Max17135 EPD PMIC
initialization code, since leaving it enabled results in a failure of
system to load properly - key regulators are disabled when 'epdc' is added
to the kernel command line.

Signed-off-by: Danny Nold <dannynold@freescale.com>
11 years agoENGR00176366: MX6-Switch ARM_CLK to PLL2_400MHz when ARM freq is below 400MHz.
Ranjani Vaidyanathan [Wed, 7 Mar 2012 18:48:21 +0000 (12:48 -0600)]
ENGR00176366: MX6-Switch ARM_CLK to PLL2_400MHz when ARM freq is below 400MHz.

PLL1 can be disabled whenever ARM_CLK is below 400MHz since
ARM_CLK can be sourced from PLL2_PFD_400MHz.

Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
11 years agoENGR00178552 MX6XX_SABRESD: update pin mux for revB board.
Zhang Jiejing [Fri, 30 Mar 2012 10:33:17 +0000 (18:33 +0800)]
ENGR00178552 MX6XX_SABRESD: update pin mux for revB board.

update some pin mux of revB board.
fix i2c3 not work on sabre6q board, and change related pins.

Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
11 years agommc: block: fixed NULL pointer dereference
Jaehoon Chung [Wed, 13 Jul 2011 08:02:16 +0000 (17:02 +0900)]
mmc: block: fixed NULL pointer dereference

We already check for ongoing async transfers when handling discard
requests, but not in mmc_blk_issue_flush().  This patch fixes that
omission.

Tested with an SDHCI controller and eMMC4.41.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Per Forlin <per.forlin@linaro.org>
Cc: <stable@kernel.org>
Signed-off-by: Chris Ball <cjb@laptop.org>
11 years agoENGR00178505 [MX6]Enable performance and ondemand governor
Anson Huang [Fri, 30 Mar 2012 08:01:00 +0000 (16:01 +0800)]
ENGR00178505 [MX6]Enable performance and ondemand governor

Enable performance and ondemand governor for CPUFreq, but
default governor is still interactive.

Signed-off-by: Anson Huang <b20788@freescale.com>
11 years agoENGR00178456 IPUv3 fb:Unblank primary fb only by default
Liu Ying [Fri, 30 Mar 2012 01:22:00 +0000 (09:22 +0800)]
ENGR00178456 IPUv3 fb:Unblank primary fb only by default

This patch changes IPUv3 fb probe function logic to
unblank the primary fb only by default so that the
secondary fb using IPU DP BG channel won't be unblanked
when system boot-ups. This avoids the HDMI fb(as the
secondary fb using IPU DP BG channel) is unblanked
accidentally without plugging in HDMI cable.

Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit 2c8188de61f84e40e26e662138af5ef4f81a0969)

11 years agoENGR00177932 - i.MX6 sabresd : Recorrect fec phy AR8031 rework.
Fugang Duan [Mon, 26 Mar 2012 09:30:24 +0000 (17:30 +0800)]
ENGR00177932 - i.MX6 sabresd : Recorrect fec phy AR8031 rework.

- i.MX6 sabresd board revA and revB adopt Atheros AR8031 phy.
  Recorrect the fec phy AR8031 rework.

Signed-off-by: Fugang Duan <B38611@freescale.com>
11 years agoENGR00178458 - WM8962 regulator constraint fix to prevent unwanted disable
Danny Nold [Fri, 30 Mar 2012 02:28:14 +0000 (21:28 -0500)]
ENGR00178458 - WM8962 regulator constraint fix to prevent unwanted disable

SPKVDD regulator was being disabled whenever EPDC was included in the
image, because the EPD PMIC initialization code includes an invocation
of regulator_has_full_constraints().  This causes all regulators with
zero ref count to be disabled as part of a late_initcall.  To prevent
this disable (which breaks ethernet and DHCP), set regulator to
have boot_on attribute, so that it will not be disabled at end of
driver loading sequence.

Signed-off-by: Danny Nold <dannynold@freescale.com>