Eric Huang [Mon, 11 Apr 2016 18:28:55 +0000 (14:28 -0400)]
drm/amd/powerplay: fix fan speed percent setting error on Fiji
Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Eric Huang [Mon, 11 Apr 2016 18:27:51 +0000 (14:27 -0400)]
drm/amd/powerplay: fix fan speed percent setting error on Tonga
Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Felix Kuehling [Fri, 8 Apr 2016 01:42:17 +0000 (21:42 -0400)]
drm/ttm: Fix TTM BO accounting
TTM BO accounting is out of sync with how memory is really allocated
in ttm[_dma]_tt_alloc_page_directory. This resulted in excessive
estimated overhead with many small allocations.
ttm_dma_tt_alloc_page_directory makes a single allocation for three
arrays: pages, DMA and CPU addresses. It uses drm_calloc_large, which
uses kmalloc internally for allocations smaller than PAGE_SIZE.
ttm_round_pot should be a good approximation of its memory usage both
above and below PAGE_SIZE.
Reviewed-by: Thomas Hellstrom <thellstrom@vmware.com> Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Monk Liu <monk.liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
v2:
- Make firmware version check correctly. Firmware
versions >= 1.80 should all support 40 UVD
instances.
- Replace AMDGPU_MAX_UVD_HANDLES with max_handles
variable.
v1:
- The firmware can handle upto 40 UVD sessions.
Signed-off-by: Arindam Nath <arindam.nath@amd.com> Signed-off-by: Ayyappa Chandolu <ayyappa.chandolu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nils Wallménius [Sun, 10 Apr 2016 14:30:04 +0000 (16:30 +0200)]
drm/amd: make some function-local tables static const
These tables were initialized on stack on each call, avoid that
and save a little bit of text size.
Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Nils Wallménius <nils.wallmenius@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nils Wallménius [Sun, 10 Apr 2016 14:30:03 +0000 (16:30 +0200)]
drm/amd/powerplay: mark phm_master_table_* structs as const
Also adjust phm_construct_table to take a const pointer
Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Nils Wallménius <nils.wallmenius@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nils Wallménius [Sun, 10 Apr 2016 14:30:02 +0000 (16:30 +0200)]
drm/amd/powerplay: Mark pem_event_action chains as const
As these arrays were of pointer to pointer type, they were
pointer to pointer to const. Make them pointer to const
pointer to const.
Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Nils Wallménius <nils.wallmenius@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nils Wallménius [Mon, 2 May 2016 16:46:15 +0000 (12:46 -0400)]
drm/amdgpu: Mark all instances of struct drm_info_list as const
All these are compile time constand and the
drm_debugfs_create/remove_files functions take a const
pointer argument.
Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Nils Wallménius <nils.wallmenius@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nils Wallménius [Sun, 10 Apr 2016 14:30:00 +0000 (16:30 +0200)]
drm/amd/scheduler: Mark amdgpu_sched_ops const
This marks the struct amdgpu_sched_ops const and
adjusts amd_sched_init to take a const pointer
for the ops param. The ops member of
struct amd_gpu_scheduler is also changed to const.
Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Nils Wallménius <nils.wallmenius@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nils Wallménius [Sun, 10 Apr 2016 14:29:59 +0000 (16:29 +0200)]
drm/amd: Mark some tables as const
This patch marks some compile-time constant tables 'const'.
The tables marked in this patch are the low hanging fruit
where little other changes were necesary to avoid casting
away constness etc. Also mark some tables that are private
to a file as static.
Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Nils Wallménius <nils.wallmenius@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dave Airlie [Wed, 6 Apr 2016 20:50:25 +0000 (06:50 +1000)]
drm/radeon: add support for SET_APPEND_CNT packet3 (v2)
This adds support to the command parser for the set append counter
packet3, this is required to support atomic counters on
evergreen/cayman GPUs.
v2: fixup some of the hardcoded numbers with real register names
(Christian)
Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Arindam Nath <arindam.nath@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Arindam Nath <arindam.nath@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Wed, 9 Mar 2016 21:11:53 +0000 (22:11 +0100)]
drm/amdgpu: reuse VMIDs already assigned to a process
If we don't need to flush we can easily use another VMID
already assigned to the process.
Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Tue, 1 Mar 2016 15:46:18 +0000 (16:46 +0100)]
drm/amdgpu: add a fence after the VM flush
This way we can track when the flush is done.
Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Mon, 15 Feb 2016 11:33:02 +0000 (12:33 +0100)]
drm/amdgpu: use a sync object for VMID fences v2
v2: rebase & cleanup
This way we can store more than one fence as user for each VMID.
Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> (v1) Reviewed-by: Chunming Zhou <david1.zhou@amd.com> (v1) Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Tue, 8 Mar 2016 14:40:11 +0000 (15:40 +0100)]
drm/amdgpu: merge VM manager and VM context ID structure
No need to have two of them any more.
Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: Set PFLIP_SUBMITTED for crtc after address update
Also add some pflip debug prints.
This change allows us to wait on pflip status until the new surface address
is actually submitted to the register.
This reverts ed3020e923240829dcdfd3343f6e91dc02c63775
drm/amdgpu: Move MMIO flip out of spinlocked region
The original change assumed DAL will aquire locks inside DAL
implemetion of page_flip callback which eventaully didn't happen.
This moves the flip before status update which makes sense for the
non-DAL code pathes as well.
Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Michel Dänzer [Fri, 1 Apr 2016 09:51:34 +0000 (18:51 +0900)]
drm/radeon: Support DRM_MODE_PAGE_FLIP_ASYNC
When this flag is set, we program the hardware to execute the flip
during horizontal blank (i.e. for the next scanline) instead of during
vertical blank (i.e. for the next frame).
Currently this is only supported on ASICs which have a page flip
completion interrupt (>= R600), and only if the use_pflipirq parameter
has value 2 (the default).
Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Wed, 30 Mar 2016 12:42:57 +0000 (14:42 +0200)]
drm/amdgpu: optionally enable GART debugfs file
Keeping the pages array around can use a lot of system memory
when you want a large GART.
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Wed, 30 Mar 2016 08:54:16 +0000 (10:54 +0200)]
drm/amdgpu: remove GART page addr array
Not needed any more.
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Wed, 30 Mar 2016 08:50:25 +0000 (10:50 +0200)]
drm/amdgpu: use BO pages instead of GART array
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Fri, 18 Mar 2016 20:00:35 +0000 (21:00 +0100)]
drm/amdgpu: change parameter passing in the VM code
Make it more flexible by passing src and page addresses
directly instead of the structures they contain.
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Thu, 17 Mar 2016 15:25:15 +0000 (16:25 +0100)]
drm/amdgpu: drop the GTT power of two limit
As far as I can see that isn't neccessary any more.
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tom St Denis [Wed, 23 Mar 2016 17:17:04 +0000 (13:17 -0400)]
drm/amd/amdgpu: Enable clockgating in UVD6 for Stoney
This patch enables clockgating for the UVD6 block in Stoney.
Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tom St Denis [Wed, 23 Mar 2016 17:16:13 +0000 (13:16 -0400)]
drm/amd/amdgpu: Enable clockgating for UVD5 on Tonga
This patch enables clock gating for the UVD5 block with
Tonga.
Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tom St Denis [Wed, 23 Mar 2016 17:14:31 +0000 (13:14 -0400)]
drm/amd/amdgpu: Add SW clock gating support to UVD 5 and 6
This patch adds support for software clock gating to UVD 5
and UVD 6 blocks with a preliminary commented out hardware
gating routine.
Currently hardware gating does not work so it's not activated.
Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nicolai Stange [Tue, 22 Mar 2016 21:05:27 +0000 (22:05 +0100)]
drm/radeon: don't include RADEON_HPD_NONE in HPD IRQ enable bitsets
The values of all but the RADEON_HPD_NONE members of the radeon_hpd_id
enum transform 1:1 into bit positions within the 'enabled' bitset as
assembled by evergreen_hpd_init():
enabled |= 1 << radeon_connector->hpd.hpd;
However, if ->hpd.hpd happens to equal RADEON_HPD_NONE == 0xff, UBSAN
reports
UBSAN: Undefined behaviour in drivers/gpu/drm/radeon/evergreen.c:1867:16
shift exponent 255 is too large for 32-bit type 'int'
[...]
Call Trace:
[<ffffffff818c4d35>] dump_stack+0xbc/0x117
[<ffffffff818c4c79>] ? _atomic_dec_and_lock+0x169/0x169
[<ffffffff819411bb>] ubsan_epilogue+0xd/0x4e
[<ffffffff81941cbc>] __ubsan_handle_shift_out_of_bounds+0x1fb/0x254
[<ffffffffa0ba7f2e>] ? atom_execute_table+0x3e/0x50 [radeon]
[<ffffffff81941ac1>] ? __ubsan_handle_load_invalid_value+0x158/0x158
[<ffffffffa0b87700>] ? radeon_get_pll_use_mask+0x130/0x130 [radeon]
[<ffffffff81219930>] ? wake_up_klogd_work_func+0x60/0x60
[<ffffffff8121a35e>] ? vprintk_default+0x3e/0x60
[<ffffffffa0c603c4>] evergreen_hpd_init+0x274/0x2d0 [radeon]
[<ffffffffa0c603c4>] ? evergreen_hpd_init+0x274/0x2d0 [radeon]
[<ffffffffa0bd196e>] radeon_modeset_init+0x8ce/0x18d0 [radeon]
[<ffffffffa0b71d86>] radeon_driver_load_kms+0x186/0x350 [radeon]
[<ffffffffa03b6b16>] drm_dev_register+0xc6/0x100 [drm]
[<ffffffffa03bc8c4>] drm_get_pci_dev+0xe4/0x490 [drm]
[<ffffffff814b83f0>] ? kfree+0x220/0x370
[<ffffffffa0b687c2>] radeon_pci_probe+0x112/0x140 [radeon]
[...]
=====================================================================
radeon 0000:01:00.0: No connectors reported connected with modes
At least on x86, there should be no user-visible impact as there
1 << 0xff == 1 << (0xff & 31) == 1 << 31
holds and 31 > RADEON_MAX_HPD_PINS. Thus, this patch is a cosmetic one.
All of the above applies analogously to evergreen_hpd_fini(),
r100_hpd_init(), r100_hpd_fini(), r600_hpd_init(), r600_hpd_fini(),
rs600_hpd_init() and rs600_hpd_fini()
Silence UBSAN by checking ->hpd.hpd for RADEON_HPD_NONE before oring it
into the 'enabled' bitset in the *_init()- or the 'disabled' bitset in
the *_fini()-functions respectively.
Signed-off-by: Nicolai Stange <nicstange@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Wed, 16 Mar 2016 07:17:18 +0000 (15:17 +0800)]
drm/amdgpu: refine code for code style.
White space fix.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Wed, 16 Mar 2016 06:48:18 +0000 (14:48 +0800)]
drm/amdgpu: No need to stop hw init although vce's state was not true.
This is not a fatal error.
v2: add comment why ignore the error here.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Wed, 16 Mar 2016 06:45:40 +0000 (14:45 +0800)]
drm/amdgpu: fix issue that can't set vce clock gate.
Need to soft reset VCE as part of the clockgating
sequence.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Monk Liu [Thu, 10 Mar 2016 04:14:44 +0000 (12:14 +0800)]
drm/amdgpu: use ref to keep job alive
this is to fix fatal page fault error that occured if:
job is signaled/released after its timeout work is already
put to the global queue (in this case the cancel_delayed_work
will return false), which will lead to NX-protection error
page fault during job_timeout_func.
Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Monk Liu [Thu, 3 Mar 2016 11:00:50 +0000 (19:00 +0800)]
drm/amdgpu: delay job free to when it's finished (v2)
for those jobs submitted through scheduler, do not
free it immediately after scheduled, instead free it
in global workqueue by its sched fence signaling
callback function.
v2:
call uf's bo_undef after job_run()
call job's sync free after job_run()
no static inline __amdgpu_job_free() anymore, just use
kfree(job) to replace it.
Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Monk Liu [Thu, 14 Jan 2016 11:07:38 +0000 (19:07 +0800)]
drm/amdgpu: patch cond exec for SDMA
More ground work for conditional execution on SDMA
necessary for preemption.
Signed-off-by: Monk Liu <monk.liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Monk Liu [Thu, 14 Jan 2016 10:08:16 +0000 (18:08 +0800)]
drm/amdgpu: support cond exec
This adds the groundwork for conditional execution on
SDMA which is necessary for preemption.
Signed-off-by: Monk Liu <monk.liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jérome Glisse [Fri, 18 Mar 2016 15:58:39 +0000 (16:58 +0100)]
drm/radeon: hard reset r600 and newer GPU when hibernating.
Some GPU block like UVD and VCE require hard reset to be properly
resume if there is no real powerdown of the asic like during various
hibernation step. This patch perform such hard reset.
Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Jérôme Glisse <jglisse@redhat.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jérome Glisse [Fri, 18 Mar 2016 15:58:38 +0000 (16:58 +0100)]
drm/radeon: allow to force hard GPU reset.
In some cases, like when freezing for hibernation, we need to be
able to force hard reset even if no engine are stuck. This patch
add a bool option to current asic reset callback to allow to force
hard reset on asic that supports it.
Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Jérôme Glisse <jglisse@redhat.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jérome Glisse [Fri, 18 Mar 2016 15:58:37 +0000 (16:58 +0100)]
drm/radeon: add driver option to disable vce block.
Quite few suspend/hibernation bugs are related to this block. Add
an option to disable those as a work around.
Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Jérôme Glisse <jglisse@redhat.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jérome Glisse [Fri, 18 Mar 2016 15:58:36 +0000 (16:58 +0100)]
drm/radeon: add driver option to disable uvd block.
Quite few suspend/hibernation bugs are related to this block. Add
an option to disable those as a work around.
Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Jérôme Glisse <jglisse@redhat.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jérome Glisse [Fri, 18 Mar 2016 15:58:35 +0000 (16:58 +0100)]
drm/radeon: consolidate cik vce initialization and startup code.
This match the exact same control flow as existing code. It just
use goto instead of multiple levels of if/else. It also clarify
early initialization failures by clearing rdev->has_vce doing so
does not change end result from hardware point of view, it only
avoids printing more error messages down the line and thus only
the original error is reported.
Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Jérôme Glisse <jglisse@redhat.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jérome Glisse [Fri, 18 Mar 2016 15:58:34 +0000 (16:58 +0100)]
drm/radeon: consolidate si vce initialization and startup code.
This match the exact same control flow as existing code. It just
use goto instead of multiple levels of if/else. It also clarify
early initialization failures by clearing rdev->has_vce doing so
does not change end result from hardware point of view, it only
avoids printing more error messages down the line and thus only
the original error is reported.
Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Jérôme Glisse <jglisse@redhat.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jérome Glisse [Fri, 18 Mar 2016 15:58:33 +0000 (16:58 +0100)]
drm/radeon: consolidate ni vce initialization and startup code.
This match the exact same control flow as existing code. It just
use goto instead of multiple levels of if/else. It also clarify
early initialization failures by clearing rdev->has_vce doing so
does not change end result from hardware point of view, it only
avoids printing more error messages down the line and thus only
the original error is reported.
Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Jérôme Glisse <jglisse@redhat.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jérome Glisse [Fri, 18 Mar 2016 15:58:32 +0000 (16:58 +0100)]
drm/radeon: add a vce flag to know if need to initialize vce or not.
This will later on serve for module option to disable vce.
Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Jérôme Glisse <jglisse@redhat.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jérome Glisse [Fri, 18 Mar 2016 15:58:31 +0000 (16:58 +0100)]
drm/radeon: consolidate cik uvd initialization and startup code.
This match the exact same control flow as existing code. It just
use goto instead of multiple levels of if/else. It also clarify
early initialization failures by clearing rdev->has_uvd doing so
does not change end result from hardware point of view, it only
avoids printing more error messages down the line and thus only
the original error is reported.
Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Jérôme Glisse <jglisse@redhat.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jérome Glisse [Fri, 18 Mar 2016 15:58:30 +0000 (16:58 +0100)]
drm/radeon: consolidate si uvd initialization and startup code.
This match the exact same control flow as existing code. It just
use goto instead of multiple levels of if/else. It also clarify
early initialization failures by clearing rdev->has_uvd doing so
does not change end result from hardware point of view, it only
avoids printing more error messages down the line and thus only
the original error is reported.
Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Jérôme Glisse <jglisse@redhat.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jérome Glisse [Fri, 18 Mar 2016 15:58:29 +0000 (16:58 +0100)]
drm/radeon: consolidate ni uvd initialization and startup code.
This match the exact same control flow as existing code. It just
use goto instead of multiple levels of if/else. It also clarify
early initialization failures by clearing rdev->has_uvd doing so
does not change end result from hardware point of view, it only
avoids printing more error messages down the line and thus only
the original error is reported.
Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Jérôme Glisse <jglisse@redhat.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jérome Glisse [Fri, 18 Mar 2016 15:58:28 +0000 (16:58 +0100)]
drm/radeon: consolidate evergreen uvd initialization and startup code.
This match the exact same control flow as existing code. It just
use goto instead of multiple levels of if/else. It also clarify
early initialization failures by clearing rdev->has_uvd doing so
does not change end result from hardware point of view, it only
avoids printing more error messages down the line and thus only
the original error is reported.
Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Jérôme Glisse <jglisse@redhat.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jérome Glisse [Fri, 18 Mar 2016 15:58:27 +0000 (16:58 +0100)]
drm/radeon: consolidate rv770 uvd initialization and startup code.
This match the exact same control flow as existing code. It just
use goto instead of multiple levels of if/else. It also clarify
early initialization failures by clearing rdev->has_uvd doing so
does not change end result from hardware point of view, it only
avoids printing more error messages down the line and thus only
the original error is reported.
Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Jérôme Glisse <jglisse@redhat.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jérome Glisse [Fri, 18 Mar 2016 15:58:26 +0000 (16:58 +0100)]
drm/radeon: consolidate r600 uvd initialization and startup code.
This match the exact same control flow as existing code. It just
use goto instead of multiple levels of if/else. It also clarify
early initialization failures by clearing rdev->has_uvd doing so
does not change end result from hardware point of view, it only
avoids printing more error messages down the line and thus only
the original error is reported.
Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Jérôme Glisse <jglisse@redhat.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dave Airlie [Fri, 29 Apr 2016 04:57:51 +0000 (14:57 +1000)]
Merge branch 'for-next' of http://git.agner.ch/git/linux-drm-fsl-dcu into drm-next
This adds very rudimentary TCON (timing controller for raw LCD displays)
support to enable the bypass mode in order to use the DCU controller on
Freescale/NXP Vybrid SoC's.
Additionally the register clock and pixel clock has been separated, but
are currently still enabled and disabled pairwise.
Other than that, fixes and cleanups accross the driver.
* 'for-next' of http://git.agner.ch/git/linux-drm-fsl-dcu:
drm/fsl-dcu: increment version and date
drm/fsl-dcu: implement lastclose callback
drm/fsl-dcu: disable output polling on driver unload
drm/fsl-dcu: deallocate fbdev CMA on unload
drm/fsl-dcu: use variable name dev for struct drm_device
drm/fsl-dcu: handle missing panel gracefully
drm/fsl-dcu: detach panel on destroy
drm/layerscape: reduce excessive stack usage
drm/fsl-dcu: add TCON driver
drm/fsl-dcu: use common clock framework for pixel clock divider
drm/fsl-dcu: add extra clock for pixel clock
drm/fsl-dcu: disable clock on initialization failure and remove
Dave Airlie [Fri, 29 Apr 2016 04:52:41 +0000 (14:52 +1000)]
Merge tag 'sun4i-drm-for-4.7' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into drm-next
Allwinner DRM driver for 4.7
This pull request introduces the sun4i driver, meant to be used on the
older Allwinner SoCs (A10, A13, A20, A23, A31 and A33).
It currently supports only the A13, which has one of the simplest video
pipeline. Support for other video components and SoCs will be added
eventually.
It supports only a RGB or composite output. It doesn't do HDMI, VGA, LVDS
or power management yet, but that will come in time as well.
* tag 'sun4i-drm-for-4.7' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux:
MAINTAINERS: Add a maintainer for the Allwinner DRM driver
drm: sun4i: tv: Add NTSC output standard
drm: sun4i: tv: Add PAL output standard
drm: sun4i: Add composite output
drm: sun4i: Add RGB output
drm: Add Allwinner A10 Display Engine support
drm: sun4i: Add DT bindings documentation
drm: fb: Add seq_file definition
Maxime Ripard [Thu, 29 Oct 2015 08:39:01 +0000 (09:39 +0100)]
drm: sun4i: Add composite output
Some Allwinner SoCs have an IP called the TV encoder that is used to output
composite and VGA signals. In such a case, we need to use the second TCON
channel.
Add support for that TV encoder.
Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Maxime Ripard [Thu, 29 Oct 2015 08:37:32 +0000 (09:37 +0100)]
drm: sun4i: Add RGB output
One of the A10 display pipeline possible output is an RGB interface to
drive LCD panels directly. This is done through the first channel of the
TCON that will output our video signals directly.
Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Maxime Ripard [Thu, 29 Oct 2015 08:36:23 +0000 (09:36 +0100)]
drm: Add Allwinner A10 Display Engine support
The Allwinner A10 and subsequent SoCs share the same display pipeline, with
variations in the number of controllers (1 or 2), or the presence or not of
some output (HDMI, TV, VGA) or not.
Add a driver with a limited set of features for now, and we will hopefully
support all of them eventually
Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Daniel Vetter [Fri, 22 Apr 2016 20:10:30 +0000 (22:10 +0200)]
drm: Switch blobs to the new generic modeset obj refcounting
Need to move the free function around a bit, but otherwise mostly
just removing code.
Specifically we can nuke all the _locked variants since the weak idr
reference is now protected by the idr_mutex, which we never hold
anywhere expect in the lookup/reg/unreg functions. And those never
call anything else.
Another benefit of this is that this patch switches the weak reference
logic from kref_put_mutex to kref_get_unless_zero. And the later is in
general more flexible wrt accomodating multiple weak references
protected by different locks, which might or might not come handy
eventually.
But one consequence of that switch is that we need to acquire the
blob_lock from the free function for the list_del calls. That's a bit
tricky to pull off, but works well if we pick the exact same scheme as
is already used for framebuffers. Most important changes:
- filp list is maintainer by create/destroy_blob ioctls directly
(already the case, so we can just remove the redundant list_del from
the free function).
- filp close handler walks the filp-private list lockless - works
because we know no one else can access it. I copied the same comment
from the fb code over to explain this.
- Otherwise we need to sufficiently restrict blob_lock critical
sections to avoid all the unreference calls. Easy to do once the
blob_lock only protects the list, and no longer the weak reference.
Cc: Dave Airlie <airlied@gmail.com> Cc: Daniel Stone <daniels@collabora.com> Signed-off-by: Daniel Vetter <daniel.vetter@intel.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Daniel Vetter [Fri, 22 Apr 2016 20:10:28 +0000 (22:10 +0200)]
drm: Fix fb leaks and WARN spew in get/set_prop ioctls
Dave Airlie had at least the refcount leak fixed in a later patch (but
that patch does other things which need a bit more work). But we still
have the trouble that silly userspace could hit the WARN_ON in
drm_mode_object_find.
Fix this all up to make sure we don't leak objects, and don't spew
into demsg.
Fixes: d0f37cf62979 ("drm/mode: move framebuffer reference into object.")
Testcase: igt/kms_addfb_basic/invalid-*-prop* Cc: Dave Airlie <airlied@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@intel.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Daniel Vetter [Fri, 22 Apr 2016 20:10:27 +0000 (22:10 +0200)]
drm: Improve kerneldoc for new mode object refcounting
Slipped through the cracks in my review. The one issue I spotted
is that drm_mode_object_find now acquires references and can be
used on FB objects, which caused follow-on bugs in get/set_prop ioctls.
Follow-up patches will fix that.
[airlied: fixup some incr fb/decr object mixups]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Dave Airlie <airlied@redhat.com>
Carlos Palminha [Fri, 19 Feb 2016 12:30:26 +0000 (15:30 +0300)]
drm: Add support of ARC PGU display controller
ARC PGU could be found on some development boards from Synopsys.
This is a simple byte streamer that reads data from a framebuffer
and sends data to the single encoder.
Signed-off-by: Carlos Palminha <palminha@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: David Airlie <airlied@linux.ie> Cc: dri-devel@lists.freedesktop.org Cc: linux-snps-arc@lists.infradead.org
Stefan Agner [Sun, 17 Apr 2016 05:02:49 +0000 (22:02 -0700)]
drm/fsl-dcu: deallocate fbdev CMA on unload
Free fbdev CMA using drm_fbdev_cma_fini on unload. This fixes
a warning when unloading the driver:
WARNING: CPU: 0 PID: 164 at drivers/gpu/drm/drm_crtc.c:5930 drm_mode_config_cleanup+0x204/0x208
Stefan Agner [Wed, 13 Apr 2016 07:14:18 +0000 (00:14 -0700)]
drm/fsl-dcu: use variable name dev for struct drm_device
The driver uses different variable names for struct drm_device
across functions which is confusing. Stick to the more common
variable name dev. While at it, remove unnecessary if statement
in error handling.
Stefan Agner [Thu, 3 Dec 2015 02:03:50 +0000 (18:03 -0800)]
drm/fsl-dcu: handle missing panel gracefully
If the device tree property fsl,panel is missing, drm_panel_attach
is called with a NULL pointer as first argument. Having a panel is
basically mandatory since RGB is the only supported connector.
Check if a panel node has been found, return -ENODEV and cleanup
otherwise.
Arnd Bergmann [Mon, 22 Feb 2016 21:33:31 +0000 (22:33 +0100)]
drm/layerscape: reduce excessive stack usage
The fsl-dcu driver copies a drm_mode_config object to its
stack but then only accesses a single member (dpms_property)
once. The data structure is large enough to trigger a warning
about the amount of kernel stack being used:
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c: In function 'fsl_dcu_drm_connector_create':
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c:182:1: error: the frame size of 1040 bytes is larger than 1024 bytes [-Werror=frame-larger-than=]
This changes the fsl_dcu_drm_connector_create() function to
only access the drm_mode_config by reference, which is also
more efficient.
Stefan Agner [Wed, 2 Dec 2015 22:39:40 +0000 (14:39 -0800)]
drm/fsl-dcu: add TCON driver
Add driver for the TCON (timing controller) module. The TCON module
is a separate module attached after the DCU (display controller
unit). Each DCU instance has its own, directly connected TCON
instance. The DCU's RGB and timing signals are passing through
the TCON module. TCON can provide timing signals for raw TFT panels
or operate in a bypass mode which leaves all signals unaltered.
The driver currently only supports the bypass mode.
Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stefan Agner <stefan@agner.ch>
Stefan Agner [Wed, 23 Mar 2016 01:06:08 +0000 (18:06 -0700)]
drm/fsl-dcu: use common clock framework for pixel clock divider
Use the common clock framework to calculate the pixel clock
dividier. The previous implementation rounded down the calculated
factor. Thanks to the CLK_DIVIDER_ROUND_CLOSEST flag using the
common clock framework divider implementation improves the pixel
clock accuracy in some cases. Ontop of that it also allows to see
the actual pixel clock in the sysfs clock summary.
Stefan Agner [Tue, 22 Mar 2016 22:45:29 +0000 (15:45 -0700)]
drm/fsl-dcu: add extra clock for pixel clock
The Vybrid DCU variant has two independent clock inputs, one
for the registers (IPG bus clock) and one for the pixel clock.
Support this distinction in the DCU DRM driver while staying
backward compatible for old device trees.
Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stefan Agner <stefan@agner.ch>
Simon Horman [Fri, 25 Mar 2016 01:38:28 +0000 (10:38 +0900)]
drm: rcar-du: Use ARCH_RENESAS
Make use of ARCH_RENESAS in place of ARCH_SHMOBILE.
This is part of an ongoing process to migrate from ARCH_SHMOBILE to
ARCH_RENESAS the motivation for which being that RENESAS seems to be a more
appropriate name than SHMOBILE for the majority of Renesas ARM based SoCs.
Arnd Bergmann [Fri, 26 Feb 2016 11:52:20 +0000 (12:52 +0100)]
drm: rcar-du: Clarify vsp dependency
The VSP1 compositor code in DRM links against the respective V4L
driver, but the dependency is not expressed correctly in Kconfig,
which leads to a build error when the DRM driver is built-in
and the V4L driver is a module:
drivers/gpu/built-in.o: In function `rcar_du_vsp_plane_atomic_update':
rcar-du/rcar_du_vsp.c:183: undefined reference to `vsp1_du_atomic_update'
This patch avoids the problem by ensuring that the DRM VSP code can
only be enabled if the V4L driver is linked into the kernel, or
both are loadable modules.
Signed-off-by: Arnd Bergmann <arnd@arndb.de> Fixes: 6d62ef3ac30b ("drm: rcar-du: Expose the VSP1 compositor through KMS planes") Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
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