Anson Huang [Wed, 23 May 2012 01:38:29 +0000 (09:38 +0800)]
ENGR00174974 [MX6]Fix CPU hotplug platform related issue
We need to turn of cache coherency of secondary core before
it is disable by core0, otherwise, the secondary core may be
waked by cache sync, and if it exit from wfi and access BUS,
meanwhile, core0 disable it from hardware, the whole SOC would
hang.
Robby Cai [Tue, 22 May 2012 08:55:18 +0000 (16:55 +0800)]
ENGR00210360 - EPDC: Fix regulator-related EPDC failure on MX6SL ARM2 CPU board
Its similar to ENGR00178581.
Remove call to regulator_has_full_constraints() from Max17135 EPD PMIC
initialization code, since leaving it enabled results in a failure of
system to load properly - key regulators are disabled when 'epdc' is added
to the kernel command line.
Fugang Duan [Sat, 19 May 2012 03:17:03 +0000 (11:17 +0800)]
ENGR00210075-3 - SPDC: Add Sipix driver
Add Sipix driver for electronic paper dispaly
- Support RGB565 & Y4 formats with 800x600 resolution
- Support synchronization update by waiting the last
request update completed.
- Support automated update using Linux deferred io mechanism
- Support for panning(y-direction)
- Support rotation with 90,180,and 270 degree.
- Initial integration with ePXP, output Y4 format
- Support specific waveform modes update.
- Support Snapshot, Queue and Queue Merge update sheeme.
- Support full and partial EPD screen updates.
mode_1 & mode_2: partial update
mode_0 & mode_3: full update
- Align waveform mode with EPDC as below:
mode_init = mode_0;
mode_gc4 = mode_2;
mode_A2 = mode_4, mode_du =mode_4;
mode_gc8 = mode_1, mode_gc16 = mode_1, mode_gc32 = mode_1;
Ryan QIAN [Mon, 21 May 2012 09:24:42 +0000 (17:24 +0800)]
ENGR00210160: [mx6]: mmc/sd illegal func call "clk_enable" in intr context
issue:
calling clk_enable in an interrupt context which will cause kernel bug.
- It is a temp workaround for calling 'clk_enable' in an interrupt context.
By redefine SDHCI_USE_LEDS_CLASS to SDHCI_USE_LEDS_CLASS_BROKEN to exclude
led ctrl support, it does not support mmc/sd LED ctrl with this patch.
- Per current driver structure, it's difficult to fix this issue in driver
layer. The fix for this issue needs adjustment to current driver structure
and using new clock management in kernel interface.
Wu Guoxing [Mon, 21 May 2012 01:24:29 +0000 (09:24 +0800)]
ENGR00209062-2: mx6dq and mx6dl dual camera support
dual camera support for mx6q and mx6dl:
1. let mipi and parallel camera working on different csi
2. the two camera can work independently and synchronously
3. the two camera will be registered and different video
device(/dev/video0, /dev/video1)
4. when both camera are working, the can not use the same
ipu channel, that is, when camera one using PRP_ENC_MEM
or PRP_VF_MEM channel, the other one can only use CSI_MEM
Wu Guoxing [Mon, 21 May 2012 01:21:12 +0000 (09:21 +0800)]
ENGR00209062-1: mx6dq and mx6dl dual camera support
dual camera support for mx6q and mx6dl:
1. let mipi and parallel camera working on different csi
2. the two camera can work independently and synchronously
3. the two camera will be registered and different video
device(/dev/video0, /dev/video1)
4. when both camera are working, the can not use the same
ipu channel, that is, when camera one using PRP_ENC_MEM
or PRP_VF_MEM channel, the other one can only use CSI_MEM
DLL ON/OFF code randomly hangs waiting for the CON_ACK bit
to be set when a CON_REQ is asserted.
Fix this by adding a delay after the MMDC automatic power savings
mode is disabled.
To avoid the ARM from accepting an interrupt in the dangerous
window, reduce the ARM core freq just before the sytem is
about to enter WAIT state.
Reduce the ARM freq so as to maintain 12:5 ARM_CLK to IPG
ratio. Use the ARM_PODF to drop the frequency.
In a multicore case the frequency is dropped only when all the
4 cores are going to be in WFI.
In case of single core environment, its easy to drop the ARM core
freq just before WFI since there is no need to identify the state of
the other cores.
Some other points to note:
1. If "mem_clk_on" is added to the command line, the memory clocks will
not be gated in WAIT mode. This will increase the system IDLE power.
This mode is valid only on MX6sl, MX6DQ TO1.2 and MX6DL TO1.1.
2. In case the IPG clk is too low (for ex 50MHz) and ARM is at 1GHz,
we cannot match the 12:5 ratio using ARM_PODF only. In this case,
donot clock gate the memories in WAIT mode (available on MX6SL,
MXDQ TO1.2 and MXDL TO1.1). For MXDQ TO1.1 and MX6DL TO1.0, disable
system wide WAIT entry in this case.
In STOP mode, always ensure that the memory clocks are gated, else
power impact will be significant.
Danny Nold [Thu, 17 May 2012 20:17:37 +0000 (15:17 -0500)]
ENGR00209883-1 - EPDC fb: Add support for MX 6SoloLite ARM2 board
- Add EPDC and Max17135 structures and initialization calls to
the MX6SL ARM2 board file
- Add IOMUX configuration defines and GPIO defines for EPDC/Max17135
- Remove prints/debug from EPDC-related clocks.
Signed-off-by: Danny Nold <dannynold@freescale.com>
B38613 [Fri, 18 May 2012 10:15:56 +0000 (18:15 +0800)]
ENGR00209686-2:sdio:suspend/resume issue
1.add MMC_PM_WAKE_SDIO_IRQ capability, it should be
used together with MMC_PM_KEEP_POWER although not support
SDIO wakeup in function.
2.add MMC_CAP_NONREMOVABLE to describe imx6's three sdhc
devices's removable feature.Now emmc is permanent,sdio and
sd is removable instead of all default were permanent before.
According to this feature, detimine whether reinit card
or not in resume.
B38613 [Fri, 18 May 2012 10:14:56 +0000 (18:14 +0800)]
ENGR00209686-1:sdio:suspend/resume issue
1.add MMC_PM_WAKE_SDIO_IRQ capability, it should be
used together with MMC_PM_KEEP_POWER although not support
SDIO wakeup in function.
2.add MMC_CAP_NONREMOVABLE to describe imx6's three sdhc
devices's removable feature.Now emmc is permanent,sdio and
sd is removable instead of all default were permanent before.
According to this feature, detimine whether reinit card
or not in resume.
Sandor Yu [Thu, 17 May 2012 07:28:54 +0000 (15:28 +0800)]
ENGR00182769 HDMI: No sound when playing audio in 480p mode
It is cause by HDMI audio driver can't get right pixel clock
from IPU driver if pixel clock source from HSP clock not from
DI clock.
HDMI driver get pixel clock by call clk_get_rate() function,
but the function return actually clock, in some videomode the
actually pixel clock is not right equal the pixel clock in CEA spec.
Get pixel clock from video mode struct instead of CCM register.
480P HDMI audio can work.
Adrian Alonso [Wed, 16 May 2012 22:34:24 +0000 (17:34 -0500)]
ENGR00209384-4 mxc_spdif: disable sym_err isr
* Disable symbol error interrupt when rx dpll is unlocked
This means that no spdif Rx data had been identified and
driver will keep issuing sym_err interrupt request.
* Add check to only execute capture_start/stop
functions if rx_active is set.
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Robin Gong [Thu, 17 May 2012 06:19:01 +0000 (14:19 +0800)]
ENGR00209633-2 I2C mx6sl pfuze: add pfuze board support for mx6sl arm2
1.add pmic board support file
2.add i2c support on board-mx6sl_arm2.c
3.update IOMUX setting for I2C pin for mx6sl arm2 board Signed-off-by: Robin Gong <B38343@freescale.com>
ENGR00209620 MX6-Disable PU Brown out detection in low power mode.
Ensure that the brown out detection of the PU regulator is
disabled before the regulator itself is disabled.
Keeping the detection enabled will generate an interrupt that
is not currently being handled in the BSP when the regulator is
disabled since its voltage is dropped to 0V. This will prevent
the system from entering complete WAIT state thus increasing the
power in the low power idle/audio usecase.
Adrian Alonso [Mon, 14 May 2012 23:50:53 +0000 (18:50 -0500)]
ENGR00209384-2 mxc_spdif: capture playback start function
* Add start capture/playback function
Start sequence for capturing/playing audio data.
* Remove caprure/playback prepere function hwd initialization
handled by trigger function when user/app starts capture/play
process.
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Adrian Alonso [Mon, 14 May 2012 23:43:37 +0000 (18:43 -0500)]
SAUCE remove unnecessary suspend/resume functions
BugLink: http://bugs.launchpad.net/bugs/882723
Disabling/re-enabling clocks is not necessary as it's done in *_startup()
and *_shutdown() functions, and shall be performed during suspend/resume.
This is causing warnings of un-matched clk_enable()/clk_disable()
Rework patch for imx_3.0.15 code base
Signed-off-by: Eric Miao <eric.miao@linaro.org> Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Fugang Duan [Wed, 16 May 2012 09:57:53 +0000 (17:57 +0800)]
ENGR00209520-03 - FEC : Add support for MX6SL MSL.
- Modify the the platform macro define like as cpu_is_xxx()
for supporting Mergrez chip.
- Config MIIGSK for FEC IP to enable RMII mode. MX25,MX53,
and MX6Sololite use FEC IP, which need to config the MIIGSK
registers memory map for RMII and MII.
- Correct device id_table entry name for differnt IP.
- Rewrite FEC MAC address by net_device address when reset FEC,
which can avoid invalid MAC address to result in FEC cannot
work.
Fugang Duan [Wed, 16 May 2012 10:27:09 +0000 (18:27 +0800)]
ENGR00209520-01 - MX6SL MSL : Add FEC support
Add FEC support for mx6-sololite:
- Add FEC pad iomux setting.
- Power on phy and init fec.
- Add devname to distinguish different IP.
- Use ANATOP as FEC clock source in default, remove redundant
config "FEC_CLOCK_FROM_ANATOP".
Wayne Zou [Wed, 16 May 2012 07:43:12 +0000 (15:43 +0800)]
ENGR00169375 IPU: Remove the warning message when doing 8:1 downsize
Remove Overflow message on resize coeff when resize from 1280*720 to 160*120
The IPU IC can not do exactly 8:1 downsize, but can be very close to 8:1
downsize.
Xinyu Chen [Tue, 15 May 2012 09:16:33 +0000 (17:16 +0800)]
ENGR00182786 mx6q sabresd: Add power/reset function for 3G modem
Add PCIE 3V3 power up/down routing if we do not have
pcie driver selected. And power up 3V3 in board init.
As the reset function of the hw board cannot reset the
modem power. So on kernel boot up, we must make sure
the 3g modem is reset correctly by gpio reset.
Jason Liu [Mon, 14 May 2012 13:41:05 +0000 (21:41 +0800)]
ENGR00182324-4 - MX6SL MSL: Enable L2 cache as OCRAM functionality
L2 cache can be configured to serve as OCRAM. This patch adds
code to check this configuration, and reset it to L2 cache function
before enabling the L2 cache.
Jason Liu [Mon, 14 May 2012 13:15:57 +0000 (21:15 +0800)]
ENGR00182324-3 - MX6SL MSL: Add clock support for i.MX 6SoloLite
Add clock support for i.MX 6SoloLite. A new clock file has been created
to reflect the substantial set of changes in the clocks used between
6SoloLite and other 6 series SoCs.
Signed-off-by: Jason Liu <r64343@freescale.com> Signed-off-by: Robby Cai <r63905@freescale.com>
Adrian Alonso [Mon, 14 May 2012 23:02:35 +0000 (18:02 -0500)]
ENGR00178459 mxc_spdif: fix read access for debug info
* Fix read register access for debug info
* Read from spdif registers with a disabled
spdif core clock leads to kernel hang.
* Avoid it by enabling/diabling core clk.
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Adrian Alonso [Fri, 11 May 2012 17:17:44 +0000 (12:17 -0500)]
ENGR00178459 mxc_spdif: clk_enable return checks
* Add clk_enable return checks, if clocks aren't enabled
writting/reading from spdif register will cause
system to become unresponsive.
* Remove spdif_audio_clk enable/disable calls
this clock is not assigned and is reposible for making
the system unresposive.
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Zhang Jiejing [Mon, 14 May 2012 06:22:11 +0000 (14:22 +0800)]
ENGR00209059-1 MX6: reboot: add reboot to special function
add reboot to special function like mfg download mode,
android fastboot, recovery mode.
It use ASRC register to enter mfgtool download mode and other function.
For android fastboot, recovery function it use ASRC_GPR10 bit 7-8 bit,
it will checked in uboot and clear after read.
Add this feature to improve recovery function, to avoid infinit looping
enter recovery mode if some thing goes wrong in fastboot mode.
Also add convient function for developer.
Xinyu Chen [Wed, 7 Mar 2012 02:17:21 +0000 (10:17 +0800)]
ENGR00176278 mx6: make local timer work with WAIT mode
As mx6q soc use one clock to provide for cpu and local timer,
the local timers will be stopped when enter wait mode.
This causes system hang when enter wait mode with local timer
enabled. So we should switch the clock event to GPT
broadcast clock event before entering wait mode, and disable
local timers. Todo this, following changes made:
* In arch_idle(), we check if the GPT broadcast clock
event is switched to one shot mode. If the kernel clocksource
is switched from jiffies one to GPT, then we can use GPT
as broadcast event. And switch from local timer to GPT broadcast
event before entering mx6q_wait. Otherwise, kernel will hange
if the SW jiffies clock source is used.
We call clockevents_notify to switch clock source.
* Remove the enable_wait_mode check in local timer setup.
* Always return 0 in GPT v2 timer's set_next_event routing.
All the GPTs are running in free run mode as what driver did.
So we should allow the GPT CNT register roll over to 0 when it
reaches 0xFFFFFFFF. And the next event written to compare register
can less than the current value in CNT.
If we refused to do roll over settings, the kernel will continues
to set_next_event to GPT when the next event is far away and
we return negative value. This is happend when one CPU is in idle
and no timewheel is being expired in short time.
Loren Huang [Fri, 11 May 2012 02:20:56 +0000 (10:20 +0800)]
ENGR00209022 Update gpu clock management code
-This patch from vivante.They need to bypass the
reference count in clock management code as they
may touch clock while they just want to change
power state.
Huang Shijie [Wed, 9 May 2012 06:00:57 +0000 (14:00 +0800)]
ENGR00182346-2 serial: unregister the console when the console is released
The old code does not unregister the console mxc_early_uart_console when
it is disabled. This may causes the global console `console_drivers` still
pointes an invalid console mxc_early_uart_console. A hung will be observed
in this situation.
These methods are invoked if the iMX uart is used in conjuction with kgdb during
early boot. In order to access the UART without the interrupts, the kernel uses
the basic polling methods for IO with the device. With these methods
implemented, it is now possible to enable kgdb during early boot over serial.
Now the purpose of cpu_active is mostly with bringing down a cpu, where
we mark it !active to avoid the load-balancer from moving tasks to it
while we tear down the cpu. This is required because we only update the
sched_domain tree after we brought the cpu-down. And this is needed so
that some tasks can still run while we bring it down, we just don't want
new tasks to appear.
On cpu-up however the sched_domain tree doesn't yet include the new cpu,
so its invisible to the load-balancer, regardless of the active state.
So instead of setting the active state after we boot the new cpu (and
consequently having to wait for it before enabling interrupts) set the
cpu active before we set it online and avoid the whole mess.
Reported-by: Stepan Moskovchenko <stepanm@codeaurora.org> Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Acked-by: Thomas Gleixner <tglx@linutronix.de> Link: http://lkml.kernel.org/r/1323965362.18942.71.camel@twins Signed-off-by: Ingo Molnar <mingo@elte.hu>
Russell King [Thu, 19 Jan 2012 15:20:58 +0000 (15:20 +0000)]
ARM: fix rcu stalls on SMP platforms
We can stall RCU processing on SMP platforms if a CPU sits in its idle
loop for a long time. This happens because we don't call irq_enter()
and irq_exit() around generic_smp_call_function_interrupt() and
friends. Add the necessary calls, and remove the one from within
ipi_timer(), so that they're all in a common place.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Thomas Gleixner [Sat, 15 Oct 2011 00:22:43 +0000 (17:22 -0700)]
ARM: smpboot: Enable irqs on secondary CPU after marking it online/active
Patch is the last version from tglx on Oct 7.
Discussion is at: http://comments.gmane.org/gmane.linux.ports.arm.kernel/131919
The original commit message for the first patch version:
Frank Rowand reported:
I have a consistent (every boot) hang on boot with the RT patches.
With a few hacks to get console output, I get:
rcu_preempt_state detected stalls on CPUs/tasks
I have also replicated the problem on the ARM RealView (in tree) and
without the RT patches.
The problem ended up being caused by the allowed cpus mask being set
to all possible cpus for the ksoftirqd on the secondary processors.
So the RCU softirq was never executing on the secondary cpu.
The problem was that ksoftirqd was woken on the secondary processors before
the secondary processors were online. This led to allowed cpus being set
to all cpus.
wake_up_process()
try_to_wake_up()
select_task_rq()
if (... || !cpu_online(cpu))
select_fallback_rq(task_cpu(p), p)
...
/* No more Mr. Nice Guy. */
dest_cpu = cpuset_cpus_allowed_fallback(p)
do_set_cpus_allowed(p, cpu_possible_mask)
# Thus ksoftirqd can now run on any cpu...
</report>
The reason is that the ARM SMP boot code for the secondary CPUs enables
interrupts before the newly brought up CPU is marked online and
active.
That causes a wakeup of ksoftirqd or a wakeup of any other kernel
thread which is affine to the brought up CPU break that threads
affinity and therefor being scheduled on already online CPUs.
This problem has been observed on x86 before and the only solution is
to mark the CPU online and wait for the CPU active bit before the
point where interrupts are enabled.
Anson Huang [Tue, 8 May 2012 07:10:16 +0000 (15:10 +0800)]
ENGR00182243 [MX6]Fix suspend/resume issue
When there is pending wake up source before SOC enter DSM,
we should restore DDR IO and enable cache then return. Previous
code break r2 register which keep the iram stack addr, will
lead to DDR IO restore fail, need to avoid it.
Ryan QIAN [Mon, 7 May 2012 05:54:04 +0000 (13:54 +0800)]
ENGR00182054: [MX6]: always_present flag will't work as designed at some cond
As designed, when 'always_present' is set, it is assumed that cd_gpio should
be not set, and gpio_get_value(boarddata->cd_gpio) should return 0. But it is
not sure that the return value of gpio_get_value(0) is 0.
- check always_present first
- remove ESDHC_FLAG_GPIO_FOR_CD_WP flag if always_present is set.
Wayne Zou [Mon, 7 May 2012 04:47:30 +0000 (12:47 +0800)]
ENGR00180497 FB: Fix a bug: 'fb_set_par error, -22' when video playback on lvds
Change bg_id/fg_id variable to char array variable, and
avoid change the constant string in .rodata section.
[MX6Q SMD]fb: 'fb_set_par error, -22' prompted when mplay a video to lvds
/mnt/nfs/util/mplayer /mnt/nfs/test_stream/video/Mpeg4_SP1_1280x720_30fps.mp4
Before video playback finish, fb error message shows:
ENGR00181068: MX6 Source IPU_HSP and AXI clocks from 540M PFD.
IPU_HSP clocks should NOT be sourced from MMDC clock since the
MMDC clock can be scaled.
Move the IPU_HSP clock to be sourced from PLL3_PFD_540M instead.
Also don't source AXI_CLK from periph_clk as this domain is
scaled between 528MHz, 400MHz and 24MHz. Move AXI_CLK
clock to be sourced from PLL3_PFD_540M too.
When the system needs to enter low power mode, AXI_CLK is switched
from PLL3_PFD_540M to periph_clk. And then switched back
when low power mode is exited.
The code will print a warning message if PLL3_PFD_540M is
relocked to a different frequency when IPU_HSP or axi_clk is
sourced from it.
Currently remove the support for 400Mhz DDR working point for
MX6Q since we can get IPU underruns during the DDR frequency
transitions.
The DDR freq change code needs to ensure that all bus clocks
donot exceed max frequency during the frequency transition.
Chen Liangjun [Fri, 4 May 2012 09:49:51 +0000 (17:49 +0800)]
ENGR00181697 HDMI: fix ahb bus error bug
In ARIK, to prevent noise cause by false triggered burst, we reduce
the incr type to 4. and the change may cause bus_error because a
burst may unexpectly stop and thus an AHB bus error happens.
Reset HDMI Audio FIFO state to prevent AHB bus error. Signed-off-by: Chen Liangjun <b36089@freescale.com>
projects / karo-tx-linux.git / log