Since we've already reduced 2 cycles before writing PWMPR
register, the real period cycle on PWMO is the value of
period_cycles (before reducing 2). So, the following commit
message of ENGR00170342, which changes the duty cycle
calculation wrongly, is not reasonable:
===================================================
The chip document says the counter counts up to period_cycles + 1
and then is reset to 0, so the actual period of the PWM wave is
period_cycles + 2
===================================================
Revert "ENGR00170342 PWM: fix pwm output can't be set to 100% full duty"
Rong Dian [Fri, 25 Jan 2013 05:45:01 +0000 (13:45 +0800)]
ENGR00241739-1 thermal: providing the thermal hot notification
Create thermal hot's own hot notificaiton callback register and unregister
function.
Provide the thermal notification broadcast enable and disable through /sys fs.
make shi [Wed, 23 Jan 2013 02:36:00 +0000 (10:36 +0800)]
ENGR00241582 MX6 USB host: USB host certification patch
The patch include:
- USB test mode on hub port and Root-hub port
- support 3 types of message:
too much hub ties for hub attachment
too much power consumption for device attachment
unsupported device class warning
- support menuconfig select the FSL_USB_TEST_MODE, located in:
-> Device Drivers
-> USB support (USB_SUPPORT [=y])
-> FSL High-speed Electrical Test Mode support
Anson Huang [Wed, 23 Jan 2013 07:11:34 +0000 (15:11 +0800)]
ENGR00241003-2 pfuze: using _sel interface to add delay support
use regulator _sel interface set to support auto delay,
as when regulator's voltage go up, it will take some time
to ramp up to the required voltage, so the delay is necessary.
_sel interface set support such function, now we switch to this
interface set.
Anson Huang [Mon, 21 Jan 2013 08:20:56 +0000 (16:20 +0800)]
ENGR00241003-1 mx6: need to add delay in LDO voltage setting
1.LDO ramp up time may be modified by ROM code
according to fuse setting, cpu freq driver use
fixed delay time which assume the LDO ramp up time
is the reset value of ANATOP register, need to set
it to reset value in regulator init.
2.The regulator set voltage should take care of
the ramp up time, calculate the ramp up time based
of register setting and to the delay, make sure that
when the set voltage function return, the voltage is
stable enough.
3.CPUFreq no need to use delay, it is already taken
care by regulator voltage setting.
Loren HUANG [Fri, 9 Nov 2012 04:51:41 +0000 (12:51 +0800)]
ENGR00240988-5 Update gpu code to support 3.5 kernel
Cherry-pick from imx_3.5.7 branch.
-Comment regulator setting code temperarily for 3.5 kernel.
-Adjust clock setting code based on new clock framework.
-Disable dynamic frequency change feature as it depends on thermal
driver.
-Use DTS to get reserved memory information.
-Comment cpu check code for 3.5 kernel.
-Comment GPU reset code for 3.5 kernel.
Wayne Zou [Mon, 21 Jan 2013 05:44:54 +0000 (13:44 +0800)]
ENGR00240972-3 V4L2: VDI double frame rate for interlace stream
Each VPU decoded frame is de-interlaced twice inside v4l2 output driver,
and show twice also to achieve IPU/VDI double frame rate output.
This feature is disable by default.
This patch sets HDMI PHY register values in MXC HDMI driver
platform data so that MXC HDMI driver can configure the
0x09 CKSYMTXCTRL register(Clock Symbol and Transmitter
Control Register) and 0x0E VLEVCTRL register(Voltage Level
Control Register), then we may pass HDMI compliance test
for MX6 HDMI dongle board.
Enabling IPU hsp clock in mxcfb_probe() context by calling
ipu_init_channel() can avoid the IPU display channel(setup
in bootloader) from being damaged by some IPU common driver
APIS which enable/disable IPU hsp clock when doing driver
probe. However, somehow, after LDO bypass patch set is pushed
to kernel, this clock enablement can trigger IPU errors
(IPU_INT_STAT_5 - 0x00800000/IPU_INT_STAT_10 - 0x00100000) and
a display flash. A workaround is to enable IPU hsp clock when
we are at ipu_probe() context, which is earlier than mxcfb_probe()
context, and then to disable(cleanup) the clock once more when
fb_set_par() is triggered by the user for the first time. This
patch updates the comment for ipu_init_channel() and
ipu_enable_channel() in mxcfb_probe() context, and disables ipu
hsp clock when fb_set_par() is triggered by the user for the first
time.
Liu Ying [Fri, 18 Jan 2013 08:20:22 +0000 (16:20 +0800)]
ENGR00240740-1 IPUv3:Workaround bootup ipu error
Enabling IPU hsp clock in mxcfb_probe() context by calling
ipu_init_channel() can avoid the IPU display channel(setup
in bootloader) from being damaged by some IPU common driver
APIS which enable/disable IPU hsp clock when doing driver
probe. However, somehow, after LDO bypass patch set is pushed
to kernel, this clock enablement can trigger IPU errors
(IPU_INT_STAT_5 - 0x00800000/IPU_INT_STAT_10 - 0x00100000) and
a display flash. A workaround is to enable IPU hsp clock when
we are at ipu_probe() context, which is earlier than mxcfb_probe()
context, and then to disable(cleanup) the clock once more when
fb_set_par() is triggered by the user for the first time. This
patch exports an interface to disable ipu hsp clock so that
fb_set_par() may call it, and enables ipu hsp clock in ipu_probe()
context.
Sandor Yu [Fri, 11 Jan 2013 07:28:51 +0000 (15:28 +0800)]
ENGR00239734 Mx6 HDMI PHY: Add 2 variable to pass board specific config
The PHY register 0x9 and 0xe should setting
to different value in different board to pass HCT.
Add variable phy_reg_vlev and phy_reg_cksymtx to pass
phy config data.
Huang Shijie [Thu, 17 Jan 2013 08:15:45 +0000 (16:15 +0800)]
ENGR00240571 mtd: gpmi: fix the compiler warning
The current code may print out the following warning:
....................................................................
drivers/mtd/nand/gpmi-nand/gpmi-lib.c: In function gpmi_begin:
drivers/mtd/nand/gpmi-nand/gpmi-lib.c:1163: warning: hw.use_half_periods
may be used uninitialized in this function
drivers/mtd/nand/gpmi-nand/gpmi-lib.c:1163: warning: hw.sample_delay_factor
may be used uninitialized in this function
....................................................................
When disabling IPU channels, it needs less than 200us to wait for stop
Using msleep, it often sleep longer(above 10ms). So the extra delay
decrease the performance.
For 720p video playback on 1080p display(60Hz), the performance is about 40fps
With this patch, it can achieve around 60fps.
Richard Zhu [Mon, 7 Jan 2013 05:26:03 +0000 (13:26 +0800)]
ENGR00239905 PCIe Enable PCIe switch support
PCIe switch access mechanism:
- CfgRd0/CfgWr0 is used to access the CFG space of the EP device
or the upstream port of PCIe switch that is connected to RC directly.
- CfgRd1/CfgWr1 is used to access the CFG space of the downstream port
of PCIe switch and so on cases.
UR and kernel crash problem:
i.MX6 PCIe maps UR(Unsupported Request)err to AXI SLVERR err, which would
cause the arm data abort exception.
There is one "Received Master Abort" in iMX6 Root complex Secondary
status register when a requester receives a Completion
with Unsupported Request Completion Status.
In this case, the Linux kernel would be crashed.
Workaround: correct this imprecise external abort.
make shi [Thu, 10 Jan 2013 05:16:24 +0000 (13:16 +0800)]
ENGR00232755 USB: disable clock and abnormal wakeup when remove gadget driver
- In current bsp, the usb clock mismatch when rmmod gadget class driver. The
clock should be turn off when gadget class driver unregister.
- There is an abnormal usb wakeup interrupt happen if phy is no power without
VBUS. If we unplug the usb cable after unregister usb gadget driver, it is
difficult to handle the unexpected usb wakeup interrupt. SO we must call
dr_discharge_line() to make sure no abnormal usb wakeup interrupt happen in
usb unregister gadget class driver.
Sheng Nan [Tue, 8 Jan 2013 09:32:25 +0000 (17:32 +0800)]
ENGR00237682-3: mxc_v4l2_capture: ov5640: support scaling modes
The method for change between scaling and subsampling mode is different
from ov5640_mipi.
(image bigger than 1280*960 is scaling mode, smaller is subsampling).
According to OV5640 Auto Focus Camera Module Application Notes
(with DVP Interface) R2.14.pdf,
change back from QSXGA to VGA, don't need to do exposure calculation.
According to the test result, if we do exposure calculation when change
back from scaling to subsampling mode, the image would be dark.
So the method is:
Change to scaling mode, go through exposure calcuation.
Change to or back to subsampling mode, change mode directly.
Supported mode:
- QSXGA@7.5fps
- 1080P@7.5fps
Can't make 1080P works at 15fps. Here is a reply from ov fae:
because of scaling down, max frame for 1080P is the same as 5M, both are 15fps.
so if 5M can runs up to 7.5fps on your demo, then 1080P is the same 7.5fps max.
Sheng Nan [Wed, 19 Dec 2012 10:39:46 +0000 (18:39 +0800)]
ENGR00237682-2: mxc_v4l2_capture: ov5640: support all subsampling modes
Supported the following modes, verified image quality and frame rate
- VGA 30/15fps
- QVGA 30/15fps
- NTSC 30/15fps
- PAL 30/15fps
- 720P 30/15fps
Note: use the same setting as app note of ov5640 dvp
- QCIF 30/15fps
- XGA 22.5/15fps
Note: cannot make XGA work on 30fps. Just a reference of ov5640 datasheet:
1280*960 YUV422 maximum at 22.5fps.
1280*720 YUV422 maximum at 30fps.
Need to confirm later.
Sheng Nan [Wed, 19 Dec 2012 07:58:58 +0000 (15:58 +0800)]
ENGR00237682-1: mxc_v4l2_capture: ov5640: use global initialization
The current code struct of parallel ov5640 set mode directly.
The newest settings need to go through global initialization.
New settings are provided by ov company
So this patch does:
- Make parallel ov5640 mode settings go through global initialization.
- Only VGA (640 * 480) are provided as a validation of the new setting.
- Other modes will be provided in the later patches.
* Fix adv7180 tvin powerdown function
gpio power pin already exported in io-mux setup function
no need to request/free gpio
* Update copyrigth year 2013.
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Jason Liu [Tue, 8 Jan 2013 08:13:07 +0000 (16:13 +0800)]
fix echo 1 > compact_memory return error issue
when run the folloing command under shell, it will return error
sh/$ echo 1 > /proc/sys/vm/compact_memory
sh/$ sh: write error: Bad address
After strace, I found the following log:
...
write(1, "1\n", 2) = 3
write(1, "", 4294967295) = -1 EFAULT (Bad address)
write(2, "echo: write error: Bad address\n", 31echo: write error: Bad address
) = 31
This tells system return 3(COMPACT_COMPLETE) after write data to compact_memory.
The fix is to make the system just return 0 instead 3(COMPACT_COMPLETE) from
sysctl_compaction_handler after compaction_nodes finished.
Signed-off-by: Jason Liu <r64343@freescale.com> Suggested-by: David Rientjes <rientjes@google.com> Cc: Mel Gorman <mgorman@suse.de> Cc: Rik van Riel <riel@redhat.com> Cc: Minchan Kim <minchan@kernel.org> Cc: KAMEZAWA Hiroyuki <kamezawa.hiroyu@jp.fujitsu.com> Cc: <stable@vger.kernel.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Peter Chan [Tue, 8 Jan 2013 08:04:41 +0000 (16:04 +0800)]
ENGR00232879 mx6sl: EPDC VDDH and VPOS power on/off sequence is wrong
VDDH should only be ON after VPOS when power up and should be off
before VPOS when power down. Set the appropriate MAX17135 timing
parameters for the correct power up/down sequence
Robby Cai [Wed, 26 Dec 2012 07:26:39 +0000 (15:26 +0800)]
ENGR00238237-1 mx6sl: csi/v4l: fix camera picture flickering issue
Flickering issue happens when there's no buffer to be processed(e.g., the
pace of QBUF is much slower than DQBUF). The cause is the hardware is using
double buffering, while the driver has no good protection at above case and
thus the CSI will fill the buffer not in the right order. The way to fix is
refining the output of the working_q buffer list, that is, if there's no buffer
to be processed then output to a dummy buffer.
Another important change is to only do DMA reflash operation when SOF is
detected in streamon. Remove this operation is CSI interrupt handler because
it violates to the SPEC (only do DMA reflash before DMA is enabled but NOT at
the time or after DMA's enabled).
Signed-off-by: LiGang <b41990@freescale.com> Signed-off-by: Robby Cai <R63905@freescale.com>
(cherry picked from commit 0c4584763fa44b01a2f48198fa27c9206a116164)
Lionel Xu [Wed, 26 Dec 2012 05:54:49 +0000 (13:54 +0800)]
ENGR00238281 MX6SL_EVK: Add rfkill interface to bluetooth
MX6SL EVK board uses Silex SX-SDMAN board for bluetooth.
Add rfkill interface to control SX-SDMAN reset.
The reset signal is required before using bluetooth.
Gary Zhang [Fri, 4 Jan 2013 02:09:00 +0000 (10:09 +0800)]
ENGR00238809-2 mx6sl: ssi: add IRAM support
locate SSI playback buffer into IRAM in mx6sl.
because left IRAM room is not enough to contain record
buffer, if IRAM allocation for record fails, record
buffer will use external ram
Chen Liangjun [Fri, 28 Dec 2012 08:42:42 +0000 (16:42 +0800)]
ENGR00238439 ASRC: add delay before reading ASRC FIFO status
ASRC driver would read the sample number of ASRC output FIFO to fetch
the data from ASRC output FIFO. However, SDMA's fetching operation may
not finished before ASRC's reading. In this case, ASRC driver may read a
error data from the register.
In this patch, add delay before reading ASRC FIFO status to prevent
noise.
guoyin.chen [Fri, 7 Dec 2012 02:39:57 +0000 (10:39 +0800)]
ENGR00236141 csi:Add stride alignment setting from userspace
In android, IPU fills the I420 buffer. And GPU shows the buffer to display.
mx6's GPU has 32 Y-stride alignment for I420. The stride alignment will
be passed through by bytesperline. This update is only for
csi->smfc->mem channel.
Robin Gong [Wed, 19 Dec 2012 10:48:45 +0000 (18:48 +0800)]
ENGR00237742 busfreq:fix IPG_PERCLK will be decreased to 6M once exit low bus
on Sabresd board, IPG_PERCLK will be fixed on 6Mhz once system enter low bus,
and never restore to 22Mhz which be set in boot. It means some device clock
which sourcing from IPG_PERCLK such as I2C will be slow down. The root cause is
that there is workaround for GPT timer of Arik TO1.0 in mx6_ddr_freq.S. GPT
clock source from IPG_PERCLK on TO1.0 and should be fixed on 6Mhz. But for
TO1.1 and TO1.2 ,the workaround should be removed. Signed-off-by: Robin Gong <B38343@freescale.com>
Liu Ying [Wed, 19 Dec 2012 06:46:06 +0000 (14:46 +0800)]
ENGR00237678 IPUv3:Clean up sync and error interrupt
1) Split sync and error interrupt handler into 2 different
handlers, so that we may save several CPU cycles to
handler sync interrupt which is triggered in most IPU
usecases.
2) So far, every IPUv3 version in different SoCs has sync
and error interrupts, so we return -ENODEV if they cannot
be gotten from platform resource. Then, we may request
them directly but do not check more.
3) Clean up free irq code by removing unnecessary check.
Fugang Duan [Fri, 7 Dec 2012 10:48:34 +0000 (18:48 +0800)]
ENGR00236240 i2c: i2c performance optimization
It is unnecessary to calculate and update i2c divider during
every transaction. Only do it if current i2c clock is different
with the previous clock frequency.
Hongzhang Yang [Thu, 13 Dec 2012 08:44:16 +0000 (16:44 +0800)]
ENGR00236879 Enhance VPU driver to handle API call sequence abnormal abort
Some application may exit without calling neccessay API to wrap up VPU
after it receives error message.
This could lead to system hang because driver will power off VPU
(vpu_release) while VPU may still be busy.
We require application to strictly follow the API call sequence even in
error handling case. Meanwhile, we enhance VPU driver to protect against
such abnormal abort, to prevent system hang at least.
If the last instance is closed, VPU will gate off or power off only if
VPU is idle.
Signed-off-by: Hongzhang Yang <Hongzhang.Yang@freescale.com>
LiGang [Wed, 14 Nov 2012 02:12:53 +0000 (10:12 +0800)]
ENGR00231808: Add epdc pmic shut down feature
For some cases, system maybe restart with epdc pmic on.
If epdc pmic on for sometime(2~3s), the current epdc pmic consume will increase
obviously, then the total current of board maybe exceed to the current limit,
which will pull down the input voltage to lead to the system pmic reset,
an un-expected POR reset occurs.
So it is necessary to close epdc pmic before system restart.
This patch is added by Robby Cai<r63905@freescale.com>
Robby Cai [Mon, 10 Dec 2012 09:13:45 +0000 (17:13 +0800)]
ENGR00236722 mx6sl: csi: Ensure dma reflash operation done when dma is disabled
If do dma reflash operation when dma is enabled, the system will hang and we
can not connect to the core through jtag. The reason is the reflash signal
(DMA_REFLASH_RFF) will initialize the AHB bus signals and it indeed seems to
modify the AHB address on the clock as soon as the programmable register value
is changed, the bus may not respond.
This patch revised it according to the RM:
"Reflash DMA Controller for RxFIFO. This bit reflash the embedded DMA controller
for RxFIFO. It should be reflashed before the embedded DMA controller starts
to work."
Robby Cai [Thu, 29 Nov 2012 09:58:43 +0000 (17:58 +0800)]
ENGR00229855 mx6sl: csi: can not support two camera instances
run two unit test instances as follows fails (sometimes kernel dump).
/unit_tests/csi_v4l2_capture.out &
/unit_tests/csi_v4l2_capture.out
Fix by improving the resource lock.
- We get busy_lock semaphore before we get a dqueue event, so, when user
is blocked at DQBUF ioctrl, the user will also be blocked at QBUF ioctrl,
then the video performance will drop. This patch changes to get busy_lock
semaphore to protect DQBUF ioctrl until we successfully get a dqueue event.
- Use queue_int_lock spinlock to protect cam->ping_pong_csi, since it can be
modified either in irq handler or in queue event.
- linked list should be protected by the lock:
-- Use queue_int_lock and dqueue_int_lock spinlocks to protect working_q/
ready_q/done_q in the end of frame interrupt handler camera_callback(),
in case, the handler and VIDIOC_QBUF/VIDIOC_DQBUF ioctrls are called on
different threads at same time.
-- Protect ready_q with queue_int_lock spinlock in streamon(), in case,
VIDIOC_STREAMON and VIDIOC_QBUF ioctrls are called on different threads
at same time.
ENGR00236837 MX6SL-Fix random crash caused by incorrect setting of IPG clk rate.
Need to ensure that bus frequency setpoint is changed only if
the system is not already at the requested setpoint.
Changing the bus freq to high setpoint when its already at
high setpoint causes the AHB/IPG dividers to be set incorrectly.
Then when the system enters WAIT mode, the 12:5 ratio of
ARM_CLK:IPG_CLK is no longer maintained.
This causes random crashes.
Fix is to return immediately if the bus is already at the
requested setpoint
make shi [Mon, 10 Dec 2012 08:40:05 +0000 (16:40 +0800)]
ENGR00236169 MX6 USB :kfree udc_controller when remove udc driver
Kree and reset udc_controller should be done when remove udc driver to avoid
kernel dump during modprobe gadget driver after modprobe and rmmod udc driver.
Gary Zhang [Tue, 11 Dec 2012 04:42:42 +0000 (12:42 +0800)]
ENGR00236020-1 ALSA: add calling of trigger in machine driver
soc_pcm_trigger() calls trigger functions of cpu_dai, codec_dai
and platform, but the trigger function of machine is not called.
add calling of trigger in machine driver in soc_pcm_trigger()
Zhang Jiejing [Tue, 11 Dec 2012 07:34:25 +0000 (15:34 +0800)]
ENGR00235817 mx6: use SNVS LPGPR register to store boot mode value.
After using POR reset, the content in SRC will be reset.
See RM: 63.5.1.2.3 IPP_RESET_B(POR)
Because POR reset will reset most of register in IC, so use
SNVS_LP General Purpose Register (LPGPR) to store the boot mode value.
Below copy from SNVS_BlockGuide.pdf:
The SNVS_LP General Purpose Register provides a 32 bit read write
register, which can be used by any application for retaining 32 bit
data during a power-down mode
Sheng Nan [Wed, 5 Dec 2012 02:22:35 +0000 (10:22 +0800)]
ENGR00235665: mxc_v4l2_capture: add YV12 format support in camera driver
Android CTS verifier have a must requirement for YV12 format. Since IPUv3
common driver has supported IPU_PIX_FMT_YVU420P pixel format, add the
support of YV12 format in mxc_v4l2_capture.
make shi [Thu, 6 Dec 2012 09:19:30 +0000 (17:19 +0800)]
ENGR00236031 MX6 USB :Change default USB H1 and OTG driver load order
In current linux BSP USB H1 driver default load before otg driver load,
which cause USBx not match the ehci controller number. like bellow:
root@freescale /sys/devices/platform/fsl-ehci.0$ ls
driver modalias pools power subsystem uevent usb2
root@freescale /sys/devices/platform/fsl-ehci.1$ ls
driver modalias pools power subsystem uevent usb1
Hongzhang Yang [Tue, 6 Nov 2012 06:49:38 +0000 (14:49 +0800)]
ENGR00232530 Refine VPU suspend/resume according to open_count
1. Refine VPU suspend/resume according to open_count to completely
fix bug: ENGR00230203 [Android_MX6DL_SD] Gallery: System hang
after resume from suspend during video playback. 20%
open_count == 0 case can be simplified because VPU is released
(all instances are freed), so
- clock is already off
- context is no longer needed
- power is already off on MX6
VPU reset is removed from resume because power is ensured to be off
before entering resume on MX6 by calling regulator API.
2. Fix bug: VPU always busy after suspend/resume
Error log (VPU refused to suspend due to VPU busy):
pm_op(): platform_pm_suspend+0x0/0x54 returns -11
PM: Device mxc_vpu failed to suspend: error -11
PM: Some devices failed to suspend
Root cause:
- Suspend happened during vpu_Init(), somewhere after VPU lib started
to download FW (when PC == 0), but before run FW. (BIT_BUSY_FLAG=1,
BIT_CODE_RUN=1).
- In such case, VPU resume downloaded FW and run VPU to idle because
suspend was triggered after VPU was opened (active).
- vpu_Init run VPU again with BIT_BUSY_FLAG=1. So VPU was trapped in
idle loop but BIT_BUSY_FLAG was never cleared. VPU lib regarded VPU
as always busy.
Solution (in VPU resume):
- run VPU FW only if VPU was opened and PC before suspend is not 0
- restore host register is required
- download FW is required, because program memory is lost after power
off.
Signed-off-by: Hongzhang Yang <Hongzhang.Yang@freescale.com>
Fugang Duan [Thu, 29 Nov 2012 08:55:12 +0000 (08:55 +0000)]
ENGR00235626 FEC: Enable phy pause frame feature
Since some ethernet MAC flow control is relied on phy pause
status, both link partners exchange information via auto neg to
determine if both parties are capable of flow control.
Advertise phy pause frame to avoid pause frame is not responsed
by the other net node.
make shi [Wed, 5 Dec 2012 06:31:41 +0000 (14:31 +0800)]
ENGR00235630 MX6 USB :fix USB does not work when plug in device during suspend
USB does not work when plug in a usb device during system suspend. Under this
case, USB driver will be in low power mode, but WIE bit not be set if usb wake
up is not enabled.So there are only ID change interrupt no USB wakeup interrupt
after system resume.In current bsp, after system resume ID change status not be
clear,and ID change interrupt will continue happen, which cause the system busy.
No checking WIR bit if ID change interrupt happen when USB in low power mode to
fix this issue.
make shi [Thu, 29 Nov 2012 08:28:25 +0000 (16:28 +0800)]
ENGR00234722 USB: fix Kernel dump issue after USB driver loadable
- It is better to disable otgsc and wake up interrupt to avoid an
abnormal interrupt happen during USB driver being removed.
- If the USB host is already at low power mode, only need turn on
the clock, no need turn off the clock.
- Need discharge dp and dm during USB driver being removed ,in order
to avoid a wakeup interrupt happen. And if the USB otg is in host
mode, we should clear discharge dp and dm in fsl_otg_set_host()
during system boot up.
I2C driver call the function "static void __init i2c_imx_set_clk()"
in runtime, the function is linked to init.text section, and don't
be used after kernel bootup. Remove the "__init" statement to fix
the issue.
Alejandro Sierra [Wed, 21 Nov 2012 16:01:26 +0000 (10:01 -0600)]
ENGR00234466 UART: Fix disablement of CTS signal
On Uart driver, CTS signal were never disabled
on the imx_set_mctrl function since the register was
written inside of the conditional.
if (mctrl & TIOCM_RTS) {
temp |= UCR2_CTS;
writel(temp, sport->port.membase + UCR2);
}
Signed-off-by: Alejandro Sierra <b18039@freescale.com>
Fugang Duan [Wed, 28 Nov 2012 02:40:52 +0000 (10:40 +0800)]
ENGR00235086 I2C: update i2c clock divider for each transaction
Currently on Arik/Rigel, the I2C clk is from IPG_PERCLK which is
sourced from IPG_CLK. Under normal operation, ipg_perclk is at 22MHz
so that we can get 400KHz i2c speed. In low bus freq mode, IPG_CLK is
at 12MHz and IPG_PERCLK is down to 4MHz.
So the I2C driver must update the divider register for each transaction.
Fugang Duan [Tue, 27 Nov 2012 09:44:19 +0000 (17:44 +0800)]
ENGR00235090 FEC: Workaround for FEC RX hang with stress test
When do Ethernet UDP stress overnight test with abundance of
data transmission, RX path may hang-on.
Dump the RX BD, found all BD "Empty" bit is cleared, which means
CPU read BD status is not right and waiting here.
Change BD memroy attribute from Normal to strongly ordered:
changes the memory attribute of C=0, B=0 instead of C=0, B=1.
Apply the change, the issue cannot be reproduced.
Ryan QIAN [Tue, 27 Nov 2012 23:54:32 +0000 (07:54 +0800)]
ENGR00234933 mmc: sdhci: invalid cd_gpio for always_present host controller
Issue:
By default, cd_gpio is 0 for always presented host controller, which is a
valid gpio. Then it will result to free_irq for 0 in esdhc_pltfm_exit for
these always_present host controllers.
Fix:
Invalid cd_gpio if the controller is indicated to be always present.
Acked-by: Dong Aisheng <b29396@freescale.com> Signed-off-by: Ryan QIAN <b32804@freescale.com>
Michal Hocko [Tue, 10 Jan 2012 23:08:02 +0000 (15:08 -0800)]
mm: fix off-by-two in __zone_watermark_ok()
Commit 88f5acf88ae6 ("mm: page allocator: adjust the per-cpu counter
threshold when memory is low") changed the form how free_pages is
calculated but it forgot that we used to do free_pages - ((1 << order) -
1) so we ended up with off-by-two when calculating free_pages.
Reported-by: Wang Sheng-Hui <shhuiw@gmail.com> Signed-off-by: Michal Hocko <mhocko@suse.cz> Acked-by: Mel Gorman <mgorman@suse.de> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Robin Gong [Mon, 26 Nov 2012 03:25:55 +0000 (11:25 +0800)]
ENGR00234685-2 mx6q_sabreauto: change Sabreauto board to LDO-ENABLED mode
Per hardware design, we can't set LDO bypass mode on Sabreauto board,otherwise,
system will can't reset,if cpu freq run in 400Mhz. Signed-off-by: Robin Gong <b38343@freescale.com>
Robin Gong [Mon, 26 Nov 2012 03:23:28 +0000 (11:23 +0800)]
ENGR00234685-1 cpufreq:fix one bug in cpufreq driver if I2C transfer error
Currently, if we used LDO bypass, will set pfuze register by I2C bus to modify
voltage according to different cpu frequency, if I2C transfer error, we should
restore to old cpu frequency, not only in cpufreq driver but also cpufreq core.
Ge Lei [Fri, 23 Nov 2012 06:36:04 +0000 (14:36 +0800)]
ENGR00233569 SDMA: Add support for SDMA M2M copy
Our SDMA code did not support SDMA M2M copy function before, we add
SDMA M2M copy function in this patch, you can use 'sg' to use this
function, you can refer to 'linux-test/module_test/mxc_sdma_memcopy_test.c'
for how to use this function.
Ryan QIAN [Thu, 22 Nov 2012 07:38:46 +0000 (15:38 +0800)]
ENGR00234519 mmc: support eMMC v4.5 memory cards
Bypass eMMC version checking, so that eMMC v4.5 can work on current kernel as
eMMC v4.4 cards, no specific v4.5 feature supported. Only basic read/write
operations are supported, also ddr mode is supported.
Acked-by: Dong Aisheng <b29396@freescale.com> Signed-off-by: Ryan QIAN <b32804@freescale.com>
Sheng Nan [Fri, 23 Nov 2012 02:59:22 +0000 (10:59 +0800)]
ENGR00234362 Camera: ov5640_mipi: wait for sensor stable before streamon
ov5642 add some delay to wait for sensor stable after S_PARM.
And ov5640_mipi should keep the same behavior.
So the upper layer can trust the first frame comes out of ov5640_mipi.
- delay added according to the recommended time from ov company
Steve Cornelius [Tue, 20 Nov 2012 23:21:26 +0000 (16:21 -0700)]
ENGR00234401: CAAM: Fix incorrect invalidate call for output ring
The job ring driver exhibited a hang condition in the top of
caam_jr_dequeue() where a BUG_ON statement looks for a condition
where the output ring is said to have valid entries by the ring logic,
but the ring entries apparently have NULL descriptor pointers.
In the initial ARM port of this driver, the cache flush call
of the output ring content occured before the output ring read index
register read occurred, exposing a condition where the driver sensed valid
output entries, yet the entries written by the ring hardware were not
invalidated, and therefore were not visible to the processor, appearing
as false NULL entries.
This patch relocates the invalidate call to immediately follow the
check of the output read index, where it is required.
Signed-off-by: Vicki Milhoan <vicki.milhoan@freescale.com> Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com> Signed-off-by: Terry Lv <r65388@freescale.com>
Robin Gong [Thu, 22 Nov 2012 05:31:05 +0000 (13:31 +0800)]
ENGR00234411-1 Sabreauto: fix error print COULD NOT SET GP VOLTAGE.
Didn't take more care about non-pfuze board, and there is two place in BSP will
call "mx6_cpu_regulator_init". It means regulator_get will be called twice on
every vddcore/vddsoc regulator. Then one value need set twice ,because from
regulator core view, there is two regulators share the same regulator. The non-
validate one will return error and print "COULD NOT SET GP VOLTAGE!!!!." on
Sabreauto board. The same as Sabrelite and ARM2 board.
Meanwhile, Sabreauto need be configured LDO bypass default. Signed-off-by: Robin Gong <b38343@freescale.com>
projects / karo-tx-linux.git / log