When the frequency on the nand chip pins is above 33MHz,
the nand EDO(extended Data Out) timing could be applied.
The GPMI implements a Feedback read strobe to sample the read data in
the EDO timing mode.
This patch adds the EDO feature for the gpmi-nand driver.
For some onfi nand chips, the mode 4 is the fastest;
while for other onfi nand chips, the mode 5 is the fastest.
This patch only adds the support for the fastest asynchronous timing mode.
So this patch only supports the mode 4 and mode 5.
I tested several Micron's ONFI nand chips with EDO enabled,
take Micron MT29F32G08MAA for example (in mode 5, 100MHz):
1) The test result BEFORE we add the EDO feature:
=================================================
mtd_speedtest: MTD device: 2
mtd_speedtest: MTD device size 209715200, eraseblock size 524288,
page size 4096, count of eraseblocks 400,
pages per eraseblock 128, OOB size 218
.......................................
mtd_speedtest: testing eraseblock read speed
mtd_speedtest: eraseblock read speed is 3632 KiB/s
.......................................
mtd_speedtest: testing page read speed
mtd_speedtest: page read speed is 3554 KiB/s
.......................................
mtd_speedtest: testing 2 page read speed
mtd_speedtest: 2 page read speed is 3592 KiB/s
.......................................
=================================================
2) The test result AFTER we add the EDO feature:
=================================================
mtd_speedtest: MTD device: 2
mtd_speedtest: MTD device size 209715200, eraseblock size 524288,
page size 4096, count of eraseblocks 400,
pages per eraseblock 128, OOB size 218
.......................................
mtd_speedtest: testing eraseblock read speed
mtd_speedtest: eraseblock read speed is 19555 KiB/s
.......................................
mtd_speedtest: testing page read speed
mtd_speedtest: page read speed is 17319 KiB/s
.......................................
mtd_speedtest: testing 2 page read speed
mtd_speedtest: 2 page read speed is 18339 KiB/s
.......................................
=================================================
3) The read data performance is much improved by more then 5 times.
mtd: gpmi: do not set the default values for the extra clocks
The default frequencies of the extra clocks are 200MHz.
The current code sets the extra clocks to 44.5MHz.
When i add the EDO feature to gpmi, i have to revert the extra clocks
to 200MHz.
So it is better that we do not set the default values for the extra
clocks. The driver runs well even when we do not set the default values for
extra clocks.
The gpmi_nfc_compute_hardware_timing{} should contains all the
fields setting for gpmi timing registers. It already contains the fields
for HW_GPMI_TIMING0 and HW_GPMI_CTRL1.
So it is better to add a new field setting for HW_GPMI_TIMING1 in
this data structure. This makes the code more clear in logic.
This patch also changes some comments to make the code more readable.
Mike Dunn [Tue, 11 Sep 2012 15:50:50 +0000 (08:50 -0700)]
mtd: docg4: ecc.read_page() returns 0 on uncorrectable errors
Currently the docg4's ecc.read_page() method returns -EBADMSG when
uncorrectable bitflips occur. This is wrong; 0 should be returned in
this case. An error code should only be returned by this method in the
case of a hardware error (probably -EIO).
Signed-off-by: Mike Dunn <mikedunn@newsguy.com> Acked-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Mike Dunn [Tue, 11 Sep 2012 15:59:03 +0000 (08:59 -0700)]
mtd: nand: expand description of read_page method in comment header
In the absence of any formal documentation of the nand interface, I thought this
patch to the header file might be helpful.
Signed-off-by: Mike Dunn <mikedunn@newsguy.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
mtd: nand: clk: preparation for switch to common clock framework
As a first step towards migrating davinci platforms to use common clock
framework, replace all instances of clk_enable() with clk_prepare_enable()
and clk_disable() with clk_disable_unprepare(). Until the platform is
switched to use the CONFIG_HAVE_CLK_PREPARE Kconfig variable, this just
adds a might_sleep() call and would work without any issues.
This will make it easy later to switch to common clk based implementation
of clk driver from DaVinci specific driver.
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Reviewed-by: Mike Turquette <mturquette@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Akinobu Mita [Fri, 7 Sep 2012 16:48:10 +0000 (01:48 +0900)]
mtd: mtd_nandecctest: add double bit error detection tests
This adds the double bit error detection test cases listed below:
* Prepare data block with double bit error and ECC data without
corruption, and verify that the uncorrectable error is detected by
__nand_correct_data().
* Prepare data block with single bit error and ECC data with single bit
error, and verify that the uncorrectable error is detected.
* Prepare data block without corruption and ECC data with double bit
error, and verify that the uncorrectable error is detected.
Signed-off-by: Akinobu Mita <akinobu.mita@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Akinobu Mita [Fri, 7 Sep 2012 16:48:07 +0000 (01:48 +0900)]
mtd: mtd_nandecctest: rewrite the test routine
This rewrites the entire test routine in order to make it easy to add more
tests by later changes and minimize duplication of each tests as much as
possible.
Now that each test is described by the members of struct nand_ecc_test:
- name: descriptive testname
- prepare: function to prepare data block and ecc with artifical corruption
- verify: function to verify the result of correcting data block
Signed-off-by: Akinobu Mita <akinobu.mita@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Akinobu Mita [Fri, 7 Sep 2012 16:48:06 +0000 (01:48 +0900)]
mtd: mtd_nandecctest: support injecting bit error for ecc code
Currently inject_single_bit_error() is used to inject single bit error
into randomly selected bit position of the 256 or 512 bytes data block.
Later change will add tests which inject bit errors into the ecc code.
Unfortunately, inject_single_bit_error() doesn't work for the ecc code
which is not a multiple of sizeof(unsigned long).
Because bit fliping at random position is done by __change_bit().
For example, flipping bit position 0 by __change_bit(0, addr) modifies
3rd byte (32bit) or 7th byte (64bit) on big-endian systems.
Using little-endian version of bitops can fix this issue. But
little-endian version of __change_bit is not yet available.
So this defines __change_bit_le() locally in a similar fashion to
asm-generic/bitops/le.h and use it.
Signed-off-by: Akinobu Mita <akinobu.mita@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Iwo Mergler [Thu, 30 Aug 2012 22:59:48 +0000 (08:59 +1000)]
mtd: tests: test for multi-bit error correction
This tests ECC biterror recovery on a single NAND page. Mostly intended
to test ECC hardware and low-level NAND driver.
There are two test modes:
0 - artificially inserting bit errors until the ECC fails
This is the default method and fairly quick. It should
be independent of the quality of the FLASH.
1 - re-writing the same pattern repeatedly until the ECC fails.
This method relies on the physics of NAND FLASH to eventually
generate '0' bits if '1' has been written sufficient times. Depending
on the NAND, the first bit errors will appear after 1000 or
more writes and then will usually snowball, reaching the limits
of the ECC quickly.
The test stops after 10000 cycles, should your FLASH be exceptionally
good and not generate bit errors before that. Try a different page
offset in that case.
Please note that neither of these tests will significantly 'use up' any FLASH
endurance. Only a maximum of two erase operations will be performed.
Marek Vasut [Tue, 4 Sep 2012 03:31:36 +0000 (05:31 +0200)]
mtd: m25p80: Disable 4KiB erase for s25sl032p, s25sl064p
Quoting from the datasheet for S25FL064P, rev. 05, Nov 18 2011, § 9.17:
"A 64 kB[sic] sector erase (D8h) command issued on 4 kB or 8 kB erase
sectors will erase all sectors in the specified 64 kB region. However,
please note that a 4 kB sector erase (20h) or 8 kB sector erase (40h)
command will not work on a 64 kB sector."
Referring further to Table 8.1 and Table 8.2, it is clearly seen
that most of the sectors are 64KiB; therefore disable this 4KiB
erase support since it's valid only on first/last sectors.
Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Akinobu Mita [Mon, 3 Sep 2012 13:00:01 +0000 (22:00 +0900)]
mtd: mtd_nandecctest: ensure alignment requirement for bitops
Currently the data blocks which is used to test single bit error
correction is allocated statically and injecting single bit error is
implemented by using __change_bit() which must operate on the memory
aligned to the size of an "unsigned long". But there is no such
guarantee for statically allocated array.
This fix the issue by allocating the data block dynamically by
kmalloc(). It also allocate the ecc code dynamically instead of
allocating statically on stack.
The reason to allocate the ecc code dynamically is that later change
will add tests which inject bit errors into the ecc code by bitops.
Signed-off-by: Akinobu Mita <akinobu.mita@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Akinobu Mita [Mon, 3 Sep 2012 13:00:00 +0000 (22:00 +0900)]
mtd: mtd_nandecctest: improve message output
This includes the message related changes:
- Use pr_* instead of printk
- Print hexdump of ECC code if test fails
- Change log level for hexdump of data from KERN_DEBUG to KERN_INFO
- Factor out the hexdump code into a separate function
Signed-off-by: Akinobu Mita <akinobu.mita@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Brian Norris [Fri, 31 Aug 2012 22:01:19 +0000 (15:01 -0700)]
JFFS2: don't fail on bitflips in OOB
JFFS2 was designed without thought for OOB bitflips, it seems, but they
can occur and will be reported to JFFS2 via mtd_read_oob()[1]. We don't
want to fail on these transactions, since the data was corrected.
[1] Few drivers report bitflips for OOB-only transactions. With such
drivers, this patch should have no effect.
Signed-off-by: Brian Norris <computersforpeace@gmail.com> Cc: stable@vger.kernel.org Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
This patch revises and fixes error handling in the command line mtd
partitions parser. Namely:
1. we ignored return code of 'mtdpart_setup_real()'.
2. instead of returning 0 for failure and 1 for success, teach
'mtdpart_setup_real()' to return real error codes.
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Rafał Miłecki [Thu, 30 Aug 2012 05:41:16 +0000 (07:41 +0200)]
mtd: bcm47part driver for BCM47XX chipsets
This driver provides parser detecting partitions on BCM47XX flash
memories. It has many differences in comparison to BCM63XX, like:
1) Different CFE with no more trivial MAGICs
2) More partitions types (board_data, ML, POT)
3) Supporting more than 1 flash on a device
which resulted in decision of writing new parser.
It uses generic mtd interface and was successfully tested with Netgear
WNDR4500 router which has 2 flash memories: serial one and NAND one.
Andreas Bießmann [Fri, 31 Aug 2012 11:35:42 +0000 (13:35 +0200)]
mtd: omap2: fix module loading
Unloading the omap2 nand driver missed to release the memory region which will
result in not being able to request it again if one want to load the driver
later on.
This patch fixes following error when loading omap2 module after unloading:
---8<---
~ $ rmmod omap2
~ $ modprobe omap2
[ 37.420928] omap2-nand: probe of omap2-nand.0 failed with error -16
~ $
--->8---
Andreas Bießmann [Fri, 31 Aug 2012 11:35:41 +0000 (13:35 +0200)]
mtd: omap2: fix omap_nand_remove segfault
Do not kfree() the mtd_info; it is handled in the mtd subsystem and
already freed by nand_release(). Instead kfree() the struct
omap_nand_info allocated in omap_nand_probe which was not freed before.
This patch fixes following error when unloading the omap2 module:
Stefan Roese [Tue, 28 Aug 2012 09:34:13 +0000 (11:34 +0200)]
mtd: cfi_cmdset_0001: Fix problem with unlocking timeout
Unlocking may take up to 1.4 seconds on some Intel flashes. So
lets use a max. of 1.5 seconds (1500ms) as timeout.
See "Clear Block Lock-Bits Time" on page 40 in
"3 Volt Intel StrataFlash Memory" 28F128J3,28F640J3,28F320J3 manual
from February 2003
This patch also fixes some other problems with this timeout:
- Don't use HZ in timeout "calculation"!
While testing we noticed that an unlocking timeout occured with
HZ=1000 and didn't occur with HZ=300. This was because the
timeout parameter was calculated differently depending on the
HZ value. Now a fixed value of 1500ms is used.
- The last parameter of WAIT_TIMEOUT (defined to
inval_cache_and_wait_for_operation) has to be passed in
micro-seconds. So multiply the ms value with 1000 and not 100
to calculate this value.
- Use variable name "mdelay" instead of misleading "udelay".
Signed-off-by: Stefan Roese <sr@denx.de> Tested-by: Stephan Gatzka <stephan@gatzka.org> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Jeff Westfahl [Mon, 13 Aug 2012 21:35:30 +0000 (16:35 -0500)]
mtd: nand: Added a device flag for subpage read support
Added a NAND device flag for subpage read support. Previously this was
hard coded based on large page and soft ECC.
Updated base NAND driver to use the new subpage read flag if the NAND is
large page and soft ECC.
Signed-off-by: Jeff Westfahl <jeff.westfahl@ni.com> Reviewed-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Thomas Petazzoni [Mon, 27 Aug 2012 23:35:28 +0000 (01:35 +0200)]
mtd: orion_nand: remove <mach/hardware.h> include
Commit abcda1dc ('arm: plat-orion: introduce PLAT_ORION_LEGACY hidden
config option') currently pending in linux-next will make the ARCH_MVEBU
platform select PLAT_ORION, which means that now all Orion drivers can
be enabled on ARCH_MVEBU. This works fine for most drivers, except for
orion_nand, because it includes <mach/hardware.h>, but mach-mvebu does
not have a mach/hardware.h header (it is considered as a deprecated
practice).
It turns out that the <mach/hardware.h> include in orion_nand is not
necessary: the driver builds perfectly fine without it, so we simply
get rid of it.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Tested-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Roland Stigge [Fri, 24 Aug 2012 13:06:52 +0000 (15:06 +0200)]
mtd: lpc32xx_mlc: Cleanup after DT-only conversion
The LPC32xx's DT-only conversion of the MLC NAND driver makes NAND config via
platform_data obsolete. Dropped by this patch.
Further, the driver really needs CONFIG_OF, which is already reflected by the
dependency on ARCH_LPC32XX which depends on CONFIG_OF. So also dropping
CONFIG_OF ifdefs.
There is still platform_data necessary to supply the dma_filter callback for
the dma engine. This is a completely different data structure than the old
platform_data for NAND config, so renaming some old "pdata" variable to "ncfg"
to prevent confusion with the new platform data.
Signed-off-by: Roland Stigge <stigge@antcom.de> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Roland Stigge [Fri, 24 Aug 2012 13:06:51 +0000 (15:06 +0200)]
mtd: lpc32xx_slc: Cleanup after DT-only conversion
The LPC32xx's DT-only conversion of the SLC NAND driver makes NAND config via
platform_data obsolete. Dropped by this patch.
Further, the driver really needs CONFIG_OF, which is already reflected by the
dependency on ARCH_LPC32XX which depends on CONFIG_OF. So also dropping
CONFIG_OF ifdefs.
There is still platform_data necessary to supply the dma_filter callback for
the dma engine. This is a completely different data structure than the old
platform_data for NAND config, so renaming some old "pdata" variable to "ncfg"
to prevent confusion with the new platform data.
Signed-off-by: Roland Stigge <stigge@antcom.de> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Shmulik Ladkani [Mon, 20 Aug 2012 13:29:15 +0000 (16:29 +0300)]
mtd: nand: rename create_bbt()'s 'len' variable to 'numpages'
Rename 'len' variable of create_bbt/scan_block_fast/scan_block_full to
'numpages', since it really means number of pages to scan when
searching for the BBM (and not the byte length of the scan).
Signed-off-by: Shmulik Ladkani <shmulik.ladkani@gmail.com> Reviewed-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Sachin Kamat [Tue, 21 Aug 2012 08:54:10 +0000 (14:24 +0530)]
mtd: s3c2410: Fix compiler warnings
Fixes the following warnings:
‘s3c2410_nand_correct_data’ defined but not used [-Wunused-function]
‘s3c2410_nand_enable_hwecc’ defined but not used [-Wunused-function]
‘s3c2412_nand_enable_hwecc’ defined but not used [-Wunused-function]
‘s3c2440_nand_enable_hwecc’ defined but not used [-Wunused-function]
‘s3c2410_nand_calculate_ecc’ defined but not used [-Wunused-function]
‘s3c2412_nand_calculate_ecc’ defined but not used [-Wunused-function]
‘s3c2440_nand_calculate_ecc’ defined but not used [-Wunused-function]
The above functions are called only when CONFIG_MTD_NAND_S3C2410_HWECC
is defined. Thus making them conditional.
Sachin Kamat [Tue, 21 Aug 2012 08:54:09 +0000 (14:24 +0530)]
mtd: s3c2410: Use devm_* functions
devm_* functions are device managed functions and make cleanup code
simpler and smaller.
devm_kzalloc, devm_clk_get and devm_request_and_ioremap functions
are used.
Huang Shijie [Sat, 18 Aug 2012 17:07:41 +0000 (13:07 -0400)]
mtd: mtdpart: break it as soon as we parse out the partitions
We may cause a memory leak when the @types has more then one parser.
Take the `default_mtd_part_types` for example. The default_mtd_part_types has
two parsers now: `cmdlinepart` and `ofpart`.
Assume the following case:
The kernel command line sets the partitions like:
#gpmi-nand:20m(boot),20m(kernel),1g(rootfs),-(user)
But the devicetree file(such as arch/arm/boot/dts/imx28-evk.dts) also sets
the same partitions as the kernel command line does.
In the current code, the partitions parsed out by the `ofpart` will
overwrite the @pparts which has already set by the `cmdlinepart` parser,
and the the partitions parsed out by the `cmdlinepart` is missed.
A memory leak occurs.
So we should break the code as soon as we parse out the partitions,
In actually, this patch makes a priority order between the parsers.
If one parser has already parsed out the partitions successfully,
it's no need to use another parser anymore.
On some platforms (e.g. MPC5200) a direct 1:1 mapping may cause
problems with JFFS2 usage, as the local bus (LPB) doesn't support
unaligned accesses as implemented in the JFFS2 code via memcpy().
By defining "no-unaligned-direct-access", the flash will not be
exposed directly to the MTD users (e.g. JFFS2) any more.
Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Julia Lawall [Sat, 4 Aug 2012 20:36:38 +0000 (22:36 +0200)]
mtd: spear_smi: use devm_ functions consistently
Use devm_kzalloc for all calls to kzalloc and not just the first. Use devm
functions for other allocations as well.
Move the call to platform_get_resource(pdev, IORESOURCE_MEM, 0) closer to
where its result is passed to devm_request_and_ioremap to make the lack of
need for a NULL test more evident.
The semantic match that finds the inconsistency is as follows:
(http://coccinelle.lip6.fr/)
// <smpl>
@@
@@
*devm_kzalloc(...)
...
*kzalloc(...)
// </smpl>
Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
John Crispin [Thu, 23 Aug 2012 18:28:32 +0000 (20:28 +0200)]
mtd: lantiq: Add NAND support on Lantiq XWAY SoC.
The driver uses plat_nand. As the platform_device is loaded from DT, we need
to lookup the node and attach our xway specific "struct platform_nand_data"
to it.
Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Huang Shijie [Wed, 15 Aug 2012 02:38:45 +0000 (22:38 -0400)]
mtd: kill MTD_NAND_VERIFY_WRITE
Just as Artem suggested:
"Both UBI and JFFS2 are able to read verify what they wrote already.
There are also MTD tests which do this verification. So I think there
is no reason to keep this in the NAND layer, let alone wasting RAM in
the driver to support this feature. Besides, it does not work for sub-pages
and many drivers have it broken. It hurts more than it provides benefits."
Wolfram Sang [Sat, 11 Aug 2012 08:58:43 +0000 (10:58 +0200)]
mtd: maps: pci: remove dead code
Removes disabled printk (which should be dev_dbg these days) as well
as #if 0 blocks (which are trivial to reimplement if ever needed) to
meet basic CodingStyle guidelines.
Signed-off-by: Wolfram Sang <w.sang@pengutronix.de> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Artem Bityutskiy [Thu, 23 Aug 2012 07:10:07 +0000 (10:10 +0300)]
JFFS2: fix unmount regression
This patch fixes regression introduced by
"8bdc81c jffs2: get rid of jffs2_sync_super". We submit a delayed work in order
to make sure the write-buffer is synchronized at some point. But we do not
flush it when we unmount, which causes an oops when we unmount the file-system
and then the delayed work is executed.
This patch fixes the issue by adding a "cancel_delayed_work_sync()" infocation
in the '->sync_fs()' handler. This will make sure the delayed work is canceled
on sync, unmount and re-mount. And because VFS always callse 'sync_fs()' before
unmounting or remounting, this fixes the issue.
mtd: allow uclinux map driver to be used on any ColdFire CPU platform
The uclinux.c map driver has traditionally been used only on non-MMU based
systems. But there is no fundamental reason it can't be used on systems
running with virtual memory.
Some ColdFire CPU based systems now have full paged MMU hardware and can use
the uclinux.c mapping driver, so making the uclinux.c driver configuration
depend on !CONFIG_MMU doesn't make sense now. Allow the CONFIG_MTD_UCLINUX
option to be enabled if CONFIG_COLDFIRE is enabled. (I have chosen not to
just more generally allow uclinux.c for any MMU type to keep this option
hidden for most systems that are not interested in setting it).
mtd: fix wrong usage of ioremap_nocache() in uclinux.c map driver
The uclinux.c mapping driver uses ioremap_nocache() to map its physical
mapping address to a system virtual address. Problem is that the region
it is mapping is not device memory. It is ordinary system RAM. On most
non-MMU systems this doesn't matter, and the mapping is always a 1:1
translation of the address. On paged memory systems on some architectures
the page table mappings are not compatible between normal RAM and device
memory.
If we want to use the uclinux.c mapping driver on real MMU enabled systems
we should be using the kernel virtual address that the mapping is at. For
architectures that support the traditional initrd they use phys_to_virt or
__va to convert the physical start initrd address to a kernel usable virtual
address. The uclinux filesystem mapping is even more restrictive than the
typical initrd, it always follows the kernels own bss section (so always in
directly mapped memory). Therefore we can use the usual phys_to_virt to
translate the physical start address to a virtual address.
Alexander Shiyan [Wed, 15 Aug 2012 16:28:06 +0000 (20:28 +0400)]
mtd: autcpu12-nvram: Convert driver to platform_device
Because we can have a single kernel to support multiple machines, we
need to make loading specific drivers for the target platform only.
For this, driver is converted to the platform driver.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Alexander Shiyan [Wed, 15 Aug 2012 16:28:05 +0000 (20:28 +0400)]
mtd: autcpu12-nvram: Fix compile breakage
Update driver autcpu12-nvram.c so it compiles; map_read32/map_write32
no longer exist in the kernel so the driver is totally broken.
Additionally, map_info name passed to simple_map_init is incorrect.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Acked-by: Arnd Bergmann <arnd@arndb.de> Cc: stable@vger.kernel.org Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Brian Norris [Fri, 13 Jul 2012 16:28:24 +0000 (09:28 -0700)]
mtd: nand: allow NAND_NO_SUBPAGE_WRITE to be set from driver
The NAND_CHIPOPTIONS_MSK has limited utility and is causing real bugs. It
silently masks off at least one flag that might be set by the driver
(NAND_NO_SUBPAGE_WRITE). This breaks the GPMI NAND driver and possibly
others.
Really, as long as driver writers exercise a small amount of care with
NAND_* options, this mask is not necessary at all; it was only here to
prevent certain options from accidentally being set by the driver. But the
original thought turns out to be a bad idea occasionally. Thus, kill it.
Note, this patch fixes some major gpmi-nand breakage.
Signed-off-by: Brian Norris <computersforpeace@gmail.com> Tested-by: Huang Shijie <shijie8@gmail.com> Cc: stable@vger.kernel.org Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Mike Dunn [Wed, 11 Jul 2012 18:08:19 +0000 (11:08 -0700)]
mtd: docg4: fix oob reads
This patch does two closely related things:
(1) Currently the ecc.read_page() method does not fill the nand->oob_poi buffer
with the oob data, but instead reads oob into a local buffer. Fix this by
filling the oob_poi buffer instead of a local buffer. The 'oob_required'
argument is quietly ignored; the device must always read oob after the page
data, and it is presumed that there's no harm in filling oob_poi, even when not
explicitly requested.
(2) Always read oob from the device in ecc.read_oob(), instead of copying it
from a local buffer under some circumstances.
Signed-off-by: Mike Dunn <mikedunn@newsguy.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Artem Bityutskiy [Fri, 17 Aug 2012 10:05:41 +0000 (13:05 +0300)]
mtd: spear_smi: fix compilation warning
drivers/mtd/devices/spear_smi.c: In function 'spear_smi_probe':
drivers/mtd/devices/spear_smi.c:984:2: warning: comparison of unsigned expression < 0 is always false [-Wtype-limits]
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Brian Norris [Fri, 22 Jun 2012 23:35:42 +0000 (16:35 -0700)]
mtd: nand: rename '_raw' BBT scan functions
None of these scanning functions use MTD_OPS_RAW mode any more, so there's
really nothing 'raw' about them. Rename them to (hopefully) make the code
a little clearer.
Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Brian Norris [Fri, 22 Jun 2012 23:35:45 +0000 (16:35 -0700)]
mtd: nand: use ECC, if present, when scanning OOB
scan_read_raw_oob() is used in only in places where the MTD_OPS_PLACE_OOB mode
is preferable to MTD_OPS_RAW mode, so use MTD_OPS_PLACE_OOB instead.
MTD_OPS_PLACE_OOB provides the same functionality with the potential[1] added
bonus of error correction.
This brings scan_block_full() in line with scan_block_fast() so that they
both read bad block markers with MTD_OPS_PLACE_OOB. This can help in
preventing 0xff markers (in good blocks) from being interpreted as bad
block indicators in the presence of a single bitflip.
Note that ECC error codes (EUCLEAN or EBADMSG) are already silently
ignored in all users of scan_read_raw_oob().
[1] Few drivers perform proper error correction on OOB data. In those
cases, the use of MTD_OPS_RAW vs. MTD_OPS_PLACE_OOB is not
significant.
Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Brian Norris [Fri, 22 Jun 2012 23:35:39 +0000 (16:35 -0700)]
mtd: check for max_bitflips in mtd_read_oob()
mtd_read_oob() has some unexpected similarities to mtd_read(). For
instance, when ops->datbuf != NULL, nand_base.c might return max_bitflips;
however, when ops->datbuf == NULL, nand_base's code potentially could
return -EUCLEAN (no in-tree drivers do this yet). In any case where the
driver might return max_bitflips, we should translate this into an
appropriate return code using the bitflip_threshold.
Essentially, mtd_read_oob() duplicates the logic from mtd_read().
This prevents users of mtd_read_oob() from receiving a positive return
value (i.e., from max_bitflips) and interpreting it as an unknown error.
Artem: amend comments.
Signed-off-by: Brian Norris <computersforpeace@gmail.com> Reviewed-by: Mike Dunn <mikedunn@newsguy.com> Reviewed-by: Shmulik Ladkani <shmulik.ladkani@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
The gpmi nand driver may needs several clocks(MX6Q needs five clocks).
In the old clock framework, all these clocks are chained together,
all you need is to manipulate the first clock.
But the kernel uses the common clk framework now, which forces us to
get the clocks one by one. When we use them, we have to enable them
one by one too.
projects / linux-beck.git / log