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9 years agoMIPS: Respect the ISA level in FCSR handling
Maciej W. Rozycki [Fri, 3 Apr 2015 22:27:48 +0000 (23:27 +0100)]
MIPS: Respect the ISA level in FCSR handling

Define the central place the default FCSR value is set from, initialised
in `cpu_probe'.  Determine the FCSR mask applied to values written to
the register with CTC1 in the full emulation mode and via ptrace(2),
according to the ISA level of processor hardware or the writability of
bits 31:18 if actual FPU hardware is used.

Software may rely on FCSR bits whose functions our emulator does not
implement, so it should not allow them to be set or software may get
confused.  For ptrace(2) it's just sanity.

[ralf@linux-mips.org: Fixed double inclusion of <asm/current.h>.]

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9711/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: math-emu: Make ABS.fmt and NEG.fmt arithmetic again
Maciej W. Rozycki [Fri, 3 Apr 2015 22:27:43 +0000 (23:27 +0100)]
MIPS: math-emu: Make ABS.fmt and NEG.fmt arithmetic again

The ABS.fmt and NEG.fmt instructions have been specified as arithmetic
in the MIPS architecture, which in particular implies handling NaN data
in the usual way with qNaN bit patterns propagated unchanged and sNaN
bit patterns signalling the usual IEEE 754 Invalid Operation exception
and quieted by default.

A series of changes applied over time to our implementation:

c5033d78 [MIPS] ieee754[sd]p_neg workaround
cea2be44 MIPS: Fix abs.[sd] and neg.[sd] emulation for NaN operands

has led to the current situation where the sign bit is updated according
to the operation requested even for NaN inputs.  This is according to
these commits a workaround so that broken binaries produced by GCC
disregarding the properties of these instructions have a chance to work.

For sNaN inputs this remains within IEEE Std 754 as the standard leaves
the choice of output qNaN bit patterns produced under the default
Invalid Operation exception handling for individual sNaN input bit
patterns to implementer's discretion, even though it still recommends as
much NaN input information to be preserved in NaN outputs.

For qNaN inputs however it violates the standard as it requires a qNaN
input bit patterns to propagate unchanged to output.

This is also unlike real MIPS FPU hardware behaves where sNaN and/or
qNaN processing has been fully implemented with no Unimplemented
Operation exception signalled.  Such hardware propagates any input qNaN
bit pattern unchanged.  It also quiets any input sNaN bit pattern in an
implementer-specific manner, for example the MIPS 74Kf processor returns
the default qNaN pattern with the sign bit always clear and the Broadcom
SB-1 and BMIPS5000 processors propagate the input sNaN bit pattern with
the sign bit unchanged and the quiet bit first cleared in the trailing
significand field and then the next lower bit set if clearing the quiet
bit left the field with no other bit set.

Especially the latter observation indicates the limited usefulness of
the workaround as it will cover many hardware configurations, but not
all of them, only making it harder to discover such broken binaries that
need to be recompiled with GCC told to avoid the use of ABS.fmt and
NEG.fmt instructions where non-arithmetic semantics is required by the
algorithm used.

Revert the damage done by the series of changes then, and take the
opportunity to simplify implementation by calling `ieee754dp_sub' and
`ieee754dp_add' as required and also the rounding mode set towards -Inf
temporarily so that the sign of 0 is correctly handled.

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9710/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: math-emu: Define IEEE 754-2008 feature control bits
Maciej W. Rozycki [Fri, 3 Apr 2015 22:27:38 +0000 (23:27 +0100)]
MIPS: math-emu: Define IEEE 754-2008 feature control bits

Define IEEE 754-2008 feature control bits: FIR.HAS2008, FCSR.ABS2008 and
FCSR.NAN2008, and update the `_ieee754_csr' structure accordingly.

For completeness define FIR.UFRP too.

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9709/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: math-emu: Implement the FCCR, FEXR and FENR registers
Maciej W. Rozycki [Fri, 3 Apr 2015 22:27:33 +0000 (23:27 +0100)]
MIPS: math-emu: Implement the FCCR, FEXR and FENR registers

Implement the FCCR, FEXR and FENR "shadow" FPU registers for the
architecture levels that include them, for the CFC1 and CTC1
instructions in the full emulation mode.

For completeness add macros for the CP1 UFR and UNFR registers too, no
actual implementation though.

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9708/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: math-emu: Set FIR feature flags for full emulation
Maciej W. Rozycki [Fri, 3 Apr 2015 22:27:26 +0000 (23:27 +0100)]
MIPS: math-emu: Set FIR feature flags for full emulation

Implement FIR feature flags in the FPU emulator according to features
supported and architecture level requirements.  The W, L and F64 bits
have only been added at level #2 even though the features they refer to
were also included with the MIPS64r1 ISA and the W fixed-point format
also with the MIPS32r1 ISA.

This is only relevant for the full emulation mode and the emulated CFC1
instruction as well as ptrace(2) accesses.

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9707/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: Correct ISA masking in FPU feature determination
Maciej W. Rozycki [Fri, 3 Apr 2015 22:27:21 +0000 (23:27 +0100)]
MIPS: Correct ISA masking in FPU feature determination

Correct an ISA level determination problem introduced with 8b8aa636
[MIPS: kernel: cpu-probe.c: Add support for MIPS R6], reverting explicit
masking against individual `MIPS_CPU_ISA_*' macros in FPU feature
determination.

Feature macros such as `cpu_has_mips_r' cannot be used here, because
they operate on CPU #0 and we want to refer to the current CPU instead.
They cannot be used for masking against the current CPU either because
they mask against CPU #0 too, e.g.:

# define cpu_has_mips32r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1)

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9706/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: Set `si_code' for SIGFPE signals sent from emulation too
Maciej W. Rozycki [Fri, 3 Apr 2015 22:27:15 +0000 (23:27 +0100)]
MIPS: Set `si_code' for SIGFPE signals sent from emulation too

Rework `process_fpemu_return' and move IEEE 754 exception interpretation
there, from `do_fpe'.  Record the cause bits set in FCSR before they are
cleared and pass them through to `process_fpemu_return' so as to set
`si_code' correctly too for SIGFPE signals sent from emulation rather
than those issued by hardware with the FPE processor exception only.

For simplicity `mipsr2_decoder' assumes `*fcr31' has been preinitialised
and only sets it to anything if an FPU instruction has been emulated,
which in turn is the only case SIGFPE can be issued for here.

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9705/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: Always clear FCSR cause bits after emulation
Maciej W. Rozycki [Fri, 3 Apr 2015 22:27:10 +0000 (23:27 +0100)]
MIPS: Always clear FCSR cause bits after emulation

Clear any FCSR cause bits recorded in the saved FPU context after
emulation in all cases rather than in `do_fpe' only, so that any
unmasked IEEE 754 exception left from emulation does not cause a fatal
kernel-mode FPE hardware exception with the CTC1 instruction used by the
kernel to subsequently restore FCSR hardware from the saved FPU context.

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9704/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: Respect the FCSR exception mask for `si_code'
Maciej W. Rozycki [Fri, 3 Apr 2015 22:27:06 +0000 (23:27 +0100)]
MIPS: Respect the FCSR exception mask for `si_code'

Respect the FCSR exception mask when interpreting the IEEE 754 exception
condition to report with SIGFPE in `si_code', so as not to use one that
has been masked where a different one set in parallel caused the FPE
hardware exception to trigger.  As per the IEEE Std 754 the Inexact
exception can happen together with Overflow or Underflow.

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9703/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: math-emu: Move long fixed-point support into an `ar' library
Maciej W. Rozycki [Fri, 3 Apr 2015 22:27:01 +0000 (23:27 +0100)]
MIPS: math-emu: Move long fixed-point support into an `ar' library

Complement 593d33fe [MIPS: math-emu: Move various objects into an ar
library.] and also move sp_tlong.o, sp_flong.o, dp_tlong.o, and
dp_flong.o into an `ar' library.  These objects implement long
fixed-point format support that can be omitted from MIPS I, MIPS II and
MIPS32r1 configurations.

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9702/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: math-emu: Correct delay-slot exception propagation
Maciej W. Rozycki [Fri, 3 Apr 2015 22:26:56 +0000 (23:26 +0100)]
MIPS: math-emu: Correct delay-slot exception propagation

Restore EPC at the branch whose delay slot is emulated if the delay-slot
instruction signals.  This is so that code in `fpu_emulator_cop1Handler'
does not see EPC having advanced and mistakenly successfully resume
userland execution from the location at the branch target in that case.
Restoring EPC guarantees an immediate exit from the emulation loop and
if EPC hasn't advanced at all since entering the loop, also issuing the
signal reported by the delay-slot instruction.

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9701/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: Correct FP ISA requirements
Maciej W. Rozycki [Fri, 3 Apr 2015 22:26:49 +0000 (23:26 +0100)]
MIPS: Correct FP ISA requirements

Correct ISA requirements for floating-point instructions:

* the CU3 exception signifies a real COP3 instruction in MIPS I & II,

* the BC1FL and BC1TL instructions are not supported in MIPS I,

* the SQRT.fmt instructions are indeed supported in MIPS II,

* the LDC1 and SDC1 instructions are indeed supported in MIPS32r1,

* the CEIL.W.fmt, FLOOR.W.fmt, ROUND.W.fmt and TRUNC.W.fmt instructions
  are indeed supported in MIPS32,

* the CVT.L.fmt and CVT.fmt.L instructions are indeed supported in
  MIPS32r2 and MIPS32r6,

* the CEIL.L.fmt, FLOOR.L.fmt, ROUND.L.fmt and TRUNC.L.fmt instructions
  are indeed supported in MIPS32r2 and MIPS32r6,

* the RSQRT.fmt and RECIP.fmt instructions are indeed supported in
  MIPS64r1,

Also simplify conditionals for MIPS III and MIPS IV FPU instructions and
the handling of the MOVCI minor opcode.

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9700/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: Correct MIPS I FP context layout
Maciej W. Rozycki [Fri, 3 Apr 2015 22:26:44 +0000 (23:26 +0100)]
MIPS: Correct MIPS I FP context layout

Implement the correct ordering of individual floating-point registers
within double-precision register pairs for the MIPS I FP context, as
required by our FP emulation code and expected by userland talking via
ptrace(2).  Use L.D and S.D assembly macros that do the right thing like
LDC1 and SDC1 from MIPS II up, avoiding the need to mess up with
endianness conditionals.

This in particular fixes the handling of denormals and NaN generation in
Unimplemented Operation emulation traps.

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9699/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: math-emu: Fix delay-slot emulation cache incoherency
Maciej W. Rozycki [Fri, 3 Apr 2015 22:26:37 +0000 (23:26 +0100)]
MIPS: math-emu: Fix delay-slot emulation cache incoherency

Correct a cache coherency regression introduced with be1664c4 [Another
round of fixes for the fp emulator.] for the emulation frame used in
delay-slot emulation.

Two instructions are copied into the frame and as from the commit
referred a cache synchronisation call is made for the second instruction
aka `badinst' of the two only.  The `flush_cache_sigtramp' interface is
reused that guarantees that synchronisation will be made for 8 bytes or
2 instructions starting from the address requested, although if cache
lines are wider then a larger area may be synchronised.

Change the call to point to the first of the two instructions aka `emul'
instead, removing unpredictable behaviour resulting from cache
incoherency.

This bug only ever manifested itself on systems implementing 4-byte
cache lines, typically MIPS I systems, causing all kinds of weirdness.
This is because the sequence of two instructions starting from `emul' is
8-byte aligned and for 8-byte or wider cache lines the line synchronised
will span both, so the vast majority of systems have escaped unharmed.

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9698/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: Fix BREAK code interpretation heuristics
Maciej W. Rozycki [Fri, 3 Apr 2015 22:26:32 +0000 (23:26 +0100)]
MIPS: Fix BREAK code interpretation heuristics

Do not lose the other half of the BREAK code where there is an upper
half.  This is so that e.g. `BREAK 7, 7' is not interpreted as a divide
by zero trap, while `BREAK 0, 7' or `BREAK 7, 0' still are.

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9697/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: BREAK instruction interpretation corrections
Maciej W. Rozycki [Fri, 3 Apr 2015 22:26:27 +0000 (23:26 +0100)]
MIPS: BREAK instruction interpretation corrections

Add the missing microMIPS BREAK16 instruction code interpretation and
reshape code removing instruction fetching duplication and the separate
call to `do_trap_or_bp' in the MIPS16 path.

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9696/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: Correct MIPS16 BREAK code interpretation
Maciej W. Rozycki [Fri, 3 Apr 2015 22:26:21 +0000 (23:26 +0100)]
MIPS: Correct MIPS16 BREAK code interpretation

Correct the interpretation of the immediate MIPS16 BREAK instruction
code embedded in the instruction word across bits 10:5 rather than 11:6
as current code implies, fixing the interpretation of integer overflow
and divide by zero traps.

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9695/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: Correct `nofpu' non-functionality
Maciej W. Rozycki [Fri, 3 Apr 2015 22:26:04 +0000 (23:26 +0100)]
MIPS: Correct `nofpu' non-functionality

The `cpu_has_fpu' feature flag must not be hardcoded to 1 or the `nofpu'
kernel option will be ignored.  Remove any such overrides and add a
cautionary note.  Hardcoding to 0 is fine for FPU-less platforms.

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9694/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: math-emu: Make NaN classifiers static
Maciej W. Rozycki [Fri, 3 Apr 2015 22:25:57 +0000 (23:25 +0100)]
MIPS: math-emu: Make NaN classifiers static

The `ieee754sp_isnan' and `ieee754dp_isnan' NaN classifiers are now no
longer externally referred, remove their header prototypes and make them
local to the two only respective places still making use of them.

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9693/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: math-emu: Optimise qNaN handling in `ieee754sp_fdp'
Maciej W. Rozycki [Fri, 3 Apr 2015 22:25:52 +0000 (23:25 +0100)]
MIPS: math-emu: Optimise qNaN handling in `ieee754sp_fdp'

Rewrite qNaN handling in `ieee754sp_fdp' using the `ieee754_class_nan'
helper recently added, removing the external call to `ieee754sp_isnan'
and reducing the size of code by 16 instructions or 64 bytes.

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9692/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: math-emu: Remove dead comparison helpers
Maciej W. Rozycki [Fri, 3 Apr 2015 22:25:48 +0000 (23:25 +0100)]
MIPS: math-emu: Remove dead comparison helpers

None of the comparison helpers in ieee754.h is used, remove them.

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9691/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: math-emu: Remove redundant code from NaN comparison
Maciej W. Rozycki [Fri, 3 Apr 2015 22:25:43 +0000 (23:25 +0100)]
MIPS: math-emu: Remove redundant code from NaN comparison

Remove a redundant call to `ieee754_setandtestcx' in `ieee754sp_cmp' and
`ieee754dp_cmp'.  The IEEE 754 exception requested will have already
been set by a call to `ieee754_setcx' immediately above, because `sig'
has to be non-zero to reach here, and the comparison result returned
will be 0 regardless of the result from the call.  Simplify the return
expression remaining.  All this reducing the size of code by 16 and 12
instructions or 64 and 48 bytes respectively.

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9690/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: math-emu: Optimise NaN handling in comparisons
Maciej W. Rozycki [Fri, 3 Apr 2015 22:25:38 +0000 (23:25 +0100)]
MIPS: math-emu: Optimise NaN handling in comparisons

We have the input operands already classified in `ieee754sp_cmp' and
`ieee754dp_cmp' comparison operations, so use the class obtained to tell
NaNs and numbers apart rather than classifying inputs again for this
purpose, reducing the size of code by 24 and 40 instructions or 96 and
160 bytes respectively.

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9689/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: math-emu: Reinstate sNaN quieting handlers
Maciej W. Rozycki [Fri, 3 Apr 2015 22:25:34 +0000 (23:25 +0100)]
MIPS: math-emu: Reinstate sNaN quieting handlers

Revert the changes made by commit fdffbafb [Lots of FPU bug fixes from
Kjeld Borch Egevang.] to `ieee754sp_nanxcpt' and `ieee754dp_nanxcpt'
sNaN quieting handlers and their callers so that sNaN processing is done
within the handlers againg.  Pass the sNaN causing an IEEE 754 invalid
operation exception down to the relevant handler.  Pass the sNaN in `fs'
where two sNaNs are supplied to a binary operation.

Set the Invalid Operation FCSR exception bits in the quieting handlers
rather than at their call sites throughout.  Make the handlers exclusive
for sNaN processing.

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9688/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: math-emu: Don't pass qNaNs through quieting handlers
Maciej W. Rozycki [Fri, 3 Apr 2015 22:25:30 +0000 (23:25 +0100)]
MIPS: math-emu: Don't pass qNaNs through quieting handlers

Don't call the `ieee754sp_nanxcpt' and `ieee754dp_nanxcpt' sNaN quieting
handlers for a qNaN supplied to floating-point format conversions or
SQRT.S/SQRT.D instructions, or for a qNaN produced out of a negative
operand supplied to SQRT.S/SQRT.D instructions.  Return the qNaN right
away in these cases.

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9687/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: math-emu: Factor out NaN FP format conversions
Maciej W. Rozycki [Fri, 3 Apr 2015 22:25:23 +0000 (23:25 +0100)]
MIPS: math-emu: Factor out NaN FP format conversions

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9686/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: math-emu: Update sNaN quieting handlers
Maciej W. Rozycki [Fri, 3 Apr 2015 22:25:18 +0000 (23:25 +0100)]
MIPS: math-emu: Update sNaN quieting handlers

Commit fdffbafb [Lots of FPU bug fixes from Kjeld Borch Egevang.]
replaced the two single `ieee754sp_nanxcpt' and `ieee754dp_nanxcpt'
places, where sNaN quieting used to happen for single and double
floating-point operations respectively, with individual qNaN
instantiations across all the call sites instead.  It also made most of
these two functions dead code as where called on a qNaN they return
right away.

To revert the damage and make sNaN quieting uniform again first rewrite
`ieee754sp_nanxcpt' and `ieee754dp_nanxcpt' to do the same quieting all
the call sites do, that is return the default qNaN encoding for all
input sNaN values; never propagate any sNaN payload bits from its
trailing significand field.

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9685/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: Use `FPU_CSR_ALL_X' in `__build_clear_fpe'
Maciej W. Rozycki [Fri, 3 Apr 2015 22:25:14 +0000 (23:25 +0100)]
MIPS: Use `FPU_CSR_ALL_X' in `__build_clear_fpe'

Replace a hardcoded numeric bitmask for FCSR cause bits with
`FPU_CSR_ALL_X' in `__build_clear_fpe'.

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9684/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: Normalise code flow in the CpU exception handler
Maciej W. Rozycki [Fri, 3 Apr 2015 22:25:08 +0000 (23:25 +0100)]
MIPS: Normalise code flow in the CpU exception handler

Changes applied to `do_cpu' over time reduced the use of the SIGILL
issued with `force_sig' at the end to a single CU3 case only in the
switch statement there.  Move that `force_sig' call over to right where
required then and toss out the pile of gotos now not needed to skip over
the call, replacing them with regular breaks out of the switch.

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9683/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: math-emu: Factor out CFC1/CTC1 emulation
Maciej W. Rozycki [Fri, 3 Apr 2015 22:25:04 +0000 (23:25 +0100)]
MIPS: math-emu: Factor out CFC1/CTC1 emulation

Move CFC1/CTC1 emulation code to separate functions to avoid excessive
indentation in forthcoming changes.  Adjust formatting in a minor way
and remove extraneous round brackets.

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9682/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: bitops.h: Avoid inline asm for constant FLS
Maciej W. Rozycki [Fri, 3 Apr 2015 22:25:00 +0000 (23:25 +0100)]
MIPS: bitops.h: Avoid inline asm for constant FLS

GCC is smart enough to substitute the final result for FLS calculations
as implemented in the fallback C code we have in `__fls' and `fls'
applied to constant values.  The presence of inline asm defeats the
compiler though, forcing it to emit extraneous CLZ/DCLZ calculation for
processors that support these instructions.

Use `__builtin_constant_p' then to avoid inline asm altogether for
constants.

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9681/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: math-emu: Remove `modeindex' macro
Maciej W. Rozycki [Fri, 3 Apr 2015 22:24:56 +0000 (23:24 +0100)]
MIPS: math-emu: Remove `modeindex' macro

Commit 56a64733 [MIPS: math-emu: Switch to using the MIPS rounding
modes.] removed the distinction between hardware and emulator rounding
mode encodings, the hardware encoding is now used in emulation as well.
Complement the change and remove the `modeindex' macro previously used
for indexing into encoding translation tables, it now does nothing and
only obfuscates code by reinserting the value extracted from FCSR.
Adjust comments accordingly.

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9680/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: Reindent R6 RI exception emulation
Maciej W. Rozycki [Fri, 3 Apr 2015 22:24:51 +0000 (23:24 +0100)]
MIPS: Reindent R6 RI exception emulation

Fold a nested `if' statement for the R6 case in `do_ri' into its
containing `if' block, removing excessive indentation causing code to
extend beyond 79 columns.

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9679/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: mips-r2-to-r6-emul.h: Inline empty `mipsr2_decoder'
Maciej W. Rozycki [Fri, 3 Apr 2015 22:24:46 +0000 (23:24 +0100)]
MIPS: mips-r2-to-r6-emul.h: Inline empty `mipsr2_decoder'

Use `static inline' rather than `static __maybe_unused' for
`mipsr2_decoder' in the empty case, making inlining explicit where it
will happen anyway.

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9678/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: ELF: Drop `get_fp_abi'
Maciej W. Rozycki [Fri, 3 Apr 2015 22:24:41 +0000 (23:24 +0100)]
MIPS: ELF: Drop `get_fp_abi'

Commit 46490b57 [MIPS: kernel: elf: Improve the overall ABI and FPU mode
checks] reduced `get_fp_abi' to an elaborate pass-through.  Drop it
then.

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9677/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: math-emu: Fix oversize lines in comparisons
Maciej W. Rozycki [Fri, 3 Apr 2015 22:24:35 +0000 (23:24 +0100)]
MIPS: math-emu: Fix oversize lines in comparisons

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9676/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: Correct the comment for and reformat `movf_func'
Maciej W. Rozycki [Fri, 3 Apr 2015 22:24:29 +0000 (23:24 +0100)]
MIPS: Correct the comment for and reformat `movf_func'

Correct a copy-and-paste issue with the description for `movf_func'
referring to `movt_func'.  Reformat the former function to match the
latter.

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9675/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: math-emu: Reindent `bc_op' emulation
Maciej W. Rozycki [Fri, 3 Apr 2015 22:24:24 +0000 (23:24 +0100)]
MIPS: math-emu: Reindent `bc_op' emulation

Correct the double-tab indentation of the branch-likely not-taken case.

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9674/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: Clarify the comment for `__cpu_has_fpu'
Maciej W. Rozycki [Fri, 3 Apr 2015 22:24:18 +0000 (23:24 +0100)]
MIPS: Clarify the comment for `__cpu_has_fpu'

Reword the comment for `__cpu_has_fpu' to make it unambiguous this code
is for external floating-point units only, generally MIPS I processors
using the original CP1 hardware interface.

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9673/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: Correct the comment for FPU emulator traps
Maciej W. Rozycki [Fri, 3 Apr 2015 22:24:14 +0000 (23:24 +0100)]
MIPS: Correct the comment for FPU emulator traps

Adjust the explanatory comment for FPU emulator traps according to
ba3049ed [MIPS: Switch FPU emulator trap to BREAK instruction.];
originally coming from `do_ade'.

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9672/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: ieee754.h: Supplement comments for special values
Maciej W. Rozycki [Fri, 3 Apr 2015 22:24:09 +0000 (23:24 +0100)]
MIPS: ieee754.h: Supplement comments for special values

Add the remaining missing comments for IEEE 754 special value array
indices.  Reindent macro definitions for consistency.

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9671/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: ieee754.h: Correct comments for special values
Maciej W. Rozycki [Fri, 3 Apr 2015 22:24:01 +0000 (23:24 +0100)]
MIPS: ieee754.h: Correct comments for special values

IEEE754_SPCVAL_NMIN denotes the index into the special value array where
the closest to zero negative normal number expressible is stored.
Similarly IEEE754_SPCVAL_NMIND denotes such index for the closest to
zero negative subnormal number expressible.  Make comments match that.

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9670/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: mipsregs.h: Reindent CP0 Cause macros
Maciej W. Rozycki [Fri, 3 Apr 2015 22:23:56 +0000 (23:23 +0100)]
MIPS: mipsregs.h: Reindent CP0 Cause macros

Reindent CP0 Cause macros for a single space after #define, leaving
extra indentation for individual Interrupt Pending bits as with CP0
Status register's Interrupt Mask bits.

[ralf@linux-mips.org: Fix conflict.]
[ralf@linux-mips.org: Fix indentation of the CAUSEB_FDCI and CAUSEF_FDCI
definitions.]

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9669/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: mipsregs.h: Move TX39 macros out of the way
Maciej W. Rozycki [Fri, 3 Apr 2015 22:23:50 +0000 (23:23 +0100)]
MIPS: mipsregs.h: Move TX39 macros out of the way

TX39 CP0 Configuration Register 3 macro definitions have been randomly
thrown in the middle of a block of CP0 Status register value macros.
Move them to the end of the whole CP0 register value macro block,
complementing the location of the TX39 Cache register name macro at the
end of the CP0 register name macro block.

[ralf@linux-mips.org: Fix conflict.]

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9668/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: mipsregs.h: Reorder CP1 macro definitions
Maciej W. Rozycki [Fri, 3 Apr 2015 22:23:46 +0000 (23:23 +0100)]
MIPS: mipsregs.h: Reorder CP1 macro definitions

Originally CP1 macros were placed between CP0 register name macros and
CP0 register value macros.  As changes were applied to the header the
position of CP1 macros gradually has become more and more arbitrary and
two separate blocks were created.  This may only cause confusion.

Move them out of the way then and place together after all the CP0
macros.  No semantic change.

[ralf@linux-mips.org: Fix conflict.]

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9667/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: mipsregs.h: Remove broken comments
Maciej W. Rozycki [Fri, 3 Apr 2015 22:23:41 +0000 (23:23 +0100)]
MIPS: mipsregs.h: Remove broken comments

Remove a duplicate FPU Status Register reference that has been there
since forever and a mistakenly copied and pasted R4xx0 manual reference.

[ralf@linux-mips.org: Fix conflict.]

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9666/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoDOC: kernel-parameters.txt: Mark `nofpu' for MIPS too
Maciej W. Rozycki [Fri, 3 Apr 2015 22:23:34 +0000 (23:23 +0100)]
DOC: kernel-parameters.txt: Mark `nofpu' for MIPS too

The MIPS port has supported this option since forever, long before SH
was even in plans.

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9665/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: SEAD3: Combine all platform device registrations in one file.
Ralf Baechle [Thu, 2 Apr 2015 15:07:26 +0000 (17:07 +0200)]
MIPS: SEAD3: Combine all platform device registrations in one file.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: SEAD3: Make static in sead3-ehci what can be made static.
Ralf Baechle [Thu, 2 Apr 2015 14:37:00 +0000 (16:37 +0200)]
MIPS: SEAD3: Make static in sead3-ehci what can be made static.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: SEAD3: sead3-ehci should not be a module.
Ralf Baechle [Thu, 2 Apr 2015 14:26:32 +0000 (16:26 +0200)]
MIPS: SEAD3: sead3-ehci should not be a module.

So let's remove everythig that only make sense for a kernel module and
build the thing unconditionally.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: SEAD3: sead3-platform is not a module.
Ralf Baechle [Thu, 2 Apr 2015 14:20:04 +0000 (16:20 +0200)]
MIPS: SEAD3: sead3-platform is not a module.

So let's remove everything that only makes sense for kernel modules.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: SEAD3: sead3-net is not a module.
Ralf Baechle [Thu, 2 Apr 2015 14:19:29 +0000 (16:19 +0200)]
MIPS: SEAD3: sead3-net is not a module.

So let's remove everything that only makes sense for kernel modules.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: BCM47xx: Move filling most of SPROM to the generic function
Rafał Miłecki [Thu, 2 Apr 2015 10:30:24 +0000 (12:30 +0200)]
MIPS: BCM47xx: Move filling most of SPROM to the generic function

This simplifies code a lot by dropping many per-revision-group
functions. There are still some paths left that use uncommon NVRAM read
helpers or fill arrays. They will need to be handled in separated patch.

I've tested this (by printing SPROM content) for regressions on:
1) BCM4704 (SPROM revision 2)
2) BCM4706 (SPROM revision 8 plus 11 & 9 on extra WiFi cards)
The only difference is not reading board_type from SPROM rev 11 which is
unsupported and treated as rev 1. This change for rev 1 is expected.

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: Hauke Mehrtens <hauke@hauke-m.de>
Cc: Jonas Gorski <jonas.gorski@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/9660/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: BCM47xx: Add generic function filling SPROM entries
Rafał Miłecki [Thu, 2 Apr 2015 07:13:49 +0000 (09:13 +0200)]
MIPS: BCM47xx: Add generic function filling SPROM entries

Handling many SPROM revisions became messy, we have tons of functions
specific to various revision groups which are quite hard to track.
For years there is yet another revision 11 asking for support, but
adding it in current the form would make things even worse.
To resolve this problem let's add new function with table-like entries
that will contain revision bitmask for every SPROM variable.

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: Hauke Mehrtens <hauke@hauke-m.de>
Cc: Jonas Gorski <jonas.gorski@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/9659/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: Reduce kernel image size for !CONFIG_DEBUG_ZBOOT
Wu Zhangjin [Sat, 25 Dec 2010 15:11:49 +0000 (23:11 +0800)]
MIPS: Reduce kernel image size for !CONFIG_DEBUG_ZBOOT

!CONFIG_DEBUG_ZBOOT doesn't need puts() and puthex(), remove them and
the corrospindig strings for !CONFIG_DEBUG_ZBOOT, as a result, it saves
about 1280 bytes.

[ralf@linux-mips.org: Resolved reject.]

Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: Wu Zhangjin <wuzhangjin@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/1898/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: BCM47xx: Devices database update for 4.1 (or 4.2?)
Rafał Miłecki [Wed, 1 Apr 2015 16:18:02 +0000 (18:18 +0200)]
MIPS: BCM47xx: Devices database update for 4.1 (or 4.2?)

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: Hauke Mehrtens <hauke@hauke-m.de>
Patchwork: https://patchwork.linux-mips.org/patch/9656/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: BCM47xx: Keep ID entries for non-standard devices together
Rafał Miłecki [Wed, 1 Apr 2015 16:18:01 +0000 (18:18 +0200)]
MIPS: BCM47xx: Keep ID entries for non-standard devices together

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: Hauke Mehrtens <hauke@hauke-m.de>
Patchwork: https://patchwork.linux-mips.org/patch/9655/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: AR7: Replace mac address parsing
Daniel Walter [Tue, 24 Jun 2014 15:39:59 +0000 (16:39 +0100)]
MIPS: AR7: Replace mac address parsing

Replace sscanf() with mac_pton().

[ralf@linux-mips.org: Resolved conflict.]

Signed-off-by: Daniel Walter <dwalter@google.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/7151/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: Lasat: Remove unused function from sysctl code.
Rickard Strandqvist [Thu, 1 Jan 2015 16:48:23 +0000 (17:48 +0100)]
MIPS: Lasat: Remove unused function from sysctl code.

Remove the function proc_dolasatint() that is not used anywhere.

This was partially found by using a static code analysis program called cppcheck.

Signed-off-by: Rickard Strandqvist <rickard_strandqvist@spectrumdigital.se>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8868/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: BCM47XX: Don't try guessing NVRAM size on MTD partition
Rafał Miłecki [Wed, 1 Apr 2015 06:23:05 +0000 (08:23 +0200)]
MIPS: BCM47XX: Don't try guessing NVRAM size on MTD partition

When dealing with whole flash content (bcm47xx_nvram_init_from_mem) we
need to find NVRAM start trying various partition sizes (nvram_sizes).
This is not needed when using MTD as we have direct partition access.

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: Hauke Mehrtens <hauke@hauke-m.de>
Patchwork: https://patchwork.linux-mips.org/patch/9652/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: BCM47XX: Increase NVRAM buffer size to 64 KiB
Rafał Miłecki [Wed, 1 Apr 2015 06:23:04 +0000 (08:23 +0200)]
MIPS: BCM47XX: Increase NVRAM buffer size to 64 KiB

For years Broadcom devices use 64 KiB NVRAM partition size and some of
them indeed have it filled in more than 50%. This change allows reading
whole NVRAM e.g. on Netgear WNDR4500 and Netgear R8000.

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: Hauke Mehrtens <hauke@hauke-m.de>
Patchwork: https://patchwork.linux-mips.org/patch/9651/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: BCM47XX: Include io.h directly and fix brace indent
Rafał Miłecki [Wed, 1 Apr 2015 06:23:03 +0000 (08:23 +0200)]
MIPS: BCM47XX: Include io.h directly and fix brace indent

We use IO functions like readl & ioremap_nocache, so include linux/io.h

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: Hauke Mehrtens <hauke@hauke-m.de>
Patchwork: https://patchwork.linux-mips.org/patch/9650/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: c-r4k.c: Fix the 74K D-cache alias erratum workaround
Maciej W. Rozycki [Sun, 16 Nov 2014 01:02:29 +0000 (01:02 +0000)]
MIPS: c-r4k.c: Fix the 74K D-cache alias erratum workaround

Fix the 74K D-cache alias erratum workaround so that it actually works.
Our current code sets MIPS_CACHE_VTAG for the D-cache, but that flag
only has any effect for the I-cache.  Additionally MIPS_CACHE_PINDEX is
set for the D-cache if CP0.Config7.AR is also set for an affected
processor, leading to confusing information in the bootstrap log (the
flag isn't used beyond that).

So delete the setting of MIPS_CACHE_VTAG and rely on MIPS_CACHE_ALIASES,
set in a common place, removing I-cache coherency issues seen in GDB
testing with software breakpoints, gdbserver and ptrace(2), on affected
systems.

While at it add a little piece of explanation of what CP0.Config6.SYND
is so that people do not have to chase documentation.

Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8507/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: Remove prototype for copy_user_page
Guenter Roeck [Wed, 11 Feb 2015 21:27:19 +0000 (13:27 -0800)]
MIPS: Remove prototype for copy_user_page

MIPS architecture code does not provide copy_user_page,
so it should not provide a prototype for it either.

Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9266/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: Loongson-3: Add chipset ACPI platform driver
Huacai Chen [Sun, 29 Mar 2015 02:54:10 +0000 (10:54 +0800)]
MIPS: Loongson-3: Add chipset ACPI platform driver

This add south-bridge (SB700/SB710/SB800 chipset) ACPI platform driver
for Loongson-3. This will be used by EC (Embedded Controller, used by
laptops) driver and STR (Suspend To RAM).

[ralf@linux-mips.org: Fix build error if !CONFIG_CPU_LOONGSON3.  Build
doesn't like it if no obj-* variable is defined at all in a Makefile.
Obviously this has not been tested on other platforms.]

Signed-off-by: Huacai Chen <chenhc@lemote.com>
Cc: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/9619/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: Loongson-3: Add CPU Hwmon platform driver
Huacai Chen [Sun, 29 Mar 2015 02:54:09 +0000 (10:54 +0800)]
MIPS: Loongson-3: Add CPU Hwmon platform driver

This add CPU Hwmon (temperature sensor) platform driver for Loongson-3.

Signed-off-by: Huacai Chen <chenhc@lemote.com>
Cc: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/9617/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: perf: Add hardware perf events support for Loongson-3
Huacai Chen [Sun, 29 Mar 2015 02:54:08 +0000 (10:54 +0800)]
MIPS: perf: Add hardware perf events support for Loongson-3

This patch enable hardware performance counter support for Loongson-3's
perf events.

Signed-off-by: Huacai Chen <chenhc@lemote.com>
Cc: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/9618/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: PCI: Add a hook for IORESOURCE_BUS in pci_controller/bridge_controller
Joshua Kinard [Mon, 19 Jan 2015 09:19:20 +0000 (04:19 -0500)]
MIPS: PCI: Add a hook for IORESOURCE_BUS in pci_controller/bridge_controller

On SGI Origin 2k/Onyx2 and SGI Octane systems, there can exist multiple PCI
buses attached to the Xtalk bus.  The current code will stop counting PCI buses
after it finds the first one.  If one installs the optional PCI cardcage
("shoebox") into these systems, because of the order of the Xtalk widgets, the
current PCI code will find the cardcage first, and fail to detect the BaseIO
PCI devices, which are on a higher Xtalk widget ID.

This patch adds the hooks needed for resolving this issue in the IP27 PCI code
(in a later patch).

Verified on both an SGI Onyx2 and an SGI Octane.

Signed-off-by: Joshua Kinard <kumba@gentoo.org>
Cc: Linux MIPS List <linux-mips@linux-mips.org>
Patchwork: https://patchwork.linux-mips.org/patch/9074/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: Use bool function return values of true/false not 1/0
Joe Perches [Mon, 30 Mar 2015 23:46:03 +0000 (16:46 -0700)]
MIPS: Use bool function return values of true/false not 1/0

Use the normal return values for bool functions

Signed-off-by: Joe Perches <joe@perches.com>
Cc: linux-kernel@vger.kernel.org
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9640/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: Octeon: Fix to IP checksum offloading in Little Endian
Paul Martin [Mon, 30 Mar 2015 16:01:01 +0000 (17:01 +0100)]
MIPS: Octeon: Fix to IP checksum offloading in Little Endian

When hardware checksum generation is switched on the checksum
generation was only being signalled to the hardware correctly
in Big Endian mode.

Signed-off-by: Paul Martin <paul.martin@codethink.co.uk>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9634/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: Octeon: Make octeon-md5 driver endian-agnostic
Paul Martin [Mon, 30 Mar 2015 16:01:00 +0000 (17:01 +0100)]
MIPS: Octeon: Make octeon-md5 driver endian-agnostic

The octeon crypto co-processor expects values to be big endian.
Wrap the data transfers with cpu_to_be64() and be64_to_cpu()
transformations.

This passes for all the MD5 test vectors in crypto/testmgr.h

Signed-off-by: Paul Martin <paul.martin@codethink.co.uk>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9631/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: Octeon: Set up ethernet hardware for little endian
Paul Martin [Mon, 30 Mar 2015 16:00:59 +0000 (17:00 +0100)]
MIPS: Octeon: Set up ethernet hardware for little endian

Signed-off-by: Paul Martin <paul.martin@codethink.co.uk>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9635/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: Octeon: Reverse the order of register accesses to the FAU
Paul Martin [Mon, 30 Mar 2015 16:00:58 +0000 (17:00 +0100)]
MIPS: Octeon: Reverse the order of register accesses to the FAU

64 bit access is unaffected but for 32 bit access, swap high and
low words.  Similarly for 16 bit access, reverse the order of the
four possible words, and for 8 bit access reverse the order of byte
accesses.

Signed-off-by: Paul Martin <paul.martin@codethink.co.uk>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9630/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: Octeon: Set appropriate endianness in L2C registers
Paul Martin [Mon, 30 Mar 2015 16:00:57 +0000 (17:00 +0100)]
MIPS: Octeon: Set appropriate endianness in L2C registers

Signed-off-by: Paul Martin <paul.martin@codethink.co.uk>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9629/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: Octeon: Turn hardware bitfields and structures inside out.
Paul Martin [Mon, 30 Mar 2015 16:00:56 +0000 (17:00 +0100)]
MIPS: Octeon: Turn hardware bitfields and structures inside out.

Although the proper way to do this for bitfields would be to use
the macro that Ralf has provided, this is a little easier to
understand as a diff.

Signed-off-by: Paul Martin <paul.martin@codethink.co.uk>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9628/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: IP32: ip32-platform is not a module.
Ralf Baechle [Mon, 30 Mar 2015 21:02:51 +0000 (23:02 +0200)]
MIPS: IP32: ip32-platform is not a module.

So let's remove everything that only makes sense for kernel modules.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: Add R16000 detection
Joshua Kinard [Wed, 21 Jan 2015 12:59:45 +0000 (07:59 -0500)]
MIPS: Add R16000 detection

This allows the kernel to correctly detect an R16000 MIPS CPU on systems that
have those.  Otherwise, such systems will detect the CPU as an R14000, due to
similarities in the CPU PRId value.

Signed-off-by: Joshua Kinard <kumba@gentoo.org>
Cc: Linux MIPS List <linux-mips@linux-mips.org>
Patchwork: https://patchwork.linux-mips.org/patch/9092/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoCLOCKSOURCE: mips-gic: Allow GIC clock to be specified in device-tree
Andrew Bresticker [Tue, 24 Feb 2015 02:28:34 +0000 (18:28 -0800)]
CLOCKSOURCE: mips-gic: Allow GIC clock to be specified in device-tree

As an alternative to the "clock-frequency" property, allow the GIC
timer operating clock to be specified in the device-tree instead.
This is useful on systems which use common clock or where the GIC
is not fixed to a particular frequency and is instead, for example,
derived from the CPU clock.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Cc: James Hogan <james.hogan@imgtec.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: devicetree@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9309/

9 years agoMIPS: csum_partial: Improve instruction parallelism.
Chen Jie [Thu, 26 Mar 2015 17:07:24 +0000 (01:07 +0800)]
MIPS: csum_partial: Improve instruction parallelism.

Computing sum introduces true data dependency. This patch removes some
true data depdendencies, hence increases instruction level parallelism.

This patch brings up to 50% csum performance gain on Loongson 3a.

One example about how this patch works is in CSUM_BIGCHUNK1:
// ** original **    vs    ** patch applied **
    ADDC(sum, t0)           ADDC(t0, t1)
    ADDC(sum, t1)           ADDC(t2, t3)
    ADDC(sum, t2)           ADDC(sum, t0)
    ADDC(sum, t3)           ADDC(sum, t2)

In the original implementation, each ADDC(sum, ...) depends on the sum
value updated by previous ADDC(as source operand).

With this patch applied, the first two ADDC operations are independent,
hence can be executed simultaneously if possible.

Another example is in the "copy and sum calculating chunk":
// ** original **    vs    ** patch applied **
    STORE(t0, UNIT(0) ...   STORE(t0, UNIT(0) ...
    ADDC(sum, t0)           ADDC(t0, t1)
    STORE(t1, UNIT(1) ...   STORE(t1, UNIT(1) ...
    ADDC(sum, t1)           ADDC(sum, t0)
    STORE(t2, UNIT(2) ...   STORE(t2, UNIT(2) ...
    ADDC(sum, t2)           ADDC(t2, t3)
    STORE(t3, UNIT(3) ...   STORE(t3, UNIT(3) ...
    ADDC(sum, t3)           ADDC(sum, t2)

With this patch applied, ADDC and the **next next** ADDC are independent.

Signed-off-by: chenj <chenj@lemote.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9608/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: BCM47XX: Fix coding style to match kernel standards
Rafał Miłecki [Wed, 10 Dec 2014 16:38:26 +0000 (17:38 +0100)]
MIPS: BCM47XX: Fix coding style to match kernel standards

[ralf@linux-mips.org: Fixed conflicts.]

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Acked-by: Hauke Mehrtens <hauke@hauke-m.de>
Cc: linux-mips@linux-mips.org
Cc: Paul Walmsley <paul@pwsan.com>
Patchwork: https://patchwork.linux-mips.org/patch/8665/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: OCTEON: add GPIO LED support for DSR-1000N
Aaro Koskinen [Sun, 29 Mar 2015 21:04:56 +0000 (00:04 +0300)]
MIPS: OCTEON: add GPIO LED support for DSR-1000N

DSR-1000N board has two GPIO LEDs next to USB ports. Add support for them.

[ralf@linux-mips.org: Resolved conflict due to the moving of the DTS files
into vendor subdirectories.]

Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9624/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: Hibernate: Restructure files and functions
Huacai Chen [Sun, 29 Mar 2015 02:54:06 +0000 (10:54 +0800)]
MIPS: Hibernate: Restructure files and functions

This patch has no functional changes, it just to keep the assembler
code to a minimum. Files and functions naming is borrowed from X86.

Signed-off-by: Huacai Chen <chenhc@lemote.com>
Cc: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/9616/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: Hibernate: flush TLB entries earlier
Huacai Chen [Sun, 29 Mar 2015 02:54:05 +0000 (10:54 +0800)]
MIPS: Hibernate: flush TLB entries earlier

We found that TLB mismatch not only happens after kernel resume, but
also happens during snapshot restore. So move it to the beginning of
swsusp_arch_suspend().

Signed-off-by: Huacai Chen <chenhc@lemote.com>
Cc: <stable@vger.kernel.org>
Cc: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Cc: stable@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9621/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: SEAD3: Nuke remaining I2C bits.
Ralf Baechle [Sun, 29 Mar 2015 20:09:02 +0000 (22:09 +0200)]
MIPS: SEAD3: Nuke remaining I2C bits.

With no I2C driver available, keeping the platform device registration
makes no sense just as keeping the code to instantiage the I2C devices.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: SEAD3: Nuke I2C driver that never was wired up in Makefile.
Ralf Baechle [Sun, 29 Mar 2015 20:06:51 +0000 (22:06 +0200)]
MIPS: SEAD3: Nuke I2C driver that never was wired up in Makefile.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: SEAD3: Use symbolic addresses from sead-addr.h in I2C driver.
Ralf Baechle [Sun, 29 Mar 2015 14:06:03 +0000 (16:06 +0200)]
MIPS: SEAD3: Use symbolic addresses from sead-addr.h in I2C driver.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: SEAD3: Use symbolic addresses from sead-addr.h in LED driver.
Ralf Baechle [Fri, 27 Mar 2015 22:50:58 +0000 (23:50 +0100)]
MIPS: SEAD3: Use symbolic addresses from sead-addr.h in LED driver.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: SEAD3: New header file sead3-addr.h with hardware addresses.
Ralf Baechle [Fri, 27 Mar 2015 22:47:59 +0000 (23:47 +0100)]
MIPS: SEAD3: New header file sead3-addr.h with hardware addresses.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: SEAD3: Get rid of DRVNAME from LED driver for readability.
Ralf Baechle [Fri, 27 Mar 2015 20:57:36 +0000 (21:57 +0100)]
MIPS: SEAD3: Get rid of DRVNAME from LED driver for readability.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: SEAD3: Get rid of useless pr_debug calls in the LED driver.
Ralf Baechle [Fri, 27 Mar 2015 20:56:01 +0000 (21:56 +0100)]
MIPS: SEAD3: Get rid of useless pr_debug calls in the LED driver.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: SEAD3: Convert I2C driver to module_platform_driver.
Ralf Baechle [Fri, 27 Mar 2015 20:47:42 +0000 (21:47 +0100)]
MIPS: SEAD3: Convert I2C driver to module_platform_driver.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: SEAD3: Convert LED driver to module_platform_driver.
Ralf Baechle [Fri, 27 Mar 2015 20:47:01 +0000 (21:47 +0100)]
MIPS: SEAD3: Convert LED driver to module_platform_driver.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: SEAD3: Collect LED platform device registration in a single file.
Ralf Baechle [Thu, 23 Oct 2014 23:32:25 +0000 (01:32 +0200)]
MIPS: SEAD3: Collect LED platform device registration in a single file.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Cc: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: Bryan Wu <cooloney@gmail.com>
Cc: Richard Purdie <rpurdie@rpsys.net>
Cc: linux-leds@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8203/

9 years agoMIPS: BMIPS: restrict DTB selection to BMIPS_GENERIC
Florian Fainelli [Thu, 26 Mar 2015 04:55:15 +0000 (21:55 -0700)]
MIPS: BMIPS: restrict DTB selection to BMIPS_GENERIC

Since we are always sourcing arch/mips/bmips/Kconfig and there is no
dependency on BMIPS_GENERIC, we will offer building BMIPS-related DTBs
while this is not relevant for the other MIPS platforms.

Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: cernekee@gmail.com
Cc: jaedon.shin@gmail.com
Patchwork: https://patchwork.linux-mips.org/patch/9603/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: BMIPS: Flush the readahead cache after DMA.
Ralf Baechle [Fri, 27 Mar 2015 14:17:31 +0000 (15:17 +0100)]
MIPS: BMIPS: Flush the readahead cache after DMA.

BMIPS 3300/435x/438x CPUs have a readahead cache that is separate from
the L1/L2.  During a DMA operation, accesses adjacent to a DMA buffer
may cause parts of the DMA buffer to be prefetched into the RAC.  To
avoid possible coherency problems, flush the RAC upon DMA completion.

Derived from Kevin Cernekee's https://patchwork.linux-mips.org/patch/9602/.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: DMA: Implement platform hook to perform post-DMA cache flushes.
Ralf Baechle [Fri, 27 Mar 2015 14:10:30 +0000 (15:10 +0100)]
MIPS: DMA: Implement platform hook to perform post-DMA cache flushes.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: ath25: Remove unused DMA helper functions.
Ralf Baechle [Fri, 27 Mar 2015 12:11:51 +0000 (13:11 +0100)]
MIPS: ath25: Remove unused DMA helper functions.

These got merged with the ath25 support after 4e7f72660c39 (MIPS: Remove
unnecessary platform dma helper functions) had already removed them for
all other platforms.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: Loongson-3: remove deprecated IRQF_DISABLED
Michael Opdenacker [Fri, 27 Mar 2015 01:33:41 +0000 (18:33 -0700)]
MIPS: Loongson-3: remove deprecated IRQF_DISABLED

This removes the use of the IRQF_DISABLED flag
from arch/mips/loongson/loongson-3/hpet.c

It's a NOOP since 2.6.35.

Signed-off-by: Michael Opdenacker <michael.opdenacker@free-electrons.com>
Cc: chenhc@lemote.com
Cc: taohl@lemote.com
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9609/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: BCM47xx: Move NVRAM header to the include/linux/.
Rafał Miłecki [Mon, 1 Dec 2014 06:58:18 +0000 (07:58 +0100)]
MIPS: BCM47xx: Move NVRAM header to the include/linux/.

There are two reasons for having this header in the common place:
1) Simplifying drivers that read NVRAM entries. We will be able to
   safely call bcm47xx_nvram_* functions without #ifdef-s.
2) Getting NVRAM driver out of MIPS arch code. This is needed to support
   BCM5301X arch which also requires this NVRAM driver. Patch for that
   will follow once we get is reviewed.

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Acked-by: Hauke Mehrtens <hauke@hauke-m.de>
Cc: linux-mips@linux-mips.org
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: linux-soc@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8619/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: Expand __swp_offset() to carry 40 significant bits for 64-bit kernel.
David Daney [Tue, 24 Feb 2015 23:35:34 +0000 (15:35 -0800)]
MIPS: Expand __swp_offset() to carry 40 significant bits for 64-bit kernel.

With CONFIG_MIGRATION, the PFN of the migrating pages is stored in
__swp_offset(), so we must have enough bits to store the largest
possible PFN.  OCTEON NUMA systems have 41 bits of physical address
space, so with 4K pages (12-bits), we need at least 29 bits to store
the PFN.

The current width of 24-bits is too narrow, so expand it all the way
out to 40-bits.  This leaves the low order 16 bits as zero which does
not interfere with any of the PTE bits.

Signed-off-by: David Daney <david.daney@cavium.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9315/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>