Patrik Jakobsson [Mon, 16 Nov 2015 15:20:01 +0000 (16:20 +0100)]
drm/i915/gen9: Turn DC handling into a power well
Handle DC off as a power well where enabling the power well will prevent
the DMC to enter selected DC states (required around modesets and Aux
A). Disabling the power well will allow DC states again. For now the
highest DC state is DC6 for Skylake and DC5 for Broxton but will be
configurable for Skylake in a later patch.
v2: Check both DC5 and DC6 bits in power well enabled function (Ville)
v3:
- Remove unneeded DC_OFF case in skl_set_power_well() (Imre)
- Add PW2 dependency to DC_OFF (Imre)
v4: Put DC_OFF before PW2 in BXT power well array
drm/i915: Do not warn on PG2 enabled in gen9_disable_dc5()
PG2 enabled is not a requirement for disabling DC5. It's just one
of the reasons why the DMC wouldn't enter DC5. During modeset we don't
care about PG2 from a DC perspective, only the fact that DC5/DC6 is not
allowed.
drm/i915: Remove distinction between DDI 2 vs 4 lanes
We never make use of the distinction between 2 vs 4 lanes so combine
them into a per port domain instead. This saves us a few bits in the
power domain mask. Change suggested by Ville.
Ville Syrjälä [Mon, 9 Nov 2015 15:48:20 +0000 (16:48 +0100)]
drm/i915: Remove DDI power domain exclusion SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS
All the DDI power domains are already excluded from
SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS on account of
excluding SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS and
SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS, no need to spell them out again.
Ville Syrjälä [Mon, 9 Nov 2015 15:48:19 +0000 (16:48 +0100)]
drm/i915: Introduce a gmbus power domain
Currently the gmbus code uses intel_aux_display_runtime_get/put in an
effort to make sure the hardware is powered up sufficiently for gmbus.
That function only takes the runtime PM reference which on VLV/CHV/BXT
is not enough. We need the disp2d/pipe-a well on VLV/CHV and power well
2 on BXT. So add a new power domnain for gmbus and kill off the now
unused intel_aux_display_runtime_get/put. And change
intel_hdmi_set_edid() to use the gmbus power domain too since that's all
we need there.
Also toss in a BUILD_BUG_ON() to catch problems if we run out of
bits for power domains. We're already really close to the limit...
Ville Syrjälä [Mon, 16 Nov 2015 14:01:04 +0000 (15:01 +0100)]
drm/i915: Clean up AUX power domain handling
Introduce intel_display_port_aux_power_domain() which simply returns
the appropriate AUX power domain for a specific port, and then replace
the intel_display_port_power_domain() with calls to the new function
in the DP code. As long as we're not actually enabling the port we don't
need the lane power domains, and those are handled now purely from
modeset_update_crtc_power_domains().
My initial motivation for this was to see if I could keep the DPIO power
wells powered down while doing AUX on CHV, but turns out I can't so this
doesn't change anything for CHV at least. But I think it's still a
worthwile change.
v2: Add case for PORT E. Default to POWER_DOMAIN_AUX_D for now. (Ville)
Replaces "drm/i915: Force loading of csr program at boot" in the old
series.
Previously we called blindly into intel_csr_load_program() and depended
on a check of whether the CSR program memory was cleared or not.
This check is not reliable and no longer needed since we fixed the
call-sites of intel_csr_load_program().
Imre Deak [Tue, 17 Nov 2015 15:44:23 +0000 (17:44 +0200)]
drm/i915: fix handling of the disable_power_well module option
When this option is 0 (so the power well support is disabled) we are
supposed to enable all power wells once and don't disable them unless we
system suspend the device. Currently if the option is 0, we can call the
power well enable handlers multiple times, whenever their refcount
changes from 0->1. This may not be a problem for the HW, but it's not
logical and may trigger some warnings in the power well code which
doesn't expect this. So simply keep around a reference while we are
not system suspended to solve this. For simplicity mark the module
option read only, so we don't need to deal with re-enabling the feature
during runtime. If someone really needs that it could be added later in
a more proper way.
v2:
- fix typo in comment in intel_power_domains_suspend() (Patrik)
Imre Deak [Wed, 4 Nov 2015 17:24:19 +0000 (19:24 +0200)]
drm/i915/skl: remove redundant DDI/IRQ reinitialization during PW1 enabling
We don't need to reinit DDI and IRQs during PW1 enabling any more, since
we don't toggle PW1 on-demand any more. We enable PW1 only as part of
the display core init sequence and after this we initialize both DDI and
IRQs later in the init sequence. So remove these init steps from the
power well code.
Imre Deak [Wed, 4 Nov 2015 17:24:18 +0000 (19:24 +0200)]
drm/i915/skl: make sure LCPLL is disabled when uniniting CDCLK
Suppressing LCPLL disabling was added to avoid interfering with the DMC
firmware. It is not needed any more since we uninit CDCLK now with the
DMC deactivated (DC states disabled). We also must disable it during system
suspend as part of the Bspec "Display uninit sequence".
Imre Deak [Wed, 4 Nov 2015 17:24:17 +0000 (19:24 +0200)]
drm/i915/skl: disable DC states before display core init/uninit
We need to disable the DC states during display core init to sanitize
the HW state we inherit from the BIOS. We need to disable it during
display core uninit too, since the power well framework will leave it
enabled (since we get to the display core uninit step with all power
domains disabled already).
Imre Deak [Wed, 4 Nov 2015 17:24:15 +0000 (19:24 +0200)]
drm/i915/skl: don't toggle PW1 and MISC power wells on-demand
With the DMC firmware installed we don't need to handle HW resources
that are handled automatically by the firmware. Besides being redundant
this can also interfere with the firmware, possibly getting it into a
broken/blocked state. The on-demand handling of PW1 was already half-way
removed, MISC IO was still handled in this way. After the last patch we
init/uninit these HW resources manually as part of the display core
init/uninit sequence, so we can now remove the on-demand handling for
these completely.
We still keep around the power wells (with no domains attached to them)
since the manual toggling during display core init/uninit happens via
the current API.
Imre Deak [Tue, 17 Nov 2015 15:33:53 +0000 (17:33 +0200)]
drm/i915/skl: init/uninit display core as part of the HW power domain state
We need to initialize the display core part early, before initializing
the rest of the display power state. This is also described in the bspec
termed "Display initialization sequence". Atm we run this sequence
during driver loading after power domain HW state initialization which
is too late and during runtime suspend/resume which is unneeded and can
interere with DMC functionality which handles HW resources toggled
by this init/uninit sequence automatically. The init sequence must be
run as the first step of HW power state initialization and during
system resume. The uninit sequence must be run during system suspend.
To address the above move the init sequence to the initial HW power
state setup and the uninit sequence to a new power domains suspend
function called during system suspend.
As part of the init sequence we also have to reprogram the DMC firmware
as it's lost across a system suspend/resume cycle.
After this change CD clock initialization during driver loading will
happen only later after other dependent HW/SW parts are initialized,
while during system resume it will get initialized as the last step of
the init sequence. This distinction can be removed by some refactoring
of platform independent parts. I left this refactoring out from this
series since I didn't want to change non-SKL parts. This is a TODO for
later.
v2:
- fix error path in i915_drm_suspend_late()
- don't try to re-program the DMC firmware if it failed to load
Damien Lespiau [Wed, 4 Nov 2015 17:24:12 +0000 (19:24 +0200)]
drm/i915: Make turning on/off PW1 and Misc I/O part of the init/fini sequences
Before this patch, we used the intel_display_power_{get,put} functions
to make sure the PW1 and Misc I/O power wells were enabled all the
time while LCPLL was enabled. We called a get() at
intel_ddi_pll_init() when we discovered that LCPLL was enabled, then
we would call put/get at skl_{un,}init_cdclk().
The problem is that skl_uninit_cdclk() is indirectly called by
intel_runtime_suspend(). So it will only release its power well
_after_ we already decided to runtime suspend. But since we only
decide to runtime suspend after all power wells and refcounts are
released, that basically means we will never decide to runtime
suspend.
So what this patch does to fix that problem is move the PW1 + Misc I/O
power well handling out of the runtime PM mechanism: instead of
calling intel_display_power_{get_put} - functions that touch the
refcount -, we'll call the low level intel_power_well_{en,dis}able,
which don't change the refcount. This way, it is now possible for the
refcount to actually reach zero, and we'll now start runtime
suspending/resuming.
v2 (from Paulo):
- Write a commit message since the original patch left it empty.
- Rebase after the intel_power_well_{en,dis}able rename.
- Use lookup_power_well() instead of hardcoded indexes.
Testcase: igt/pm_rpm/rte (and every other rpm test) Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92211
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92605 Signed-off-by: Imre Deak <imre.deak@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1446657859-9598-4-git-send-email-imre.deak@intel.com
Imre Deak [Wed, 4 Nov 2015 17:24:11 +0000 (19:24 +0200)]
drm/i915: fix lookup_power_well for power wells without any domain
The current lookup code wouldn't find a power well if it's not in any
power domain. There wasn't any power wells before but an upcoming patch
will detach the power domains from power well#1 and the MISC IO power
wells, so fix things up accordingly.
Imre Deak [Wed, 4 Nov 2015 17:24:10 +0000 (19:24 +0200)]
drm/i915: fix the power well ID for always on wells
lookup_power_well() expects uniq power well IDs, but atm we have
uninitialized IDs which would clash with those power wells with a 0
ID. This wasn't a problem so far since nothing looked up such a power
well, but an upcoming patch will (Misc IO for SKL), so fix this up on
platforms where this matters.
Imre Deak [Mon, 9 Nov 2015 18:16:26 +0000 (20:16 +0200)]
drm/i915: get runtime PM reference around GEM set_tiling IOCTL
After fixing the same issue in the set_caching IOCTL and Chris' request
to check out the possibilities for an improved RPM ref handling I
noticed that we have the same issue in the set_tiling IOCTL. Fix this
up.I didn't see any bug reports about this one, but the GTT unbind
operation on this path accesses the HW, which needs the ref.
Chris Wilson [Fri, 23 Oct 2015 17:43:32 +0000 (18:43 +0100)]
drm/i915: Serialise updates to GGTT with access through GGTT on Braswell
When accessing through the GTT from one CPU whilst concurrently updating
the GGTT PTEs in another thread, the hardware likes to return random
data. As we have strong serialisation prevent us from modifying the PTE
of an active GTT mmapping, we have to conclude that it whilst modifying
other PTE's that error occurs. (I have not looked for any pattern such
as modifying PTE within the same page or cacheline as active PTE -
though checking whether revoking neighbouring objects should be enough
to test that theory.) The corruption also seems restricted to Braswell
and disappears with maxcpus=0. This patch stops all access through the
GTT by other CPUs when we update any PTE by stopping the machine around
the GGTT update.
Note that splitting up the 64 bit write into two 32 bit writes was
tried and found to fail too.
Testcase: igt/gem_concurrent_blit
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89079 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
[danvet: Add note about 2x 32bits failing too.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drm/i915: Cleanup test data during long/short hotplug
Automated test data that is updated when a test is requested is not cleared
till next automated test request is recevied which can cause various
problems. This patch fixes this by clearing this during the next
short pulse and on hot unplug.
For example, when TEST_LINK_TRAINING is requested it is updated
to appropriate variable inside intel_dp_handle_test_request
but is also cleared only inside the same function. if the next
short pulse does not have the AUTOMATED_TEST_REQUEST bits set
the variable will not be cleared resulting in carrying incorrect
test status in local variables.
v2: Added comments and moved nack and defer variables before set_edid
(Sonika)
If ddb allocation for planes in current CRTC is changed, that doesn't
lead to ddb allocation change for other CRTCs, because our DDB allocation
is not dynamic according to plane parameters, ddb is allocated according
to number of CRTC enabled, & divided equally among CTRC's.
In current condition check during Watermark calculation, if number of
plane/ddb allocation changes for current CRTC, Watermark for other pipes
are recalculated. But there is no change in DDB allocation of other pipe
so watermark is also not changed, This leads to warning messages.
WARN_ON(!wm_changed)
This patch corrects this and check if DDB allocation for pipes is changed,
then only recalculate watermarks.
v2 (by Matt): Rebased to latest -nightly and fixed a typo
Signed-off-by: Kumar, Mahesh <mahesh1.kumar@intel.com>
Reviewed-by(v1): Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Ville Syrjälä [Wed, 11 Nov 2015 18:34:13 +0000 (20:34 +0200)]
drm/i915: Remove the magic AUX_CTL is at DP + foo tricks
Currently we determine the location of the AUX registers in a confusing
way. First we assume the PCH registers are used always, but then we
override it for everything but HSW/BDW to use DP+0x10. Very confusing.
Let's just make it straightforward and simply add a few functions to
pick the right AUX_CTL based on the DP port.
To deal with VLV/CHV we'll include the display_mmio_offset into the
AUX register defines.
Ville Syrjälä [Wed, 11 Nov 2015 18:34:12 +0000 (20:34 +0200)]
drm/i915: Parametrize AUX registers
v2: Keep some MISSING_CASE() stuff (Jani)
s/-1/-PIPE_B/ in the register macro
Fix typo in patch subject
v3: Use PORT_B registers for invalid ports in g4x_aux_ctl_reg() (Jani)
v4: Reorder patches (Chris)
Ville Syrjälä [Wed, 11 Nov 2015 18:34:11 +0000 (20:34 +0200)]
drm/i915: Replace the aux ddc name switch statement with kasprintf()
Use kasprintf() to generate the "DPDDC-<port>" name for the aux helper.
To deal with errors properly make intel_dp_aux_init() return something,
and adjust the caller to match. It seems we were also missing a
intel_dp_mst_encoder_cleanup() call on edp (non-port A) init failures,
so add that too.
The whole error/cleanup ordering doesn't feel entirely sane to me, but
I'll leave that part alone for now.
v2: Use kasprintf() instead of a table, reorder patches (Chis)
The i_boost level in the DDI translation tables are stored per level.
However, skl_ddi_set_iboos() would choose an entry of that table based
on the port argument.
Imre Deak [Wed, 28 Oct 2015 21:59:06 +0000 (23:59 +0200)]
drm/i915/gen9: flush DMC fw loading work during system suspend
Currently during system s/r we enable/disable DC6, so before we do so
make sure that the firmware loading is complete.
Note that whether we need to enable DC6 for S3/S4 is still open. At
least the firmware program is lost during S3 and we need to reprogram it
after resuming. Until this is clarified we keep the current behavior and
enable/disable DC6.
Animesh Manna [Wed, 28 Oct 2015 21:59:05 +0000 (23:59 +0200)]
drm/i915/gen9: Use flush_work to synchronize with dmc loader
During driver unload to ensure we dont have any pending task,
flush_work added to complete firmware loading task.
v1: Initial version.
v2: As per review comments from Daniel,
Removed flush_work from skl_set_power_well. As we have taken
power well refernece and rpm count during firmware loading
by using display_power_domain_get/put - this will always
ensure rpm will be blocked if firmware is not loaded.
Cc: Daniel Vetter <daniel.vetter@intel.com> Cc: Damien Lespiau <damien.lespiau@intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: Sunil Kamath <sunil.kamath@intel.com> Signed-off-by: Animesh Manna <animesh.manna@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Tested-by: Daniel Stone <daniels@collabora.com> # SKL Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1446069547-24760-12-git-send-email-imre.deak@intel.com
Daniel Vetter [Wed, 28 Oct 2015 21:59:04 +0000 (23:59 +0200)]
drm/i915: Use request_firmware and our own async work
Two benefits:
- We can use FW_LOADER_USERSPACE_FALLBACK.
- We can use flush_work to synchronize with the oustanding worker,
which is a notch more obvious what it does than having a special
completion.
The next patch will properly synchronize against the async loader in
the resume and unload code.
Cc: Damien Lespiau <damien.lespiau@intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: Sunil Kamath <sunil.kamath@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@intel.com> Signed-off-by: Animesh Manna <animesh.manna@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Tested-by: Daniel Stone <daniels@collabora.com> # SKL Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1446069547-24760-11-git-send-email-imre.deak@intel.com
Daniel Vetter [Thu, 12 Nov 2015 15:11:29 +0000 (17:11 +0200)]
drm/i915/gen9: extract parse_csr_fw
The loader function will get a bit more complicated soon, extract the
parsing code to make the control flow clearer. While doing that just
use dev_priv->csr.dmc_payload as the indicator for whether it all
suceeded or not.
v2-v3:
- unchanged
v4:
- rebased on top of latest drm-intel-nightly
Cc: Damien Lespiau <damien.lespiau@intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: Sunil Kamath <sunil.kamath@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@intel.com> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
[imre: remove note about BE cast from commit message, it's not relevant
any more] Signed-off-by: Imre Deak <imre.deak@intel.com> Tested-by: Daniel Stone <daniels@collabora.com> # SKL
[Jani: fix checkpatch warn on multiple blank lines] Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1447341089-2735-1-git-send-email-imre.deak@intel.com
Daniel Vetter [Wed, 28 Oct 2015 21:59:02 +0000 (23:59 +0200)]
drm/i915/gen9: Use dev_priv in csr functions
As all csr firmware related opertion are not using any
any data structures of drm framework level, so better to
use dev_priv instead of dev. it's a new style! :)
Cc: Damien Lespiau <damien.lespiau@intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: Sunil Kamath <sunil.kamath@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@intel.com> Signed-off-by: Animesh Manna <animesh.manna@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Tested-by: Daniel Stone <daniels@collabora.com> # SKL Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1446069547-24760-9-git-send-email-imre.deak@intel.com
Daniel Vetter [Wed, 28 Oct 2015 21:58:59 +0000 (23:58 +0200)]
drm/i915/gen9: Align line continuations in intel_csr.c.
Standard is to align continuations of parameter lists and if
conditions to the opening ( in i915 and drm code.
Apply this across the entire file since it was sticking out a bit too
much.
Cc: Damien Lespiau <damien.lespiau@intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: Sunil Kamath <sunil.kamath@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@intel.com> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
[imre: removed note about reg definitions from the commit message, it's
not relevant any more] Signed-off-by: Imre Deak <imre.deak@intel.com> Tested-by: Daniel Stone <daniels@collabora.com> # SKL Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1446069547-24760-6-git-send-email-imre.deak@intel.com
Daniel Vetter [Thu, 12 Nov 2015 15:10:37 +0000 (17:10 +0200)]
drm/i915/gen9: Remove csr.state, csr_lock and related code.
This removes two anti-patterns:
- Locking shouldn't be used to synchronize with async work (of any
form, whether callbacks, workers or other threads). This is what the
mutex_lock/unlock seems to have been for in intel_csr_load_program.
Instead ordering should be ensured with the generic
wait_for_completion()/complete(). Or more specific functions
provided by the core kernel like e.g.
flush_work()/cancel_work_sync() in the case of synchronizing with a
work item.
- Don't invent own completion like the following code did with the
(already removed) wait_for(csr_load_status_get()) pattern - it's
really hard to get these right when you want them to be _really_
correct (and be fast) in all cases. Furthermore it's easier to read
code using the well-known primitives than new ones using
non-standard names.
Before enabling/disabling DC6 check if the firmware is loaded
successfully. This is guaranteed during runtime s/r, since otherwise we
don't enable RPM, but not during system s/r.
Note that it's still unclear whether we need to enable/disable DC6
during system s/r, until that's clarified, keep the current behavior and
enable/disable DC6.
Also after this patch there is a race during system s/r where the
firmware may not be loaded yet, that's addressed in an upcoming patch.
v2-v3:
- unchanged
v4:
- rebased on latest drm-intel-nightly
Cc: Damien Lespiau <damien.lespiau@intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: Sunil Kamath <sunil.kamath@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@intel.com> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
[imre: added code and note about checking if the firmware loaded ok,
before enabling/disabling it] Reviewed-by: Animesh Manna <animesh.manna@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Tested-by: Daniel Stone <daniels@collabora.com> # SKL Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1447341037-2623-1-git-send-email-imre.deak@intel.com
Daniel Vetter [Wed, 28 Oct 2015 21:58:57 +0000 (23:58 +0200)]
drm/i915/gen9: move assert_csr_loaded into intel_rpm.c
Avoids non-static functions since all the callers are in intel_rpm.c.
Cc: Damien Lespiau <damien.lespiau@intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: Sunil Kamath <sunil.kamath@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@intel.com> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
[imre: removed note about reg definitions from commit message, since
it's not relevant any more] Signed-off-by: Imre Deak <imre.deak@intel.com> Tested-by: Daniel Stone <daniels@collabora.com> # SKL
[Jani: make assert_csr_loaded static] Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1446069547-24760-4-git-send-email-imre.deak@intel.com
Daniel Vetter [Wed, 28 Oct 2015 21:58:56 +0000 (23:58 +0200)]
drm/i915: use correct power domain for csr loading
Grabbing a runtime pm reference with intel_runtime_pm_get will only
prevent device D3. But dmc firmware is required even earlier (namely
for the skl power well 2).
Hence we need to grab a rpm reference higher up in the hierarchy. For
simplicity just grab the _INIT display power well. That's a bit too
much, but since the firmware loading task should completely fairly
quickly this won't be a real problem really.
Cc: Damien Lespiau <damien.lespiau@intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: Sunil Kamath <sunil.kamath@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@intel.com> Signed-off-by: Animesh Manna <animesh.manna@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Tested-by: Daniel Stone <daniels@collabora.com> # SKL Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1446069547-24760-3-git-send-email-imre.deak@intel.com
Animesh Manna [Wed, 28 Oct 2015 21:58:55 +0000 (23:58 +0200)]
drm/i915/gen9: csr_init after runtime pm enable
Skl is fully dependent on dmc for going to low power state (dc5/dc6).
This requires a trigger from rpm. To ensure the dmc firmware
is available for runtime pm support rpm-reference-count is used
by not releasing the rpm reference if firmware loading is
not completed.
So moved the intel_csr_ucode_init call after runtime pm enable.
Cc: Daniel Vetter <daniel.vetter@intel.com> Cc: Damien Lespiau <damien.lespiau@intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: Sunil Kamath <sunil.kamath@intel.com> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
[imre: moved the call right after power domain init to avoid race with
the console modesetting] Signed-off-by: Imre Deak <imre.deak@intel.com> Tested-by: Daniel Stone <daniels@collabora.com> # SKL Reviewed-by: A.Sunil Kamath <sunil.kamath@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1446069547-24760-2-git-send-email-imre.deak@intel.com
Jani Nikula [Tue, 20 Oct 2015 12:38:33 +0000 (15:38 +0300)]
drm/i915: refactor stepping info retrieval
Have only one if ladder for platforms and only one range check for
size. Makes it easier to handle new platforms. Remove the use of
negative return values in char, which might underflow to be positive for
some negative error codes.
Lukas Wunner [Thu, 5 Nov 2015 08:30:50 +0000 (09:30 +0100)]
drm/i915: Clean up LVDS register handling harder
Minor fixup to d0669d007542 ("drm/i915: Clean up LVDS register
handling") which intended to read lvds_reg just once at the
beginning of intel_lvds_init() and use that throughout the rest
of the function but accidentally missed one register readout.
Ville Syrjälä [Fri, 6 Nov 2015 13:08:33 +0000 (15:08 +0200)]
drm/i915: Move the fbdev async_schedule() into intel_fbdev.c
Reading the driver load/unload code leaves one confused as there's
an async_schedule() in the load, but not async_synchronize_full()
in sight. In fact it's hidden inside intel_fbdev.c. So let's move the
async_schedule() into intel_fbdev.c as well so that it's next to the
async_synchronize_full(), which should make the relationship easier
to see.
Plus this way we won't schedule a nop function call when fbdev is
disabled. And we were passing a pointer to a static inline
function to async_schedule(), which seems rather dubious to me.
Ville Syrjälä [Fri, 6 Nov 2015 13:08:32 +0000 (15:08 +0200)]
drm/i915: Do fbdev fini first during unload
We set up fbdev last during load, so doing the fbdev cleanup should be
first.
We weren't supposed to drop the init power during driver unload, but since
the fbdev teardown happened after intel_power_domains_fini() that could
have happened due in one of two ways. First it could have happened
during the modeset caused by normal fbdev cleanup. But in addition it
could have happened already via the intel_fbdev_initial_config() since
that is executed asynhronously, and the async_synchronize_full() was
done during fbdev cleanup, after intel_power_domains_fini(). All of
that got eliminated by
commit 292b990e86abc ("drm/i915: Update power domains on readout.")
since we now drop the init power synchronously during driver load.
So there is no real bug wrt. the init power anymore, but still it seems
better to do the fbdev cleanup first, before we've potentially cleaned
up something else important.
Ville Syrjälä [Fri, 6 Nov 2015 13:08:31 +0000 (15:08 +0200)]
drm/i915: Kill intel_runtime_pm_disable()
intel_runtime_pm_disable() takes an extra rpm reference which combined
with the one we leak from intel_display_set_init_power() leaves the
usage count at <original>+1 after the driver has been unloaded.
The original ref is dropped explicitly in intel_runtime_pm_enable().
So the next time we load the driver we can no longer do runtime PM ever.
This used to work, but
commit 292b990e86ab ("drm/i915: Update power domains on readout.")
broke things by not dropping the init power domain during fbdev
teardown. Based on the comment in intel_power_domains_fini(), the
way it used to to work wasn't intentional. As in we weren't supposed
to drop the init power during driver unload. And since we no longer
do, we now leak an extra rpm reference.
So fix things by throwing intel_runtime_pm_disable() to the bin, so
that the only leaked reference comes from the init power domain.
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Cc: Daniel Stone <daniels@collabora.com> Cc: Jesse Barnes <jbarnes@virtuousgeek.org> Fixes: 292b990e86ab ("drm/i915: Update power domains on readout.") Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1446815313-9490-2-git-send-email-ville.syrjala@linux.intel.com Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Ville Syrjälä [Tue, 10 Nov 2015 14:16:17 +0000 (16:16 +0200)]
drm/i915: Use intel_dp->DP in eDP PLL setup
Use intel_dp->DP in the eDP PLL setup, instead of doing RMWs.
To do this we need to move DP_AUDIO_OUTPUT_ENABLE setup to happen later,
so that we don't enable audio accidentally while configuring the PLL.
Note that actually we already enabled audio before the port due to
the double port register write magic required by VLV/CHV from 7b713f50d78b6 ("drm/i915: Fix eDP link training when switching pipes on VLV/CHV")
So that gets changed now to keep audio off as long as the port is off.
Also intel_dp_link_down() must be made to update intel_dp->DP so that we
don't re-enable the port by accident when turning off the PLL. This is
safe now that we don't call intel_dp_link_down() during link retraining.
v2: Add a note about the audio vs. port enable (Daniel)
Ville Syrjälä [Thu, 29 Oct 2015 19:25:58 +0000 (21:25 +0200)]
drm/i915: Hide underruns from eDP PLL and port enable on ILK
We get underruns on the other pipe when enabling the CPU eDP PLL and
port on ILK.
Bspec knows about the PLL issue, and recommends doing a vblank wait just
prior to enabling the PLL. That does seem to help, but unfortunately we
get another underrun when actually enabling the CPU eDP port. Bspec
doesn't mention that at all, and the same vblank wait trick doesn't
appear to be effective there.
Since I have no better clue how to deal with this, just hide the errors.
Ville Syrjälä [Fri, 30 Oct 2015 17:23:22 +0000 (19:23 +0200)]
drm/i915: Disable FIFO underrun reporting around IBX transcoder B workaround
Doing the IBX transcoder B workaround causes underruns on
pipe/transcoder A. Just hide them by disabling underrun reporting for
pipe A around the workaround.
It might be possible to avoid the underruns by moving the workaround
to be applied only when enabling pipe A. But I was too lazy to try it
right now, and the current method has been proven to work, so didn't
want to change it too hastily.
Note that this can re-enable underrun reporting on pipe A if was
already disabled due to a previous actual underrun. But that's OK, we
may just get a second underrun report if another real underron occurrs
on pipe A.
v2: Note that pipe A underruns can get re-enabled due to this (Jani)
Ville Syrjälä [Thu, 29 Oct 2015 19:25:56 +0000 (21:25 +0200)]
drm/i915: Check for CPT and not !IBX in ironlake_disable_pch_transcoder()
ironlake_enaable_pch_transcoder() checks for CPT to see if it should
enable the timing override chicken bit, but
ironlake_disable_pch_transcoder() checks for !IBX to see if it should
clear the same bit. Change ironlake_disable_pch_transcoder() to check
for CPT as well to keep the two sides consistent.
Ville Syrjälä [Fri, 30 Oct 2015 17:22:21 +0000 (19:22 +0200)]
drm/i915: Check for FIFO underruns after modeset on IVB/HSW and CPT/PPT
Due to the shared error interrupt on IVB/HSW and CPT/PPT we may not
always get an interrupt on a FIFO underrun. But we can always do an
explicit check (like we do on GMCH platforms that have no underrun
interrupt).
v2: Drop stale kerneldoc for i9xx_check_fifo_underruns() (Daniel)
Ville Syrjälä [Fri, 30 Oct 2015 17:21:31 +0000 (19:21 +0200)]
drm/i915: Re-enable PCH FIO underrun reporting after pipe has been disabled
Some hardware (IVB/HSW and CPT/PPT) have a shared error interrupt for
all the relevant underrun bits, so in order to keep the error interrupt
enabled, we need to have underrun reporting enabled on all PCH
transocders. Currently we leave the underrun reporting disabled when
the pipe is off, which means we won't get any underrun interrupts
when only a subset of the pipes are active.
Fix the problem by re-enabling the underrun reporting after the pipe has
been disabled. And to avoid the spurious underruns during pipe enable,
disable the underrun reporting before embarking on the pipe enable
sequence. So this way we have the error reporting disabled while
running through the modeset sequence.
v2: Re-enable PCH FIFO underrun reporting unconditionally on pre-HSW
Ville Syrjälä [Thu, 29 Oct 2015 19:25:53 +0000 (21:25 +0200)]
drm/i915: Enable PCH FIFO underruns later on HSW+
As we did for ILK/SNB/IVB, move the PCH FIFO underrun enable to happen
after the encoder enable on HSW+. And again, for symmetry, move the
the disable to happen before encoder disable.
I've left out the vblank wait before the enable here because I don't
know if it's needed or not. Actually I don't know if this entire
change is needed as I don't have a HSW/BDW with VGA output.
Ville Syrjälä [Fri, 30 Oct 2015 17:20:27 +0000 (19:20 +0200)]
drm/i915: Enable PCH FIFO underruns later on ILK/SNB/IVB
We get spurious PCH FIFO underruns if we enable the reporting too soon
after enabling the crtc. Move it to be the last step, after the encoder
enable. Additionally we need an extra vblank wait, otherwise we still
get the underruns. Presumably the pipe/fdi isn't yet fully up and running
otherwise.
For symmetry, disable the PCH underrun reporting as the first thing,
just before encoder disable, when shutting down the crtc.
v2: Do the PCH underrun enable unconditionally (Jani, Daniel)
Ville Syrjälä [Thu, 29 Oct 2015 19:25:51 +0000 (21:25 +0200)]
drm/i915: Set sync polarity from adjusted mode for TRANS_DP_CTL
Rather than looking at crtc->mode (which is the user mode) dig up the
sync polarity settings from the adjusted_mode when programming
TRANS_DP_CTL on CPT/PPT.
Paulo Zanoni [Wed, 4 Nov 2015 19:10:56 +0000 (17:10 -0200)]
drm/i915: remove in_dbg_master check from intel_fbc.c
From our maintainer Daniel Vetter a few days ago:
"Oh dear this is dead code. kdbg uses the fbcon, which always uses
untiled, which means fbc will never be enabled. Also we have 0 users
and 0 test coverage for kdbg on top of i915 (Jesse implemented it
for fun years back). Imo just remove all this code."
Adding to what Daniel said: for kgdboc's KMS support,
intel_pipe_set_base_atomic() already manually disables FBC, so we
won't do the in_dbg_master() check there. This is essentially a revert
of:
commit c924b934d0cd14a4559611da91f28f59acebe32a
Author: Jason Wessel <jason.wessel@windriver.com>
Date: Thu Aug 5 09:22:32 2010 -0500
i915: when kgdb is active display compression should be off
Besides, it is not clear what is the exact problem caused by FBC, and
why other features such as PSR, DRRS, IPS and RPM are not also
checking for in_dbg_master(). IMHO we should either remove the code as
suggested by Daniel or we add some nice comments explaining why is FBC
so special.
v2: Rebase due to new patch order.
Cc: Jason Wessel <jason.wessel@windriver.com> Cc: Jesse Barnes <jbarnes@virtuousgeek.org> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Link: http://patchwork.freedesktop.org/patch/msgid/1446664257-32012-13-git-send-email-paulo.r.zanoni@intel.com Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Paulo Zanoni [Wed, 4 Nov 2015 19:10:55 +0000 (17:10 -0200)]
drm/i915: clarify that checking the FB stride for CFB is intentional
Daniel was looking at this code and asked about whether fb->pitches[0]
is correct, then he suggested we should a comment to make sure it is
actually intentional.
For more information on the CFB size calculation, please see the
commit message of:
commit c4ffd40908c30a33291227920e921f6b45b9e8f7
Author: Paulo Zanoni <paulo.r.zanoni@intel.com>
Date: Thu Oct 1 19:55:57 2015 -0300
drm/i915: fix CFB size calculation
Paulo Zanoni [Wed, 4 Nov 2015 19:10:53 +0000 (17:10 -0200)]
drm/i915: remove too-frequent FBC debug message
If we run igt/kms_frontbuffer_tracking, this message will appear
thousands of times, eating a significant part of our dmesg buffer.
It's part of the expected FBC behavior, so let's just silence it.
Paulo Zanoni [Wed, 4 Nov 2015 19:10:52 +0000 (17:10 -0200)]
drm/i915: refactor FBC deactivation at init
Make sure we deactivate FBC at intel_fbc_init(), so we can remove the
call from intel_display.c. Currently we only have the "enabled"
software state, but later we'll have both "enabled" and "active", and
we'll add assertions to them, so just calling intel_fbc_disable() from
intel_modeset_init() won't work. It's better to make sure
intel_fbc_init() already puts the hardware in the expected state, so
we can put nice assertions in the other functions.
v2: Keep/improve the comment (Chris).
v3: Improve the commit message a little bit.
Paulo Zanoni [Wed, 4 Nov 2015 19:10:51 +0000 (17:10 -0200)]
drm/i915: don't disable_fbc() if FBC is already disabled
If FBC is disabled we will still call intel_fbc_invalidate(), and as a
result we may call intel_fbc_deactivate(), which will try to touch
registers.
I'm pretty sure I saw this happen on a runtime suspended device, and
I'm almost sure I was running igt/pm_rpm. It produced the "you touched
registers while the device is suspended" WARNs. But this was some time
ago and I can't remember exactly which conditions were necessary to
reproduce the problem.
Paulo Zanoni [Wed, 4 Nov 2015 19:10:50 +0000 (17:10 -0200)]
drm/i915: fix the __intel_fbc_update() comments
Don't try to list in comments the cases where we should enable or
disable FBC: it varies a lot with the hardware generations and the
code should be the documentation. Also notice that there's already a
huge gap between the comments and what's in the code.
Paulo Zanoni [Wed, 4 Nov 2015 19:10:49 +0000 (17:10 -0200)]
drm/i915: use struct intel_crtc *crtc at __intel_fbc_update()
This change was part of the commit that makes intel_fbc_update()
receive an intel_crtc as argument instead of dev_priv, but since it
was polluting the diff with too many chunks I decided to move it to
its own commit.
It seems that our developers are favoring having this instead of the
old combination drm_crtc *crtc + intel_crtc *intel_crtc, and on the
mentioned commit we'll get rid of the drm_crtc variable, so let's do
an intermediate commit with the rename, so on the next commit we'll
have just struct intel_crtc *crtc.
Paulo Zanoni [Wed, 4 Nov 2015 19:10:45 +0000 (17:10 -0200)]
drm/i915: rename intel_fbc_nuke to intel_fbc_recompress
Although the term "nuke" is part of the FBC spec, it's not very
intuitive, so let's rename it to make it easier for people that are
not familiar with the spec.
Matt Roper [Thu, 5 Nov 2015 22:53:32 +0000 (14:53 -0800)]
drm/i915/bxt: Force port A DDI to use 4 lanes
The bspec indicates that DDI A using four lanes is the only valid
configuration for Broxton (Broxton doesn't have a DDI E to split these
lanes with); the DDI_A_4_LANES bit of port A's DDI_BUF_CTL should always
be set by the BIOS. However some BIOS versions seem to only be setting
this bit if eDP is actually lit up at boot time; if the BIOS doesn't
turn on the eDP panel because an external display is plugged in, then
this bit is never properly initialized. The end result of this is that
we wind up calculating a lower max data rate than we should and may wind
up rejecting the native mode for panels that we should be able to drive.
Let's workaround this BIOS bug by just turning the DDI_A_4_LANES bit on
in our driver's internal state if we recognize that we're running on BXT
where it should have been on anyway.
Mika Kuoppala [Fri, 30 Oct 2015 11:26:15 +0000 (13:26 +0200)]
drm/i915: Avoid pointer arithmetic in calculating plane surface offset
VMA offsets are 64 bits. Plane surface offsets are in ggtt and
the hardware register to set this is thus 32 bits. Be explicit
about these and convert carefully to from vma to final size.
This will make sparse happy by not creating 32bit pointers out
of 64bit vma offsets.
Mika Kuoppala [Thu, 29 Oct 2015 13:21:19 +0000 (15:21 +0200)]
drm/i915: Add dmc firmware load state and version to error state
We have had one case where buggy csr/dmc firmware version influenced
gt side and caused a hang. Add dmc firmware loading state and
version to error state.
v2: - Rebased on top of Damien's patches
- included fw load state
v3: include dmc info only if platform supports it (Chris)
v4: move *csr to branch scope (Chris)
v5: remove dependency to csr_state
Mika Kuoppala [Tue, 27 Oct 2015 12:47:03 +0000 (14:47 +0200)]
drm/i915/bxt: Expose DC5 entry count
For bxt CSR firmware exposes a count of dc5 entries. Expose
it through debugs
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Tested-by: Daniel Stone <daniels@collabora.com> # SKL Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Damien Lespiau [Tue, 27 Oct 2015 12:47:01 +0000 (14:47 +0200)]
drm/i915/skl: Print the DMC firmware status in debugfs
Create a new debufs file for it, we'll have a few more things to add
there.
v2: Fix checkpatch warning about static const array
v3: use named initializers (Ville)
v4: strip out csr_state as it will be removed in future (Ville, Imre)
Mika Kuoppala [Fri, 30 Oct 2015 15:52:16 +0000 (17:52 +0200)]
drm/i915/skl: Refuse to load outdated dmc firmware
There is known issue on GT interrupt delivery with DC6 and
firmwares <1.21. There is a suspicion that this causes
spurious gpu hangs on driver init and with some workloads,
as upgrading the firmware to 1.21 makes these problems
disappear.
As of now the current version included in distribution
firmware packages is very like to be 1.19. Play it safe and
refuse to load a firmware version that may affect gpu
side stability.
With < 1.23 there is a palette and dmc ram corruption issue
so blacklist anything below that.
v2: Refuse to load fw instead of notifying the user
v3: Rebase on header version changes
v4: Refuse to load anything less than 1.23
v5: Give enough information for user for finding correct fw (Chris)
v6: better url and formatting (Chris)
v7: move error log for each fail path (Mika)
bail out earlier in load path (Imre)
v8: Fix the version check (Imre)
Cc: Animesh Manna <animesh.manna@intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Dave Gordon <david.s.gordon@intel.com> Cc: Arun Siluvery <arun.siluvery@linux.intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: Patrik Jakobsson <patrik.jakobsson@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@gmail.com> Cc: Chris Wilson <chris@chris-wilson.co.uk>
References: https://01.org/linuxgraphics/downloads/skldmcver121
References: https://01.org/linuxgraphics/downloads/skylake-dmc-1.23
Testcase: igt/gem_exec_nop Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1446220336-32392-1-git-send-email-mika.kuoppala@intel.com Tested-by: Daniel Stone <daniels@collabora.com> # SKL Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Damien Lespiau [Tue, 27 Oct 2015 12:46:59 +0000 (14:46 +0200)]
drm/i915/skl: Store and print the DMC firmware version we load
That can be handy later on to tell which DMC firmware version the user
has, by just looking at the dmesg.
v2: use DRM_DEBUG_DRIVER (Chris)
v3: use DRM_INFO (Marc Herbert)
Cc: Marc Herbert <marc.herbert@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> (v1) Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1445950025-5793-1-git-send-email-mika.kuoppala@intel.com Reviewed-by: Imre Deak <imre.deak@intel.com> Tested-by: Daniel Stone <daniels@collabora.com> # SKL Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Tvrtko Ursulin [Tue, 30 Jun 2015 09:06:27 +0000 (10:06 +0100)]
drm/i915: Fix failure paths around initial fbdev allocation
We had two failure modes here:
1.
Deadlock in intelfb_alloc failure path where it calls
drm_framebuffer_remove, which grabs the struct mutex and intelfb_create
(caller of intelfb_alloc) was already holding it.
2.
Deadlock in intelfb_create failure path where it calls
drm_framebuffer_unreference, which grabs the struct mutex and
intelfb_create was already holding it.
[Daniel Vetter on why struct_mutex needs to be locked in the second half
of intelfb_create: "The vma [for the fbdev] is pinned, the problem is
that we re-lookup it a few times, which is racy. We should instead track
the vma directly, but oh well we don't."]
v2:
* Reformat commit msg to 72 chars. (Lukas Wunner)
* Add third failure mode. (Lukas Wunner)
v5:
* Rebase on drm-intel-nightly 2015y-09m-01d-09h-06m-08s UTC,
rephrase commit message. (Jani Nicula)
v6:
* In intelfb_alloc, if __intel_framebuffer_create failed,
fb will be an ERR_PTR, thus not null. So in the failure
path we need to check for IS_ERR_OR_NULL to avoid calling
drm_framebuffer_remove on the ERR_PTR. (Lukas Wunner)
* Since this is init code a drm_framebuffer_unreference should
be all we need. drm_framebuffer_remove is for framebuffers
that userspace has created - and is getting somewhat
defeatured. (Daniel Vetter)
v7:
* Clarify why struct_mutex needs to be locked in the second half
of intelfb_create. (Daniel Vetter)
Fixes: 60a5ca015ffd ("drm/i915: Add locking around
framebuffer_references--") Reported-by: Lukas Wunner <lukas@wunner.de> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
[Lukas: Create v3 + v4 + v5 + v6 + v7 based on Tvrtko's v2] Signed-off-by: Lukas Wunner <lukas@wunner.de> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/47d4e88c91b3bf0f7a280cabec54c8c8cf0cf6f2.1446892879.git.lukas@wunner.de Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Lukas Wunner [Thu, 22 Oct 2015 11:37:18 +0000 (13:37 +0200)]
drm/i915: Fix double unref in intelfb_alloc failure path
In intelfb_alloc(), if the call to intel_pin_and_fence_fb_obj() fails,
the bo is unrefed twice: By drm_framebuffer_remove() and once more by
drm_gem_object_unreference(). Fix it.
drm/i915: On fb alloc failure, unref gem object where it gets refed
Currently when allocating a framebuffer fails, the gem object gets
unrefed at the bottom of the call stack in __intel_framebuffer_create,
not where it gets refed, which is in intel_framebuffer_create_for_mode
(via i915_gem_alloc_object) and in intel_user_framebuffer_create
(via drm_gem_object_lookup).
This invites mistakes: __intel_framebuffer_create is also called from
intelfb_alloc, and as discovered by Tvrtko Ursulin, a double unref
was introduced there with a8bb6818270c ("drm/i915: Fix error path leak
in fbdev fb allocation").
As suggested by Ville Syrjälä, fix the double unref and improve code
clarity by moving the unref away from __intel_framebuffer_create to
where the gem object gets refed.
Based on Tvrtko Ursulin's original v2.
v3: On fb alloc failure, unref gem object where it gets refed,
fix double unref in separate commit (Ville Syrjälä)
v4: Lock struct_mutex on unref (Chris Wilson)
v5: Rebase on drm-intel-nightly 2015y-09m-01d-09h-06m-08s UTC,
rephrase commit message (Jani Nicula)
In order to prepare for a link training with DDI, the state machine
would call intel_ddi_prepare_link_retrain(). To remove the dependency to
the hardware information, replace that direct call with a callback.
projects / karo-tx-linux.git / log