Anson Huang [Mon, 14 Oct 2013 19:20:52 +0000 (15:20 -0400)]
ENGR00283508-4 arm: dts: imx6sl: support kpp pin sleep mode
Improve those kpp pins pad setting with no_pad_ctrl defined,
actually they are using default pad setting, to support pin
mode switch, we need to set them manually.
As i.MX6SL EVK board is very sensitive to DSM power, so we
need to lower IO power of KPP pins:
serial: imx: optimization: remove the workqueues for DMA
I worried that the delay of the sdma_run_channel0() maybe too long for
interrupt context, so I added the workqueues for RX/TX DMA.
But tested with bluetooth device, I find that the delay of sdma_run_channel0()
is about 8us (tested in imx6dl sabreauto board). I think the delay
is acceptable.
This patch removes the RX/TX workqueues for DMA, it makes the
code more clear.
Robby Cai [Mon, 14 Oct 2013 03:32:25 +0000 (11:32 +0800)]
ENGR00283496 ARM: clk: imx6sl: update epdc pixel clock tree
Add CLK_SET_RATE_PARENT flag for epdc pixel clock to allow the rate change
operation to propagate up to the clock's parent in order to get desired rate.
Huang Shijie [Fri, 11 Oct 2013 07:39:07 +0000 (15:39 +0800)]
serial: imx: fix the wrong number of scatterlist entries when xmit->head is 0
When the (xmit->tail > xmit->head) is true and the xmit->head is 0,
we only need one DMA scatterlist in actually. Current code uses two DMA
scatterlists in this case, this is obviously wrong.
Huang Shijie [Thu, 10 Oct 2013 07:05:16 +0000 (15:05 +0800)]
serial: imx: check the DMA for imx_tx_empty
Assume the following situation:
If the DMA is enabled, and the a TX DMA operation is working,
But we have not issued the TX DMA operation (or we have issued the
TX DMA operation with dma_async_issue_pending(), but the DMA has not
started to move the data from the memory to the TXFIFO).
At this time, we may get the wrong status of the transmitter when we
call the imx_tx_empty. In such situation, only check the USR2_TXDC
does not enough for us.
This patch checks the DMA's situation, and return 0 when the TX DMA is
working.
Huang Shijie [Wed, 9 Oct 2013 07:13:23 +0000 (15:13 +0800)]
serial: imx: implement the flush_buffer hook
The current driver does not implement the flush_buffer hook for
uart_ops. When we enable the DMA for the driver, and test it with Bluetooth,
we may meet the following bug for TX:
[1] User application may call the flush operation at any time.
The uart_flush_buffer() calls the uart_circ_clear() to set
the xmit->head and xmit->tail with 0.
[2] The TX DMA callback can be called at any time too.
The dma_tx_call() will update the xmit->tail.
If [2] occurs just after the [1], we will get the wrong xmit->tail.
This patch implements the flush_buffer hook to fix this issue.
ENGR00281769 [iMX6SL] Allow uart to be sourced from 24MHz XTAL
In order to optmize low power IDLE numbers all PLLs should be in bypass.
On imx6sl, UART can be sourced directly from the 24MHz XTAL. Its frequency
is limited to 4MHz due to an internal divide by 6 divider.
For customer who don't require higher uart speeds add "uart_at_4M"
to the kernel command line.
Richard Zhu [Tue, 15 Oct 2013 02:44:54 +0000 (10:44 +0800)]
ahci: imx: setup power saving methods
In order to save power consumption as much as possible.
* Disable sata phy internal pll reference clock when sysetem enter
into suspend mode, enable it after resume.
* Setup module parameter used to enable imx ahci test power down
mode(PDDQ) or not, when there is no device detected on the port
* minor modifications:
- The format of the copyright is changed, because that the original
one can't pass fsl internal patch reivew without the character
'(c)'.
- Exports ahci_platform_ops and ahci_error_handler().
NOTE:
* The hot-plug can't be supported when PDDQ mode is ever enabled.
* module parameter usage how-to:
- default: enable PDDQ mode when no device detected.
- add "ahci-imx.hotplug=1" into kernel command line if your don't
want to enable PDDQ mode when no device detected on the port.
tj: Slightly updated description and comments.
Signed-off-by: Richard Zhu <r65037@freescale.com> Signed-off-by: Tejun Heo <tj@kernel.org>
This patch add MLB150 driver support.Copy files from 3.0.35 kernel.
* Using of_xxx API to get resource from dts
* Using devm_xxx API to simply the code
* Change clk_enable()/clk_disable() to clk_prepare_enable()/
clk_disable_unprepare()
* Fix some warning when compiling
* Fix issue when handling errors in mxc_mlb150_probe()
* Remove declaration of gpio_mlb_active(), gpio_mlb_inactive()
out of mxc_mlb.h, because the functions are not invoked.
* Add UAPI support.
Fugang Duan [Mon, 14 Oct 2013 08:52:32 +0000 (16:52 +0800)]
ENGR00283540-02: net: fec: use pinctrl PM helpers
when system suspend, need to set pins to low power state to
save IO power consumption, there are three states of pinctrl:
"default", "idle" and "sleep". Currently enet supports default
and sleep state.
Anson Huang [Sat, 12 Oct 2013 17:35:12 +0000 (13:35 -0400)]
ENGR00283540-01 dts:imx6sl: add fec sleep pinctrl for pin PM state
when system suspend, need to set pins to low power state to
save IO power consumption, there are three states of pinctrl:
"default", "idle" and "sleep". Currently enet supports default
and sleep state.
Linus Walleij [Wed, 5 Jun 2013 13:30:33 +0000 (15:30 +0200)]
drivers: pinctrl sleep and idle states in the core
If a device have sleep and idle states in addition to the
default state, look up these in the core and stash them in
the pinctrl state container.
Add accessor functions for pinctrl consumers to put the pins
into "default", "sleep" and "idle" states passing nothing but
the struct device * affected.
Solution suggested by Kevin Hilman, Mark Brown and Dmitry
Torokhov in response to a patch series from Hebbar
Gururaja.
Cc: Hebbar Gururaja <gururaja.hebbar@ti.com> Cc: Dmitry Torokhov <dmitry.torokhov@gmail.com> Cc: Stephen Warren <swarren@wwwdotorg.org> Acked-by: Wolfram Sang <wsa@the-dreams.de> Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Reviewed-by: Mark Brown <broonie@kernel.org> Reviewed-by: Kevin Hilman <khilman@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Robby Cai [Wed, 25 Sep 2013 05:35:46 +0000 (13:35 +0800)]
ENGR00281186 dmaengine: pxp: not fetch data from AS buffer if it's not used
There's no explicit BIT in PxP register to disable AS buffer.
The right way to disable AS is to set ULC to a higher value than the LRC.
It has been done once in probe time, but not in run time.
This could cause one potential problem because even when ULC, LRC
and buffer address is set to 0 PxP will still fetch one pixel data from addr 0.
This patch fixes it by set ULC higher than LRC for AS if it's not used (i.e.,
no alpha-blending) at run time.
ENGR00277792 video: mxsfb: Enable pan display function
- Add interrupt handle thread for vsync and frame done irq.
- Support MXCFB_WAIT_FOR_VSYNC call to get vsync signal
in fb_ioctl function.
- Add flip_sem semaphore to check last frame done interrupt
in pan display function.
- Add cur_blank variable to record current blank state.
- Move register_framebuffer function after lcdif controller
enabled, struct of fb_info and lcdif controller should ready
to work before register_framebuffer.
Hongzhang Yang [Thu, 10 Oct 2013 03:12:06 +0000 (11:12 +0800)]
ENGR00283192 Avoid vpu rmmod failure and modprobe warning
- Avoid vpu rmmod failure caused by regulator free failure
Do not call regulator_put because regulators returned from
devm_regulator_get are automatically regulator_put() on
driver detach
- Avoid vpu modprobe warning caused by unbalanced pm_runtime_enable
Add missing call to pm_runtime_disable
Signed-off-by: Hongzhang Yang <Hongzhang.Yang@freescale.com>
Huang Shijie [Wed, 26 Oct 2011 09:31:25 +0000 (17:31 +0800)]
ENGR00160834 UTP : replace kzalloc() with vmalloc()
When allocating large memory, such as 128K,
vmalloc() uses single page for the allocation process,
while kzalloc() has to consume a continuous pages for the allocation.
In low memory case, the kzalloc() may fails.
So use the vmalloc() instead.
Peter Chen [Tue, 22 Mar 2011 09:27:17 +0000 (17:27 +0800)]
ENGR00140950 mfg: fix the bug that ubiformat utility breaks utp protocol
ubiformat includes command, data, command periods,
it breaks utp protocol for PUT commands. So we add two operations to fix it.
One is sending busy to host before the data periods begins.
The second is adding a new command to waiting ubiformat's command period.
Signed-off-by: Li Xingyu <b02754@freescale.com> Signed-off-by: Peter Chen <peter.chen@freescale.com>
Frank Li [Thu, 3 Oct 2013 19:51:58 +0000 (14:51 -0500)]
ENGR00280494-2 Add config for mfgtools
Build in USB Mass storage
Enable CONFIG_FSL_UTP
Must list all gadgets in config file
otherwise CONFIG_USB_MASS_STORAGE becomes to m
+# CONFIG_USB_ZERO is not set
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_ETH is not set
+# CONFIG_USB_G_NCM is not set
+# CONFIG_USB_GADGETFS is not set
+# CONFIG_USB_FUNCTIONFS is not set
+CONFIG_USB_MASS_STORAGE=y
+CONFIG_FSL_UTP=y
+# CONFIG_USB_G_SERIAL is not set
+# CONFIG_USB_MIDI_GADGET is not set
+# CONFIG_USB_G_PRINTER is not set
+# CONFIG_USB_CDC_COMPOSITE is not set
+# CONFIG_USB_G_ACM_MS is not set
+# CONFIG_USB_G_MULTI is not set
+# CONFIG_USB_G_HID is not set
+# CONFIG_USB_G_DBGP is not set
+# CONFIG_USB_G_WEBCAM is not set
Nicolin Chen [Tue, 8 Oct 2013 08:39:39 +0000 (16:39 +0800)]
ENGR00281859-3 ASoC: fsl: Prepare dmaengine before submit it
ASRC and HDMI audio might meet unexpected stop, 'ctrl+z' for example,
and then disable its sdma channel. But after 'fg' resume, because sdma
channel's status has already been set into DMA_ERROR, we need to prepare
dmaengine again to clear its error state, otherwise sdma driver would
bypass its channel enabling and 'Input/Output error' would happen to
ALSA lib.
The combined prepare and submit are also being used in soc-dmaengine,
the common ASoC dmaengine driver.
And since we already use a proper way to handle sdma channel status,
there's no need to make an exception for HDMI any more, so drop it.
ENGR00281017 [MX6SL]Low power IDLE mode optimizations
Added a new bus freq mode - ultra_low_bus_freq_mode.
In this mode the ARM is the only bus master that is active and
the system is already in low power idle mode.
And when ARM executes WFI in this mode, we do some aggressive
power savings techinques like:
1. Drop DDR freq to 1MHz
2. Drop AHB freq to 3MHz
3. Float the DDR IO pads
4. If all PLLs are in bypass (which should be the case), do
some analog power saving options like reducing the OSC-bias current,
turning off the regular bandgap, disabling the regular 2P5, enabling
the weak 2p5 etc.
Enet get MAC address order:
From module parameters or kernel command line -> device tree ->
pfuse -> mac registers set by bootloader -> random mac address.
When there have no "fec.macaddr" parameters set in kernel command
line, enet driver get MAC address from device tree. And then if
the MAC address set in device tree and is valid, enet driver get
MAC address from device tree. Otherwise,enet get MAC address from
pfuse. So, in the condition, update the MAC address (read from pfuse)
to device tree.
ENGR00280852-9 mxc: asrc: Use threshold to clear dma request
Previously, we used sdma's event pending to forcibly re-schedule sdma
for work round, because sdma channel for ASRC input task would fail to
be opened due to its dma request always keeping high after ASRC opens
the pair, which cause sdma miss the trigger point of dma request.
Now, instead of using event pending, we clear the dma request on ASRC
driver side by setting its thresholds to an impossible trigger area
during its stall state. Since ASRC would stall its process when input
fifo is near empty or output fifo is near full, during the stall state,
the specific thresholds, 0 for input fifo and 63 for output fifo, would
never let asrc meet this condition. So dma request can be cleared and
raised again after we restore the true required thresholds.
Accordingly, since we don't need event pending any more, we dropped the
code from the sdma driver.
ENGR00280852-7 mxc: asrc: Only set ASRC to STALL level in start_conv()
We don't need to set ASRC to STALL level everytime, instead we only need
to do that at the beginning. If we insert null data into input fifo during
the sequence of valid datas, there would be a noise occur to it.
By doing this, we can assure ASRC would keep each period's perturbation of
output dma task within 8 sample sizes, which is the default value for last
period number. Thus we don't need to expand the last period number any more.
This patch also dropped some unused functions since the driver no long needs
them and replaced wrapped function for channel number configuration with direct
regmap_update_bits() to make the driver clean.
ENGR00280852-3 mxc: asrc: Use regmap to control register accessing
Dropped the legency readl/writel() and use regmap instead. Also removed
core clock's clk_prepare() and spin_lock()/unlock() outside regmap due to
regmap already has these features.
This patch also added a missing writable register to the regmap in order
to assure the regsiter updating success.
regmap: Make regmap-mmio usable from atomic contexts
regmap-mmio uses a spinlock with spin_lock() and spin_unlock() for locking.
To be able to use the regmap API from different contexts (atomic vs non-atomic),
without the risk of race conditions, we need to use spin_lock_irqsave() and
spin_lock_irqrestore() instead. A new field, the spinlock_flags field, is added
to regmap struct to store the flags between regmap_{,un}lock_spinlock(). The
spinlock_flags field itself is also protected by the spinlock.
Thanks to Stephen Warren for the suggestion of this particular solution.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Reviewed-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Nicolin Chen <b42378@freescale.com>
ENGR00281611 i2c: imx: update i2c clock divider for each transaction
i.MX6 I2C clk is from IPG_PERCLK which is sourced from IPG_CLK.
Under normal operation, IPG_CLK is 66MHz, ipg_perclk is at 22MHz.
In low bus freq mode, IPG_CLK is at 12MHz and IPG_PERCLK is down
to 4MHz. So the I2C driver must update the divider register for
each transaction when the current IPG_PERCLK is not equal to the
clock of previous transaction.
Robby Cai [Thu, 26 Sep 2013 09:57:18 +0000 (17:57 +0800)]
ENGR00281446 ARM: dts: imx6: correct the power supply node name for epdc
The naming convention for power supply node in DTS is "%s-supply".
With this patch regulator_get() will process in the DT way rather than
traditional way. This patch has no functional impact.
The overlay framebuffer's position and resolution are
set with two different APIs. They depend on each other to
make sure the overlay framebuffer window will not go out
of the background framebuffer window. Potentially, this
causes the overlay framebuffer's position or resolution
of the current video pipeline be impacted by the settings
of the last time. To setup the overlay fb from scratch
correctly, this patch takes the following steps:
- blank framebuffer
- set framebuffer position to the starting point
- reconfigure framebuffer
- set framebuffer position to a specific point
- unblank framebuffer
This procedure applies to non-overlay framebuffers as well.
Liu Ying [Thu, 26 Sep 2013 05:41:17 +0000 (13:41 +0800)]
ENGR00279204-1 mxc vout: reconfig fb when necessary
Users may call VIDIOC_S_CTRL or VIDIOC_S_CROP ioctrls
to update streaming parameters on-the-fly after video
has been streamed on, such as for rotation/output
resolution/overlay output position change. Any
unnecessary frame buffer reconfiguration would cause
a pair of frame buffer blank/unblank events happen and
even makes the background framebuffer show up for a
short period of time if the video is rendered on an
overlay framebuffer. This patch compares the last time
video output pipe line settings with the current ones
to determine whether frame buffer reconfiguration is
necessary or not.
ENGR00279946 dts: imx6qdl-sabreauto: add baseboard sd card slot support
NOTE since SD Card in main board takes a long route hence with
Drive Speed High 80 OHMS causing error on high speed cards.
Per suggestion DSE 40 OHMS is used.
Robby Cai [Sun, 22 Sep 2013 09:31:06 +0000 (17:31 +0800)]
ENGR00280140 pxp/v4l2: restore the display content after video playback finishes
After finish video playback, the last frame remains on the display.
It's because the UI display start address (smem_start) has been changed when
do video playback but not changed back again after the playback finishes.
From the function call point of view,
pxp_set_fbinfo() // pxp->fb.base tracks right addr for UI framebuffer
pxp_show_buf(toshow) // smem_start changed to v4l2 display addr
pxp_set_fbinfo() // pxp->fb.base changed to v4l2 display addr
pxp_show_buf(not toshow) // smem_start still equal to v4l2 display addr
// for pan_display
This patch fixes it by calling pxp_set_fbinfo once in open function.
ENGR00281036: [MX6SL]Align LPDDR2 freq change code to 8-byte boundary
This patch fixes 4 issues:
1. Add the .align 8 directive to the LPDDR2 freq change code,
else the fncpy() function fails and the kernel does not boot.
2. Loads the correct L2_BASE_ADDR into register in lpddr2 freq change code
3. Fix the warning in clk_imx6sl.c
4. Change dev_WARN to dev_info in busfreq-imx6.c.
ARM: dts: imx6q: fix the wrong offset of the Pad Mux register
The patch "0b7a76a ARM: dts: imx6q{dl}: add DTE pads for uart"
adds the DTE pads for uart. For PAD_EIM_D29, the offset of the
Pad Mux register should be 0x0c8, not 0x0c4.
ENGR00279545 [MX6x:Cpufreq] Initialize mutex before driver registration
The mutex, set_cpufreq_lock, should be initialized before the driver is
registered. Else if the default governor is set to performance or ondemand,
the cpufreq driver will try to set the freq to the max freq supported and
this will cause a crash during boot.
Robby Cai [Thu, 12 Sep 2013 11:11:54 +0000 (19:11 +0800)]
ENGR00279413 pxp/v4l2: get the right framebuffer start address at run time
Previously the driver gets the framebuffer start address at probe time.
But this address might be changed if the framebuffer drivers re-allocate
the frame buffers due to the application changes the yres_virtual.
As a result, some garbage data can be observed on display.
This patch adjusts the way to detect the start address at run time to
fix this problem.
Some boards use another WDOG reset source to reboot system in ldo-bypass mode.
We need add the property in board dts file so that we can easily know the
WDOG reset source currently.
For Sabresd, WDOG1 for ldo-enable mode(WDOG event), WDOG2 for ldo-bypass mode
(reset external pmic to trigger POR event).
For sl-evk board, there is no WDOG pin connected with external pmic as Sabresd
, because mx6sl boot at 400Mhz. Then both ldo-enable and ldo-bypass mode use
the common WDOG1 as reset source.
Robby Cai [Thu, 12 Sep 2013 06:39:57 +0000 (14:39 +0800)]
ENGR00279373 epdc: add GFP_KERNEL flag to make dma memory allocated from cma
Add GFP_KERNEL flag for dma_alloc_writecombine() and dma_alloc_coherent()
to make dma memory allocated via cma. Otherwise it's from dma pool whose
size is too small by default (256KB) and will cause allocation failure unless
use 'coherent_pool=xxM' in cmdline. We prefer cma now.
As we need to float DDR IO when entering DSM, so those registers
we need to access after DDR IO is floated must be contained in TLB,
otherwise, the TLB update may case DDR access and lead to
system hang. To make sure these registers' address is in TLB,
we need to flush TLB first then access them manually.
The following commit introduced a wrong sanity check for
the io_regulator which is intended to be got from device tree. a364635a535705a8c16df49ff9bc7b9362b083ec
Oliver Brown [Sun, 8 Sep 2013 20:05:28 +0000 (15:05 -0500)]
ENGR00278667-1 [mxc_v4l2_capture]: Add adv7180 driver in 3.10.9 Kernel
Copied file from 3.5.7 Kernel
commit de6459732a23402cbe520812bf4202299330fd68
Author: Oliver Brown <oliver.brown@freescale.com>
Date: Mon Jun 24 16:41:17 2013 -0500
Added missing call to clk_disable_unprepare() in adv7180_probe.
Signed-off-by: Oliver Brown <oliver.brown@freescale.com>
-Added function and file name to some error messages that are
in multiple places.
-Added calls to clk_prepare_enable() and clk_disable_unprepare()
in ov5640_probe() to manage the sensor clock.
-Added missing sanity check for "io_regulator"
-Fixed several whitespace errors
Signed-off-by: Oliver Brown <oliver.brown@freescale.com>
We observed on some sd3.0 cards(Toshiba SDHC U1) that it may require
to reset host controller before sending the next tuning command
or the tuning may fail and cause the card can not work on uhs mode.
The root cause why the card fails on tuning without reset is still unknow.
This could be treated as a workaround before finding root cause.
ENGR00278646-8 mmc: sdhci-esdhc: correct pre_div for imx6q
According to spec, the pre_div for imx6q should be 1, or the biggest clock
rate we can get is a half of host clock rate.
This may cause we can not get the proper clock rate as we want.
e.g. if the desired clock is 200Mhz, however, the host clock is 200Mhz too,
then it causes the actual clock we get is 100Mhz due to pre_div is 2.
projects / karo-tx-linux.git / log