In the old times, the whole idle task was considered
as an RCU quiescent state. But as RCU became more and
more successful overtime, some RCU read side critical
section have been added even in the code of some
architectures idle tasks, for tracing for example.
So nowadays, rcu_idle_enter() and rcu_idle_exit() must
be called by the architecture to tell RCU about the part
in the idle loop that doesn't make use of rcu read side
critical sections, typically the part that puts the CPU
in low power mode.
This is necessary for RCU to find the quiescent states in
idle in order to complete grace periods.
Add this missing pair of calls in the m68k's idle loop.
Reported-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com> Signed-off-by: Frederic Weisbecker <fweisbec@gmail.com> Cc: Geert Uytterhoeven <geert@linux-m68k.org> Cc: m68k <linux-m68k@lists.linux-m68k.org> Cc: 3.2.x.. <stable@vger.kernel.org> Cc: Paul E. McKenney <paulmck@linux.vnet.ibm.com> Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
powerpc/mpc85xx: Add new ext fields to Integrated FLash Controller
Freescale's Integrated Flash controller(IFC) v1.1.0 supports 40 bit
address bus width.
In case more than 32 bit address is used, the EXT registers should be set.
Add support of ext registers.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Olivia Yin [Thu, 9 Aug 2012 07:42:36 +0000 (15:42 +0800)]
powerpc/e5500: Add Power ISA properties to comply with ePAPR 1.1
power-isa-version and power-isa-* are cpu node general properties defined
in ePAPR.
If the power-isa-version property exists, then for each category from the
Categories section of Book I of the Power ISA version indicated, the
existence of a property named power-isa-[CAT], where [CAT] is the
abbreviated category name with all uppercase letters converted to
lowercase, indicates that the category is supported by the implementation.
This patch update all the e5500 platforms.
Signed-off-by: Liu Yu <yu.liu@freescale.com> Signed-off-by: Olivia Yin <hong-hua.yin@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Olivia Yin [Thu, 9 Aug 2012 07:42:35 +0000 (15:42 +0800)]
powerpc/e500mc: Add Power ISA properties to comply with ePAPR 1.1
power-isa-version and power-isa-* are cpu node general properties defined
in ePAPR.
If the power-isa-version property exists, then for each category from the
Categories section of Book I of the Power ISA version indicated, the
existence of a property named power-isa-[CAT], where [CAT] is the
abbreviated category name with all uppercase letters converted to
lowercase, indicates that the category is supported by the implementation.
The patch update all the e500mc platforms.
Signed-off-by: Liu Yu <yu.liu@freescale.com> Signed-off-by: Olivia Yin <hong-hua.yin@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Olivia Yin [Thu, 9 Aug 2012 07:42:34 +0000 (15:42 +0800)]
powerpc/e500v2: Add Power ISA properties to comply with ePAPR 1.1
power-isa-version and power-isa-* are cpu node general properties defined
in ePAPR.
If the power-isa-version property exists, then for each category from the
Categories section of Book I of the Power ISA version indicated, the
existence of a property named power-isa-[CAT], where [CAT] is the
abbreviated category name with all uppercase letters converted to
lowercase, indicates that the category is supported by the implementation.
The patch update all e500v2 platforms.
Signed-off-by: Liu Yu <yu.liu@freescale.com> Signed-off-by: Olivia Yin <hong-hua.yin@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Varun Sethi [Wed, 8 Aug 2012 04:06:09 +0000 (09:36 +0530)]
powerpc/mpic: FSL MPIC error interrupt support.
All SOC device error interrupts are muxed and delivered to the core
as a single MPIC error interrupt. Currently all the device drivers
requiring access to device errors have to register for the MPIC error
interrupt as a shared interrupt.
With this patch we add interrupt demuxing capability in the mpic driver,
allowing device drivers to register for their individual error interrupts.
This is achieved by handling error interrupts in a cascaded fashion.
MPIC error interrupt is handled by the "error_int_handler", which
subsequently demuxes it using the EISR and delivers it to the respective
drivers.
The error interrupt capability is dependent on the MPIC EIMR register,
which was introduced in FSL MPIC version 4.1 (P4080 rev2). So, error
interrupt demuxing capability is dependent on the MPIC version and can
be used for versions >= 4.1.
Jia Hongtao [Fri, 3 Aug 2012 10:14:10 +0000 (18:14 +0800)]
powerpc/swiotlb: Enable at early stage and disable if not necessary
Remove the dependency on PCI initialization for SWIOTLB initialization.
So that PCI can be initialized at proper time.
SWIOTLB is partly determined by PCI inbound/outbound map which is assigned
in PCI initialization. But swiotlb_init() should be done at the stage of
mem_init() which is much earlier than PCI initialization. So we reserve the
memory for SWIOTLB first and free it if not necessary.
All boards are converted to fit this change.
Signed-off-by: Jia Hongtao <B38951@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Acked-by: Tony Breeds <tony@bakeyournoodle.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
powerpc/booke: Separate out restore_e5500/setup_e5500 routines.
For the 64 bit case separate out e5500 cpu_setup and cpu_restore functions.
The cpu_setup function (for the primary core) is passed the cpu_spec
pointer, which is not there in case of the cpu_restore function. Also, in
our case we will have to manipulate the CPU_FTR_EMB_HV flag on the primary
core.
Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
powerpc/booke: Merge the 32 bit e5500/e500mc cpu setup code.
Merge the 32 bit cpu setup code for e500mc/e5500 and define the
"cpu_restore" routine (for e5500/e6500) only for the 64 bit case. The
cpu_restore routine is used in the 64 bit case for setting up the secondary
cores.
Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Add support to disable and re-enable individual cores at runtime on
MPC85xx/QorIQ SMP machines. Currently support e500v1/e500v2 core.
MPC85xx machines use ePAPR spin-table in boot page for CPU kick-off. This
patch uses the boot page from bootloader to boot core at runtime. It
supports 32-bit and 36-bit physical address.
Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Jin Qing <b24347@freescale.com> Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Do hardware timebase sync. Firstly, stop all timebases, and transfer the
timebase value of the boot core to the other core. Finally, start all
timebases.
Only apply to dual-core chips, such as MPC8572, P2020, etc.
Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
powerpc/smp: add generic_set_cpu_up() to set cpu_state as CPU_UP_PREPARE
In the case of cpu hotplug, the cpu_state should be set to CPU_UP_PREPARE
when kicking cpu. Otherwise, the cpu_state is always CPU_DEAD after
calling generic_set_cpu_dead(), which makes the delay in generic_cpu_die()
not happen.
Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Timur Tabi [Mon, 23 Jul 2012 23:12:29 +0000 (18:12 -0500)]
powerpc/85xx: introduce support for the Freescale / iVeia P1022RDK
The Freescale / iVeia P1022RDK reference board is a small-factor board
with a Freescale P1022 SOC. It includes:
1) 512 MB 64-bit DDR3-800 (max) memory
2) 8MB SPI serial flash memory for boot loader
3) Bootable 4-bit SD/MMC port
4) Two 10/100/1000 Ethernet connectors
5) One SATA port
6) Two USB ports
7) One PCIe x4 slot
8) DVI video connector
9) Audio input and output jacks, powered by a Wolfson WM8960 codec.
Unlike the P1022DS, the P1022RDK does not have any localbus devices,
presumably because of the localbus / DIU multiplexing restriction of
the P1022 SOC.
Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Timur Tabi [Thu, 26 Jul 2012 15:08:54 +0000 (10:08 -0500)]
powerpc/85xx: Add support for P5040DS board
Add support for the Freescale P5040DS Reference Board ("Superhydra"), which
is similar to the P5020DS. Features of the P5040 are listed below, but
not all of these features (e.g. DPAA networking) are currently supported.
Four P5040 single-threaded e5500 cores built
Up to 2.4 GHz with 64-bit ISA support
Three levels of instruction: user, supervisor, hypervisor
CoreNet platform cache (CPC)
2.0 MB configures as dual 1 MB blocks hierarchical interconnect fabric
Two 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
support Up to 1600MT/s
Memory pre-fetch engine
DPAA incorporating acceleration for the following functions
Packet parsing, classification, and distribution (FMAN)
Queue management for scheduling, packet sequencing and
congestion management (QMAN)
Hardware buffer management for buffer allocation and
de-allocation (BMAN)
Cryptography acceleration (SEC 5.0) at up to 40 Gbps SerDes
20 lanes at up to 5 Gbps
Supports SGMII, XAUI, PCIe rev1.1/2.0, SATA Ethernet interfaces
Two 10 Gbps Ethernet MACs
Ten 1 Gbps Ethernet MACs
High-speed peripheral interfaces
Two PCI Express 2.0/3.0 controllers
Additional peripheral interfaces
Two serial ATA (SATA 2.0) controllers
Two high-speed USB 2.0 controllers with integrated PHY
Enhanced secure digital host controller (SD/MMC/eMMC)
Enhanced serial peripheral interface (eSPI)
Two I2C controllers
Four UARTs
Integrated flash controller supporting NAND and NOR flash
DMA
Dual four channel
Support for hardware virtualization and partitioning enforcement
Extra privileged level for hypervisor support
QorIQ Trust Architecture 1.1
Secure boot, secure debug, tamper detection, volatile key storage
Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kim Phillips [Thu, 26 Jul 2012 15:08:53 +0000 (10:08 -0500)]
powerpc/85xx: add Freescale P5040 SOC and SEC v5.2 device trees
Add device tree (dtsi) files for the Freescale P5040 SOC. Since this
SOC introduces SEC v5.2, add the dtsi file for that also.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Timur Tabi [Fri, 13 Jul 2012 22:40:43 +0000 (17:40 -0500)]
powerpc/85xx: remove P1020RDB and P2020RDB CAMP device trees
We only need two examples of CAMP device trees in the upstream kernel.
Co-operative Asymmetric Multi-Processing (CAMP) is a technique where two
or more operating systems (typically multiple copies of the same Linux
kernel) are loaded into memory, and each kernel is given a subset of the
available cores to execute on. For example, on a four-core system, one
kernel runs on cores 0 and 1, and the other runs on cores 2 and 3.
The devices are also partitioned among the operating systems, and this is
done with customized device trees. Each kernel gets its own device tree
that has only the devices that it should know about.
Unfortunately, this approach is very hackish. The kernels are trusted to
only access devices in their respective device trees, and the partitioning
only works for devices that can be handled. Crafting the device trees is a
tricky process, and getting U-Boot to load and start all kernels is
cumbersome.
But most importantly, each CAMP setup is very application-specific, since
the actual partitioning of resources is done in the DTS by the system
designer. Therefore, it doesn't make a lot of sense to have a lot of CAMP
device trees, since we only expect them to be used as examples.
Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Tiejun Chen [Tue, 7 Aug 2012 01:59:40 +0000 (09:59 +0800)]
booke/wdt: some ioctls do not return values properly
Fix some booke wdt ioctls return value error.
Signed-off-by: Tiejun Chen <tiejun.chen@windriver.com> Acked-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Jia Hongtao [Fri, 3 Aug 2012 10:14:09 +0000 (18:14 +0800)]
powerpc/fsl-pci: Only scan PCI bus if configured as a host
We change fsl_add_bridge to return -ENODEV if the controller is working in
agent mode. Then check the return value of fsl_add_bridge to guarantee
that only successfully added host bus will be scanned.
Signed-off-by: Jia Hongtao <B38951@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Gabor Juhos [Thu, 23 Aug 2012 13:35:26 +0000 (15:35 +0200)]
MIPS: pci-ar724x: avoid data bus error due to a missing PCIe module
If the controller has no PCIe module attached, accessing of the device
configuration space causes a data bus error. Avoid this by checking the
status of the PCIe link in advance, and indicate an error if the link
is down.
David Daney [Tue, 21 Aug 2012 18:45:12 +0000 (11:45 -0700)]
netdev: octeon_mgmt: Make multi-line comment style consistent.
No code changes. Recent patches have used the netdev style multi-line
comment formatting, making the style inconsistent within octeon_mgmt.c
Update the remaining comment blocks to achieve style harmony.
Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Cc: David S. Miller <davem@davemloft.net> Cc: netdev@vger.kernel.org Cc: linux-kernel@vger.kernel.org,
Patchwork: https://patchwork.linux-mips.org/patch/4289/ Acked-by: David S. Miller <davem@davemloft.net> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
David Daney [Tue, 21 Aug 2012 18:45:11 +0000 (11:45 -0700)]
netdev: octeon_mgmt: Remove some useless 'inline'
Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Cc: David S. Miller <davem@davemloft.net> Cc: netdev@vger.kernel.org Cc: linux-kernel@vger.kernel.org,
Patchwork: https://patchwork.linux-mips.org/patch/4288/ Acked-by: David S. Miller <davem@davemloft.net> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
David Daney [Tue, 21 Aug 2012 18:45:10 +0000 (11:45 -0700)]
netdev: octeon_mgmt: Cleanup and modernize MAC address handling.
Use eth_mac_addr(), and generate a random address if none is otherwise
assigned.
Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Cc: David S. Miller <davem@davemloft.net> Cc: netdev@vger.kernel.org Cc: linux-kernel@vger.kernel.org,
Patchwork: https://patchwork.linux-mips.org/patch/4287/ Acked-by: David S. Miller <davem@davemloft.net> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
David Daney [Tue, 21 Aug 2012 18:45:09 +0000 (11:45 -0700)]
netdev: octeon_mgmt: Set the parent device.
This establishes useful links in sysfs.
Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Cc: David S. Miller <davem@davemloft.net> Cc: netdev@vger.kernel.org Cc: linux-kernel@vger.kernel.org, Acked-by: David S. Miller <davem@davemloft.net>
Patchwork: https://patchwork.linux-mips.org/patch/4286/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
David Daney [Tue, 21 Aug 2012 18:45:08 +0000 (11:45 -0700)]
netdev: octeon_mgmt: Improve ethtool_ops.
Correctly show no link when the interface is down, and return
-EOPNOTSUPP for things that don't work. This quiets the ethtool
program when run on down interfaces.
Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Cc: David S. Miller <davem@davemloft.net> Cc: netdev@vger.kernel.org Cc: linux-kernel@vger.kernel.org,
Patchwork: https://patchwork.linux-mips.org/patch/4284/ Acked-by: David S. Miller <davem@davemloft.net> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Octeon cn6XXX models have timestamp support on the mgmt ports, so hook
it up.
Signed-off-by: Chad Reese <kreese@caviumnetworks.com> Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Cc: David S. Miller <davem@davemloft.net> Cc: netdev@vger.kernel.org Cc: linux-k3rnel@vger.kernel.org,
Patchwork: https://patchwork.linux-mips.org/patch/4285/ Acked-by: David S. Miller <davem@davemloft.net> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
David Daney [Tue, 21 Aug 2012 18:45:06 +0000 (11:45 -0700)]
netdev: octeon_mgmt: Add support for 1Gig ports.
The original hardware only supported 10M and 100M. Later versions
added 1G support. Here we update the driver to make use of this.
Also minor logic clean-ups for testing PHY registration error codes
and TX complete high water marks.
Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Cc: David S. Miller <davem@davemloft.net> Cc: netdev@vger.kernel.org Cc: linux-kernel@vger.kernel.org,
Patchwork: https://patchwork.linux-mips.org/patch/4283/ Acked-by: David S. Miller <davem@davemloft.net> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
David Daney [Tue, 21 Aug 2012 18:45:05 +0000 (11:45 -0700)]
MIPS: Octeon: Add octeon_io_clk_delay() function.
Also cleanup and fix octeon_init_cvmcount()
Signed-off-by: David Daney <ddaney@caviumnetworks.com> Cc: linux-mips@linux-mips.org Cc: David S. Miller <davem@davemloft.net> Cc: netdev@vger.kernel.org Cc: linux-kernel@vger.kernel.org,
Patchwork: https://patchwork.linux-mips.org/patch/4282/ Acked-by: David S. Miller <davem@davemloft.net> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Erroneously the DWMAC_CORE_3_40 was set to 34 instead of 0x34.
This can generate problems when run on old chips because
the driver assumes that there are the extra 16 regs available
for perfect filtering.
Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Cc: Gianni Antoniazzi <gianni.antoniazzi-ext@st.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Eric Dumazet [Tue, 21 Aug 2012 20:48:29 +0000 (20:48 +0000)]
ipv4: properly update pmtu
Sylvain Munault reported following info :
- TCP connection get "stuck" with data in send queue when doing
"large" transfers ( like typing 'ps ax' on a ssh connection )
- Only happens on path where the PMTU is lower than the MTU of
the interface
- Is not present right after boot, it only appears 10-20min after
boot or so. (and that's inside the _same_ TCP connection, it works
fine at first and then in the same ssh session, it'll get stuck)
- Definitely seems related to fragments somehow since I see a router
sending ICMP message saying fragmentation is needed.
- Exact same setup works fine with kernel 3.5.1
Problem happens when the 10 minutes (ip_rt_mtu_expires) expiration
period is over.
ip_rt_update_pmtu() calls dst_set_expires() to rearm a new expiration,
but dst_set_expires() does nothing because dst.expires is already set.
It seems we want to set the expires field to a new value, regardless
of prior one.
With help from Julian Anastasov.
Reported-by: Sylvain Munaut <s.munaut@whatever-company.com> Signed-off-by: Eric Dumazet <edumazet@google.com> CC: Julian Anastasov <ja@ssi.bg> Tested-by: Sylvain Munaut <s.munaut@whatever-company.com> Signed-off-by: David S. Miller <davem@davemloft.net>
David Daney [Wed, 22 Aug 2012 19:25:07 +0000 (12:25 -0700)]
spi: Add SPI master controller for OCTEON SOCs.
Add the driver, link it into the kbuild system and provide device tree
binding documentation.
Signed-off-by: David Daney <david.daney@cavium.com> Acked-by: Grant Likely <grant.likely@secretlab.ca>
Patchwork: http://patchwork.linux-mips.org/patch/4292/ Signed-off-by: John Crispin <blogic@openwrt.org>
David Daney [Fri, 11 May 2012 21:34:45 +0000 (14:34 -0700)]
MIPS: OCTEON: Add register definitions for SPI host hardware.
Needed by SPI driver.
Signed-off-by: David Daney <david.daney@cavium.com>
Patchwork: http://patchwork.linux-mips.org/patch/3796/ Signed-off-by: John Crispin <blogic@openwrt.org>
Florian Fainelli [Tue, 31 Jan 2012 17:18:45 +0000 (18:18 +0100)]
MIPS: introduce CPU_R4K_CACHE_TLB
R4K-style CPUs having common code to support their caches and tlb have this
boolean defined by default. Allows us to remove some lines in
arch/mips/mm/Makefile.
Signed-off-by: Florian Fainelli <florian@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/3328/ Signed-off-by: John Crispin <blogic@openwrt.org>
projects / karo-tx-linux.git / log