Oliver Brown [Sun, 8 Sep 2013 20:05:28 +0000 (15:05 -0500)]
ENGR00278667-1 [mxc_v4l2_capture]: Add adv7180 driver in 3.10.9 Kernel
Copied file from 3.5.7 Kernel
commit de6459732a23402cbe520812bf4202299330fd68
Author: Oliver Brown <oliver.brown@freescale.com>
Date: Mon Jun 24 16:41:17 2013 -0500
Added missing call to clk_disable_unprepare() in adv7180_probe.
Signed-off-by: Oliver Brown <oliver.brown@freescale.com>
-Added function and file name to some error messages that are
in multiple places.
-Added calls to clk_prepare_enable() and clk_disable_unprepare()
in ov5640_probe() to manage the sensor clock.
-Added missing sanity check for "io_regulator"
-Fixed several whitespace errors
Signed-off-by: Oliver Brown <oliver.brown@freescale.com>
We observed on some sd3.0 cards(Toshiba SDHC U1) that it may require
to reset host controller before sending the next tuning command
or the tuning may fail and cause the card can not work on uhs mode.
The root cause why the card fails on tuning without reset is still unknow.
This could be treated as a workaround before finding root cause.
ENGR00278646-8 mmc: sdhci-esdhc: correct pre_div for imx6q
According to spec, the pre_div for imx6q should be 1, or the biggest clock
rate we can get is a half of host clock rate.
This may cause we can not get the proper clock rate as we want.
e.g. if the desired clock is 200Mhz, however, the host clock is 200Mhz too,
then it causes the actual clock we get is 100Mhz due to pre_div is 2.
ENGR00278646-6 sdhci: sdhci-esdhci-imx: add sd3.0 clock tuning support
Freescale i.MX6Q/DL uSDHC clock tuning progress is a little different from
the standard tuning process defined in host controller spec v3.0.
Thus we use platform_execute_tuning instead of standard sdhci tuning.
The main difference are:
1) not only generate Buffer Read Ready interrupt when tuning is performing.
It generates all other DATA interrupts like the normal data command.
2) SDHCI_CTRL_EXEC_TUNING is not automatically cleared by HW,
instead it's controlled by SW.
3) SDHCI_CTRL_TUNED_CLK is not automatically set by HW,
it's controlled by SW.
4) the clock delay for every tuning is set by SW.
ENGR00278646-4 sdhci: sdhci-esdhc-imx: support real clock on and off for imx6q
The signal voltage switch follow requires to shutdown and output
clock in a specific sequence according to standard host controller
v3.0 spec. In that timing, the card must really receive clock or not.
However, for i.MX6Q, the uSDHC will not output clock even the clock
is enabled until there is command or data in transfer on the bus,
which will then cause singal voltage switch always to fail.
For i.MX6Q, we clear ESDHC_VENDOR_SPEC_FRC_SDCLK_ON bit to let
controller to gate off clock automatically and set that bit
to force clock output if clock is on.
ENGR00278646-3 mmc: sdhci-esdhci: move common esdhc_set_clock to platform driver
We need a lot of imx6 specific things into common esdhc_set_clock
for support SD3.0 and eMMC DDR mode which is not needed for power pc
platforms, so esdhc_set_clock seems not so common anymore.
Instead of keeping add platform specfics things into this common API,
we choose to move that code into platform driver itself to handle.
This can also exclude the dependency between imx and power pc on this
headfile and is easy for maintain in the future.
ENGR00278646-1 mmc: sdhci: add hooks for platform specific tuning
The tuning of some platforms may not follow the standard host control
spec v3.0, e.g. Freescale uSDHC on i.MX6Q/DL.
Add a hook here to allow execute platform specific tuning instead of
standard host controller tuning.
Robby Cai [Wed, 11 Sep 2013 05:27:59 +0000 (13:27 +0800)]
ENGR00279087-2 csi_v4l2_capture: move int_dev_init() to open function
By later initialization for camera dev (to call int_dev_init), the driver
works well whether the master (csi_v4l2_capture) or the slave (ov5640)
has been attached first. In this way, the driver can stick to the philosophy
for the V4L2_INT_DEVICE framework (the attach sequence shouldn't matter).
-Added function and file names to error messages that are similar
-Changed mxc_v4l_open to use clk_prepare_enable()
-Changed mxc_v4l_open to use clk_disable_unprepare()
Signed-off-by: Oliver Brown <oliver.brown@freescale.com>
Copied mipi_csi.h from:
commit 50ca92f4010a93be265de7aad501b4dcae095a63
Author: Sheng Nan <b38800@freescale.com>
Date: Thu Mar 7 13:39:54 2013 +0800
ARM: include: remove definition of mipi-csi2 platform data
Other files copied files from:
commit 1fb93870965b7d8d67b4db6233a30c06d82f84fc
Author: Liu Ying <Ying.Liu@freescale.com>
Date: Thu Mar 21 12:15:52 2013 +0800
MIPI-CSI2:Fix a build warning
- Changed includes files for 3.10
- Dropped deprecated __devexit
- Added generic error message if probe fails
- Added configuration and set default to 'n'
Signed-off-by: Oliver Brown <oliver.brown@freescale.com>
Oliver Brown [Sun, 8 Sep 2013 16:37:14 +0000 (11:37 -0500)]
ENGR00278683-1 [iMX6DLQ]: Add IOMUX configuration for IPU1 CSI0
Add IOMUX configuration for IPU1 CSI0 for SabreSD and SabreAuto. This
enables parallel CSI port required for OV564x on SabreSD and ADV7180
on SabreAuto.
Signed-off-by: Oliver Brown <oliver.brown@freescale.com>
ENGR00278967 ASoC: fsl: Fix null pointer when rmmod snd-soc-imx-hdmi
When rmmod snd-soc-imx-hdmi if loadable module feature of HDMI audio
is being used, there would be a kernel dump promt:
Unable to handle kernel NULL pointer dereference at virtual address
This was caused by inappropriate priv pointer fetching, thus fix it.
Acked-by: Wang Shengjiu <b02247@freescale.com> Signed-off-by: Nicolin Chen <b42378@freescale.com>
According to the help text in the config SWP_EMULATE in arch/arm/mm/Kconfig:
"In some older versions of glibc [<=2.8] SWP is used during futex trylock()
operations with the assumption that the code will not be preempted. This
invalid assumption may be more likely to fail with SWP emulation enabled,
leading to deadlock of the user application."
The audio codec toolchain version is gcc-4.1.1-glibc-2.4, we need turn off
the CONFIG_SWP_EMULATE in the imx_v7_defconfig.
Signed-off-by: Shengjiu Wang <b02247@freescale.com>
ENGR00277382-2 [MX6SL] Add WaIT mode support for MX6SL.
Enable WAIT mode support for MX6SL. Need to ensure that the
ARM:IPG clock ratio is maintained at 12:5 when WFI is executed.
This is the fix for the WAIT mode issue on MX6SL.
Set AHB to 132Mhz at boot, which is the recommended freq for AHB.
ENGR00277382-1 [MX6SL] Ensure that PLL1 and PLL2 are always enabled.
Need to ensure that PLL1 and PLL2 have the enabled bit set even when
the PLL is powered down and disabled.
1. Modifications to the ARM_PODF bits in the CCM require PLL1 to be enabled.
2. PLL2 will be set to bypass and enabled state (can be powered down) in low
power IDLE mode.
ENGR00269945: ARM: imx6: add the secondary sabreauto dts for pin conflict
The patch is to solve the pin conflicts between devices that are
currently added in imx6qdl-sabreauto dts file. It has ecspi1, i2c3, and
uart3 enabled while gpmi and weim disabled in the primary
imx6qdl-sabreauto.dtsi, and creates the secondary
imx6q/dl-sabreauto dts to have gpmi and weim enabled while others
disabled. Since usbh1 and usbotg depend on GPIO from max7310 on i2c3,
they have to be disabled as well in the secondary sabreauto dts files.
It's basically a revert of commit fc52e42 (ENGR00269945: ARM: imx6:
remove sabresd hdcp dts files).
As we agree that maintaining multiple dts files for internal tree should
not be a problem, let's add the hdcp dts files back as the solution to
hdcp pin conflict.
Jason Liu [Thu, 5 Sep 2013 23:36:10 +0000 (07:36 +0800)]
ENGR00278489 imx: i.mx6d/q: disable the double linefill feature of PL310
The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0
The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2
But according to ARM PL310 errata: 752271
ID: 752271: Double linefill feature can cause data corruption
Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2
Workaround: The only workaround to this erratum is to disable the
double linefill feature. This is the default behavior.
without this patch, you will meet the following error when run the
memtester application at: http://pyropus.ca/software/memtester/
FAILURE: 0x00100000 != 0x00200000 at offset 0x01365664.
FAILURE: 0x00100000 != 0x00200000 at offset 0x01365668.
FAILURE: 0x00100000 != 0x00200000 at offset 0x0136566c.
FAILURE: 0x00100000 != 0x00200000 at offset 0x01365670.
FAILURE: 0x00100000 != 0x00200000 at offset 0x01365674.
FAILURE: 0x00100000 != 0x00200000 at offset 0x01365678.
FAILURE: 0x00100000 != 0x00200000 at offset 0x0136567c.
Robby Cai [Tue, 3 Sep 2013 09:42:22 +0000 (17:42 +0800)]
ENGR00275034-5 ARM: imx_v7_defconfig: enable camera and v4l2 capture support
Enable the following options on imx6sl
CONFIG_VIDEO_V4L2_INT_DEVICE=y
CONFIG_VIDEO_MXC_CAPTURE=y
CONFIG_VIDEO_MXC_CSI_CAMERA=y
CONFIG_MXC_CAMERA_OV5640=y
This patch also does
- use module_i2c_driver() instead of module_init/exit.
- set the regulator reference pointer to NULL if it's not found in DT.
Otherwise call regulator_enable/disable() on it will cause dump
since the codes only check the regulator against NULL before the call
and it's not NULL but still invalid.
- drop gpo regulator definition and operations since it's of no use
Robby Cai [Thu, 29 Aug 2013 07:39:12 +0000 (15:39 +0800)]
ENGR00275034-1 media: Add CSI/CSI v4l2 capture driver support
- change the includes
<asm/uaccess.h> to <linux/uaccess.h>
<mach/ipu-v3.h> to <linux/ipu-v3.h>
<mach/dma.h> to <linux/platform_data/dma-imx.h>
- add an extra parameter for device_prep_slave_sg() as the prototype's changed.
- drop csi_mclk_recalc() func since there's no divider in CSI module
- drop deprecated __devinit, __devexit and __devexit_p
- use module_platform_driver()
- use of_match_table()
- replace ioremap() with devm_ioremap()
- replace clk_get() with devm_clk_get()
- replace clk_enable/disable() with clk_prepare_enable/clk_disable_unprepare()
- add check for no camera attached on board
- drop function csi_mclk_enable(), csi_mclk_enable() in fsl_csi.c,
and move clock enable/disable to csi_v4l2_capture.c
ENGR00277864 input: mma8450: Add chip id check in probe
Add chip ID check in probe function. The mma8450 is
on the E-INK daughter board. When the daughter board
is not pluged, there would be polling error log
continuously. Add the check to avoid this.
Richard Zhu [Fri, 6 Sep 2013 04:33:31 +0000 (12:33 +0800)]
ENGR00278492 imx: pcie: delay is required after REF_CLK_EN is set
delay is required after REF_CLK_EN of GPR1 is set.
otherwise, system would be hang when access the registers
of PCIe RC when the EARLY_PRINTK is not enabled.
ENGR00277843-04 ARM: dts: Add sii902x in imx6sl evk dts
- Add sii902x driver to imx6sl-evk.dts
- Set LCD_RESET pin work in GPIO mode, the pin is not
use by imx6sl evk lcd panel.
- Enable sii902x in imx_v7_defconfig
ENGR00277843-02 imx6sl: Enable sii902x hdmi function
- Add sii902x hdmi chip driver.
- Sii902x initialized as I2C device.
- Support resolution change by application or FB command line.
- Max support resolution 1080p60.
- Support read EDID from hdmi sink.
- Support hdmi cable hotplug.
- Support default video mode read from dts.
ENGR00277843-01 mxsfb: Allocate frame buffer from DMA pool
- Original frame buffer size is fixed in SZ_2M when driver probing,
that can not support more resolution, such as 720p and 1080p.
Add function mxsfb_map_videomem/mxsfb_unmap_videomem to replace
fixed frame buffer size. Frame buffer size can change with resolution
change and application requirement.
- Add fb_mmap function implement.
- Remove member variable sync from struct mxsfb_info, align the sync
definition with mxc_cea_mode[] in mxc_edid.c.
- Set recovery from underflow bit.
- Fix xres_virtual yres_virtual check issue in function mxsfb_check_var().
Use platform_device_add() which can pass drvdata correctly: previously
we register the dma_dev first and pass its drvdata, but this would fail
to pass its drvdata correctly when using loadable module, because the
probe() hdmi dma driver would be executed right after the register()
and before set_drvdata(). Then the drvdata actually failed to be set
to the hdmi dma driver. While platform_device_add() has no such issue
because it would finish the set_drvdata() before its execution.
This patch also move codec driver registering into CPU DAI driver.
When using autoload module, the codec driver would alwasy fail to
be detected due to its registering located in manchine driver.
Thus move this to CPU DAI driver.
ENGR00277715-8 ARM: dts: Add WM8962 support for imx6sl-evk
Add WM8962 support for imx6sl-evk:
* Add missing baud clock for ssi
* Drop fifo-depth which would cause odd-number watermark
* Add pinctrl group for audmux on evk board
* Add WM8962-related devictree binding for evk board
ENGR00277715-2 ASoC: fsl: Drop constraint in startup() of ssi driver
The constraint would disavow two simultaineous streams, eg: arecord | aplay.
Since the hw_params() have the SSIEN checking, the stccr register would not
be modified during a actual procedure of one stream, we can safely drop this
one in startup().
Acked-by: Wang Shengjiu <b02247@freescale.com> Signed-off-by: Nicolin Chen <b42378@freescale.com>
Peter Chen [Wed, 4 Sep 2013 07:06:21 +0000 (15:06 +0800)]
ENGR00278097-2 usb: chipidea: imx: Add usb_phy_shutdown at probe's error path
If not, the PHY will be active even the controller is not in use.
We find this issue due to the PHY's clock refcount is not correct
due to -EPROBE_DEFER return after phy's init.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
ENGR00277955-2 rtc: rtc-snvs: support wakeup system from freeze mode
To support wakeup system from freeze mode of suspend,
device's irq can NOT be disabled during devices suspend,
so we need to add IRQF_NO_SUSPEND flag to irqflags.
ENGR00277955-1 keyboard: gpio_keys: support wakeup system from freeze mode
To support wakeup system from freeze mode of suspend,
device's irq can NOT be disabled during devices suspend,
so we need to add IRQF_NO_SUSPEND flag to irqflags.
Currently, we use different dts files to support ldo-bypass or ldo-enable, then
we need add both dts files for the boards which can support ldo-bypass mode(all
boards support ldo-enable at least). So for below boards we need add ldo-enable
dts file so that we can use this to easily support ldo-enable mode:
1)mx6q-sabresd board: ldo-bypass dts->mx6q-sabresd.dtb,
ldo-enable dts->mx6q-sabresd-ldo.dtb
2)mx6q-sabresd board: ldo-bypass dts->mx6dl-sabresd.dtb,
ldo-enable dts->mx6dl-sabresd-ldo.dtb
3)mx6sl-evk board: ldo-bypass dts->mx6sl-evk.dtb,
ldo-enable dts->mx6sl-evk-ldo.dtb
ENGR00278098 Make gpu modulable driver passing build
Gpu driver requires to do cache invalid, clean and flush operation.
But in 3.10 kernel, these APIs are not supposed to be called from
device driver. To avoid too much code change, Revert "ARM: Fix bad
merge bd1274dc005 (Merge branch 'v6v7' into devel)" to make the
situation the same as 3.0.35 kernel.
Robby Cai [Thu, 22 Aug 2013 10:01:59 +0000 (18:01 +0800)]
ENGR00275033-1 mx6sl: pxp/v4l: port v4l2 output driver to 3.10
port v4l2 output driver to 3.10 kernel
- replace .ioctl with .unlocked_ioctl
- add .vfl_dir flag - VFL_DIR_TX (newly introduced) for video_device
- drop __devinit, __devexit, __exit and __exit_p
- replace mxc_elcdif_frame_addr_setup() with pxp_show_buf(), where pan_display
be called due to the adoption of mxsfb.c from community
- change the fb id to be compared due to use new mxsfb.c
- mark the s_crop() and s_fbuf() third parameter const
- move local fbi variable to struct pxps
- use module_platform_driver()
Sascha Hauer [Mon, 26 Aug 2013 11:48:36 +0000 (13:48 +0200)]
cpufreq: imx6q: Fix clock enable balance
For changing the cpu frequency the i.MX6q has to be switched to some
intermediate clock during the PLL reprogramming. The driver tries
to be clever to keep the enable count correct but gets it wrong. If
the cpufreq is increased it calls clk_disable_unprepare twice
on pll2_pfd2_396m. This puts all other devices which get their clock
from pll2_pfd2_396m into a nonworking state.
Fix this by removing the clk enabling/disabling altogether since the
clk core will do this automatically during a reparent.
[shawn.guo: The driver assumes that cpu always boots with 800MHz, and
the first transition on 400MHz must be entering 400MHz setpoint. But
it turns out that's not always the case. In some system, cpu boots up
at 400MHz and then the first transition on 400MHz will be leaving
400MHz setpoint rather than entering. In this case, the use count of
pll2_pfd2_396m will be wrong. Anyway, since clock framework has been
nicely handling the clk enabling during reparent, we should not need
to worry about it.]
ENGR00277697 cpufreq: imx: increase cpufreq during suspend/resume
During suspend/resume, when cpufreq driver try to increase
voltage/freq, it needs to control I2C/SPI to communicate with
external PMIC to adjust voltage, but these I2C/SPI devices may
be already suspended, to avoid such scenario, we just increase
cpufreq to highest setpoint before suspend.
As this pm notification's updating cpu policy may work together
with cpufreq governor, both of them may call set_target at same
time, so we need to add mutex lock to prevent this scenario,
otherwise, the clock use count will be wrong.
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