Dave Airlie [Tue, 31 Mar 2015 03:36:25 +0000 (13:36 +1000)]
Merge tag 'drm-amdkfd-next-2015-03-25' of git://people.freedesktop.org/~gabbayo/linux into drm-next
- Allow amdkfd to work with multiple kgd instances. This is in preparation for
AMD's new open source kernel graphic driver (amdgpu), and for the new
AMD APU, Carrizo.
- Convert timestamping to use 64bit time accessors
- Three other minor changes.
* tag 'drm-amdkfd-next-2015-03-25' of git://people.freedesktop.org/~gabbayo/linux:
drm/amdkfd: Add multiple kgd support
drm/amdkfd: Convert timestamping to use 64bit time accessors
drm/amdkfd: add debug prints for process teardown
drm/amdkfd: Remove unused field from struct qcm_process_device
drm/amdkfd: rename fence_wait_timeout
Dave Airlie [Thu, 26 Mar 2015 23:17:20 +0000 (09:17 +1000)]
Merge branch 'drm-st-next-2015-03-19' of git://git.linaro.org/people/benjamin.gaignard/kernel into drm-next
This patch makes STI driver use the atomic helpers.
I have fix the comments done by Daniel on the first version and get
his ack with this second version.
* 'drm-st-next-2015-03-19' of git://git.linaro.org/people/benjamin.gaignard/kernel:
drm: sti: convert driver to atomic modeset
Xihan Zhang [Tue, 17 Mar 2015 11:32:53 +0000 (19:32 +0800)]
drm/amdkfd: Add multiple kgd support
The current code can only support one kgd instance. We have to
support multiple kgd instances in one system. i.e two amdgpu or two
radeon or one amdgpu + one radeon or more than two kgd instances.
John Stultz [Thu, 12 Mar 2015 17:23:40 +0000 (10:23 -0700)]
drm/amdkfd: Convert timestamping to use 64bit time accessors
Convert the timestamping in the amdkfd driver to use a timespec64 and 64bit
time accessors.
Although the existing code is completely safe beyond y2038 because it deals
with monotonic time, this patch is still needed in order to kill off all uses
of struct timespec.
Signed-off-by: John Stultz <john.stultz@linaro.org> Signed-off-by: Oded Gabbay <oded.gabbay@amd.com>
Dave Airlie [Tue, 24 Mar 2015 01:12:20 +0000 (11:12 +1000)]
Merge tag 'drm-intel-next-2015-03-13-merge' of git://anongit.freedesktop.org/drm-intel into drm-next
drm-intel-next-2015-03-13-rebased:
- EU count report param for gen9+ (Jeff McGee)
- piles of pll/wm/... fixes for chv, finally out of preliminary hw support
(Ville, Vijay)
- gen9 rps support from Akash
- more work to move towards atomic from Matt, Ander and others
- runtime pm support for skl (Damien)
- edp1.4 intermediate link clock support (Sonika)
- use frontbuffer tracking for fbc (Paulo)
- remove ilk rc6 (John Harrison)
- a bunch of smaller things and fixes all over
Includes backmerge because git rerere couldn't keep up any more.
* tag 'drm-intel-next-2015-03-13-merge' of git://anongit.freedesktop.org/drm-intel: (366 commits)
drm/i915: Make sure the primary plane is enabled before reading out the fb state
drm/i915: Update DRIVER_DATE to 20150313
drm/i915: Fix vmap_batch page iterator overrun
drm/i915: Export total subslice and EU counts
drm/i915: redefine WARN_ON_ONCE to include the condition
drm/i915/skl: Implement WaDisableHBR2
drm/i915: Remove the preliminary_hw_support shackles from CHV
drm/i915: Read CHV_PLL_DW8 from the correct offset
drm/i915: Rewrite IVB FDI bifurcation conflict checks
drm/i915: Rewrite some some of the FDI lane checks
drm/i915/skl: Enable the RPS interrupts programming
drm/i915/skl: Enabling processing of Turbo interrupts
drm/i915/skl: Updated the i915_frequency_info debugfs function
drm/i915: Simplify the way BC bifurcation state consistency is kept
drm/i915/skl: Updated the act_freq_mhz_show sysfs function
drm/i915/skl: Updated the gen9_enable_rps function
drm/i915/skl: Updated the gen6_rps_limits function
drm/i915/skl: Restructured the gen6_set_rps_thresholds function
drm/i915/skl: Updated the gen6_set_rps function
drm/i915/skl: Updated the gen6_init_rps_frequencies function
...
Dave Airlie [Sun, 22 Mar 2015 23:34:32 +0000 (09:34 +1000)]
Merge branch 'drm/next/rcar-du' of git://linuxtv.org/pinchartl/fbdev into drm-next
rcar-du fixes
* 'drm/next/rcar-du' of git://linuxtv.org/pinchartl/fbdev:
drm: rcar-du: Enable the atomic updates API
drm: rcar-du: Don't initialize event->pipe field
drm: rcar-du: Fix framebuffer reference leak through plane state
MAINTAINERS: Remove rcar-du.h entry
Dave Airlie [Sun, 22 Mar 2015 23:15:02 +0000 (09:15 +1000)]
Merge branch 'drm-next-4.1' of git://people.freedesktop.org/~agd5f/linux into drm-next
- DP MST support (disabled by default)
- non-ATOM aux support (DCE5+)
- output csc support for clamped RGB
- Lots of new queries for profiling, Gallium HUD, etc.
- Misc fixes
* 'drm-next-4.1' of git://people.freedesktop.org/~agd5f/linux: (40 commits)
drm/radeon: add DisplayPort MST support (v2)
drm/radeon: improve encoder picking functions (v2)
drm/radeon: export max link rate calculation
drm/radeon: add new atombios encoder/transmitter interfaces
drm/radeon: add some MST registers
radeon/fb: add wrapper functions around fb connector add/remove
radeon/cik: add support for short HPD irqs
radeon/si: add support for short HPD irqs
radeon/evergreen: add support for short HPD irqs
radeon: introduce a dp_work handler
drm/dp_mst: add a function to retrieve vcpi slots
drm/radeon: program auxch directly (v2)
drm/radeon: fix doublescan modes (v2)
drm/radeon: typo in parameter description
drm/radeon: add support for read reg query from radeon info ioctl
drm/radeon: add get_allowed_info_register for CIK
drm/radeon: add get_allowed_info_register for SI
drm/radeon: add get_allowed_info_register for cayman/TN
drm/radeon: add get_allowed_info_register for EG/BTC
drm/radeon: add get_allowed_info_register for r6xx/r7xx
...
For MST we need to be able to pick front end encoders
separate from backend, but only for MST, so we need to
make the encoder picking interface smarter.
v2: agd5f: squash in:
drm/radeon: release digital encoder before asking for new one Reported-by: Dieter Nützel <Dieter@nuetzel-hh.de> Signed-off-by: Dave Airlie <airlied@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dave Airlie [Thu, 19 Feb 2015 23:21:36 +0000 (09:21 +1000)]
drm/radeon: program auxch directly (v2)
The atombios tables have an unfortunate restriction on only
being able to write 12 bytes, MST really wants 16-bytes here,
and since the hw can do it, we should just write directly to it.
This uses a module option to allow for it now, and maybe
we should provide the old code as a fallback for a while.
v2: (agd5f)
- move registers to a proper register header
- only enable on DCE5+
- enable by default on DCE5+
- Switch pad to aux mode before using it
- reformat instance handling to better match the
rest of the driver
Signed-off-by: Dave Airlie <airlied@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Wed, 1 Oct 2014 15:26:50 +0000 (11:26 -0400)]
drm/radeon: add support for read reg query from radeon info ioctl
This allows us to query certain registers from userspace
for profiling and harvest configuration. E.g., it can
be used by the GALLIUM_HUD for profiling the status of
various gfx blocks.
Tested-by: Marek Olšák <marek.olsak@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Mon, 23 Feb 2015 15:11:49 +0000 (10:11 -0500)]
drm/radeon: add an output_csc property
This adds the drm property for output csc (e.g.,
transform of output display colorspace). Currently
only common ones (TV RGB, BT.601, BT.709) are supported,
but bypass and tv rgb are really the only useful ones at
the moment. Additionally we could expose a user adjustable
matrix in the future.
This commit just adds the property. The hw support will
be added in subsequent patches.
Remove the internal dependency on DPMS mode for power management by
using a by a powered state boolean instead, and use the new power off
handler at probe time. This ensure that the regmap cache is properly
marked as dirty when the device is probed, and the registers properly
synced during the first power up.
As a side effect this removes the initialization of current_edid_segment
at probe time, as the field will be initialized when the device is
powered on, at the latest right before reading EDID data.
Laurent Pinchart [Wed, 18 Feb 2015 13:19:33 +0000 (15:19 +0200)]
drm: adv7511: Fix nested sleep when reading EDID
The EDID read code waits for the read completion interrupt to occur
using wait_event_interruptible(). The condition passed to the macro
reads I2C registers. This results in sleeping with the task state set
to TASK_INTERRUPTIBLE, triggering a WARN_ON() introduced in commit 8eb23b9f35aae ("sched: Debug nested sleeps").
Fix this by reworking the EDID read code. Instead of checking whether
the read is complete through I2C reads, handle the interrupt registers
in the interrupt handler and update a new edid_read flag accordingly. As
a side effect both the IRQ and polling code paths now process the
interrupt sources through the same code path, simplifying the code.
Laurent Pinchart [Wed, 18 Feb 2015 13:19:33 +0000 (15:19 +0200)]
drm: adv7511: Fix DDC error interrupt handling
The DDC error interrupt bit is located in REG_INT1, not REG_INT0. Update
both the interrupt wait code and the interrupt sources reset code
accordingly.
drm: rcar-du: Fix framebuffer reference leak through plane state
Plane state duplication takes a reference to the framebuffer stored in
the state, but state destroy doesn't release it. This causes a reference
leak. Fix it.
Dave Airlie [Thu, 19 Mar 2015 04:05:53 +0000 (14:05 +1000)]
Merge branch 'drm_next' of https://github.com/markyzq/kernel-drm-rockchip into drm-next
rockchip fixes.
* 'drm_next' of https://github.com/markyzq/kernel-drm-rockchip:
drm/rockchip: vop: power off until vop standby take effect
drm/rockchip: vop: set vop enabled after enable iommu
drm/rockchip: vop use is_enabled instead of dpms mode
drm/rockchip: vop: fix vop vsync/hsync polarity
drm/rockchip: Only alloc a kmap for fbdev gem object
Dave Airlie [Thu, 19 Mar 2015 04:03:39 +0000 (14:03 +1000)]
Merge tag 'topic/drm-misc-2015-03-18' of git://anongit.freedesktop.org/drm-intel into drm-next
Another drm-misch pull request. Mostly the fbdev sizes deconfusion series
from Rob, everything else is small stuff all over. And the large i2c over
aux transfers patch, too.
* tag 'topic/drm-misc-2015-03-18' of git://anongit.freedesktop.org/drm-intel:
drm: check that planes types are correct while initializing CRTC
drm: change connector to tmp_connector
drm: Fix some typo mistake of the annotations
drm: Silence sparse warnings
drm: %pF is only for function pointers
drm/fb: handle tiled connectors better
drm/fb: small cleanup
drm/rockchip: use correct fb width/height
drm/exynos: use correct fb width/height
drm/cma: use correct fb width/height
drm/atomic: minor kerneldoc typo fix
drm/fb: document drm_fb_helper_surface_size
drm/dp: Use large transactions for I2C over AUX
drm/plane-helper: Fixup mismerge
drm/atomic: Constify a bunch of functions pointer structs
Damien Lespiau [Thu, 5 Feb 2015 19:35:13 +0000 (19:35 +0000)]
drm/i915: Make sure the primary plane is enabled before reading out the fb state
We don't want to end up in a state where we track that the pipe has its
primary plane enabled when primary plane registers are programmed with
values that look possible but the plane actually disabled.
Refuse to read out the fb state when the primary plane isn't enabled.
Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Suggested-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Reported-by: Andrey Skvortsov <andrej.skvortzov@gmail.com> Reported-by: Steven Rostedt <rostedt@goodmis.org>
Reference: http://mid.gmane.org/20150203191507.GA2374@crion86 Tested-by: Steven Rostedt <rostedt@goodmis.org> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Mika Kuoppala [Fri, 13 Mar 2015 13:21:53 +0000 (15:21 +0200)]
drm/i915: Fix vmap_batch page iterator overrun
vmap_batch() calculates amount of needed pages for the mapping
we are going to create. And it uses this page count as an
argument for the for_each_sg_pages() macro. The macro takes the number
of sg list entities as an argument, not the page count. So we ended
up iterating through all the pages on the mapped object, corrupting
memory past the smaller pages[] array.
Fix this by bailing out when we have enough pages.
Cc: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Jeff McGee [Mon, 9 Mar 2015 23:06:54 +0000 (16:06 -0700)]
drm/i915: Export total subslice and EU counts
Setup new I915_GETPARAM ioctl entries for subslice total and
EU total. Userspace drivers need these values when constructing
GPGPU commands. This kernel query method is intended to replace
the PCI ID-based tables that userspace drivers currently maintain.
The kernel driver can employ fuse register reads as needed to
ensure the most accurate determination of GT config attributes.
This first became important with Cherryview in which the config
could differ between devices with the same PCI ID.
The kernel detection of these values is device-specific and not
included in this patch. Because zero is not a valid value for any of
these parameters, a value of zero is interpreted as unknown for the
device. Userspace drivers should continue to maintain ID-based tables
for older devices not supported by the new query method.
v2: Increment our I915_GETPARAM indices to fit after REVISION
which was merged ahead of us.
For: VIZ-4636 Signed-off-by: Jeff McGee <jeff.mcgee@intel.com> Tested-by: Zhigang Gong <zhigang.gong@linux.intel.com> Acked-by: Zhigang Gong <zhigang.gong@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Ville Syrjälä [Wed, 11 Mar 2015 20:52:08 +0000 (22:52 +0200)]
drm/i915: Read CHV_PLL_DW8 from the correct offset
We accidentally pass 'pipe' instead of 'port' to CHV_PLL_DW8() and
with PIPE_C we end up at register offset 0x8320 which isn't the
0x8020 we wanted. Fix it.
The problem was fortunately caught by the sanity check in vlv_dpio_read():
WARNING: CPU: 1 PID: 238 at ../drivers/gpu/drm/i915/intel_sideband.c:200 vlv_dpio_read+0x77/0x80 [i915]()
DPIO read pipe C reg 0x8320 == 0xffffffff
The problem got introduced with this commit:
commit 71af07f91f12bbab96335e202c82525d31680960
Author: Vijay Purushothaman <vijay.a.purushothaman@linux.intel.com>
Date: Thu Mar 5 19:33:08 2015 +0530
drm/i915: Update prop, int co-eff and gain threshold for CHV
Cc: Vijay Purushothaman <vijay.a.purushothaman@linux.intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Todd Previte <tprevite@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Ignore the current state of the pipe and just check crtc_state->enable
and the number of FDI lanes required. This means we don't accidentally
mistake the FDI lanes as being available of one of the pipes just
happens to be disabled at the time of the check. Also we no longer
consider pipe C to require FDI lanes when it's driving the eDP
transcoder.
We also take the opportunity to make the code a bit nicer looking by
hiding the ugly bits in the new pipe_required_fdi_lanes() function.
Cc: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Cc: Daniel Vetter <daniel@ffwll.ch> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Ander Conselvan de Oliveira <conselvan2@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Ville Syrjälä [Wed, 11 Mar 2015 16:52:30 +0000 (18:52 +0200)]
drm/i915: Rewrite some some of the FDI lane checks
The logic in the FDI lane checks is very hard for my poor brain to
grasp. Rewrite it in a more straightforward way.
Cc: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Cc: Daniel Vetter <daniel@ffwll.ch> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Ander Conselvan de Oliveira <conselvan2@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Akash Goel [Fri, 6 Mar 2015 05:37:23 +0000 (11:07 +0530)]
drm/i915/skl: Enabling processing of Turbo interrupts
Earlier Turbo interrupts were not being processed for SKL,
as something was amiss in turbo programming for SKL.
Now missing changes have been added, so enabling the Turbo
interrupt processing for SKL.
drm/i915: Simplify the way BC bifurcation state consistency is kept
Remove the global modeset resource function that would disable the
bifurcation bit, and instead enable/disable it when enabling the pch
transcoder. The mode set consistency check should prevent us from
disabling the bit if pipe C is enabled so the change should be safe.
Note that this doens't affect the logic that prevents the bit being
set while a pipe is active, since the patch retains the behavior of
only chaging the bit if necessary. Because of the checks during mode
set, the first change would necessarily happen with both pipes B and
C disabled, and any subsequent write would be skipped.
v2: Only change the bit during pch trancoder enable. (Ville)
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Akash Goel [Fri, 6 Mar 2015 05:37:20 +0000 (11:07 +0530)]
drm/i915/skl: Updated the gen9_enable_rps function
On SKL, GT frequency is programmed in units of 16.66 MHZ units compared
to 50 MHZ for older platforms. Also the time value specified for Up/Down EI &
Up/Down thresholds are expressed in units of 1.33 us, compared to 1.28
us for older platforms. So updated the gen9_enable_rps function as per that.
v2: Updated to use new macro GT_INTERVAL_FROM_US
v3: Removed the initial setup of certain registers, from gen9_enable_rps,
which gets overridden later from gen6_set_rps (Damien)
v4: Removed the enabling of rps interrupts, from gen9_enable_rps.
To be done from intel_gen6_powersave_work only, as done for other
platforms also.
Akash Goel [Fri, 6 Mar 2015 05:37:18 +0000 (11:07 +0530)]
drm/i915/skl: Restructured the gen6_set_rps_thresholds function
Prior to SKL, the time period programmed in Up/Down EI & Up/Down
threshold registers was in units of 1.28 micro seconds. But for
SKL, the units have changed (1.333 micro seconds).
Have generalized the implementation of gen6_set_rps_thresholds function,
by removing the hard coding done in it as per 1.28 micro seconds.
v2: Renamed the local variables & removed superfluous comments (Chris)
Signed-off-by: Akash Goel <akash.goel@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Akash Goel [Fri, 6 Mar 2015 05:37:17 +0000 (11:07 +0530)]
drm/i915/skl: Updated the gen6_set_rps function
On SKL, the frequency is programmed differently in RPNSWREQ (A008)
register (from bits 23 to 31, compared to bits 24 to 31). So updated
the gen6_set_rps function, as per this change.
Signed-off-by: Akash Goel <akash.goel@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Akash Goel [Fri, 6 Mar 2015 05:37:16 +0000 (11:07 +0530)]
drm/i915/skl: Updated the gen6_init_rps_frequencies function
On SKL the frequency is specified in units of 16.66 MHZ, barring the
RP_STATE_CAP(0x5998) register, which still reports frequency in units
of 50 MHZ. So an extra conversion is required in gen6_init_rps_frequencies
function for SKL, to store the frequency values as per the actual hardware unit.
v2: Corrected the conversion from 50 to 16.66 MHZ (Ville)
Signed-off-by: Akash Goel <akash.goel@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Akash Goel [Fri, 6 Mar 2015 05:37:15 +0000 (11:07 +0530)]
drm/i915/skl: Updated intel_gpu_freq() and intel_freq_opcode()
On SKL, frequency is specified in units of 16.66 MHZ.
Updated the intel_gpu_freq() and intel_freq_opecode() functions
to do the conversion appropriately.
Signed-off-by: Akash Goel <akash.goel@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Akash Goel [Fri, 6 Mar 2015 05:37:14 +0000 (11:07 +0530)]
drm/i915/skl: Added new macros
For SKL, register definition for RPNSWREQ (A008), RPSTAT1(A01C)
have changed slightly. Also on SKL, frequency is specified in
units of 16.66 MHZ, compared to 50 MHZ for most of the earlier
platforms and the time values are expressed in units of 1.33 us,
compared to 1.28 us for earlier platforms.
Added new macros for the aforementioned changes.
v2: Renamed the GT_FREQ_FROM_PERIOD macro to GT_INTERVAL_FROM_US (Damien)
v3: Removed the implicit use of dev_priv in GT_INTERVAL_FROM_US macro (Chris)
Signed-off-by: Akash Goel <akash.goel@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Jani Nikula [Tue, 3 Feb 2015 12:34:05 +0000 (14:34 +0200)]
drm/i915: remove indirection in the PCI ID macros
Spell all the PCI IDs out to be able to quickly grep for the IDs. No
functional changes.
Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
[danvet: Add GT1/2 to comments to not loose that distinction.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Ville Syrjälä [Tue, 10 Mar 2015 14:16:28 +0000 (16:16 +0200)]
drm/i915: Add polish to VLV WM shift+mask operations
Wrap the FW register value shift+mask operations into a macro to hide
the ugliness a bit. Also might avoid bugs due to typos.
Also rename all the primary/sprite plane low order bit masks to have the
_VLV suffix, so that we can use the FW_WM_VLV() macro instead of the
FW_WM() macro for them in a consistent manner. Cursor and all the high
order bits are left to use the FW_WM() macro as there's no real
confusion with them.
Cc: Daniel Vetter <daniel@ffwll.ch> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Ville Syrjälä [Tue, 10 Mar 2015 11:15:23 +0000 (13:15 +0200)]
drm/i915: Use plane->state->fb instead of plane->fb in intel_plane_restore()
plane->fb is not as reliable as plane->state->fb so let's convert
intel_plane_restore() over the the new way of thinking as well.
Cc: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Ville Syrjälä [Tue, 10 Mar 2015 11:15:21 +0000 (13:15 +0200)]
drm/i915: Remove debug prints from primary plane update funcs
These are now called from the plane commit hooks, so they really need to
be fast or else we risk atomic update failures. So kill the debug prints
which are slowing things down massively.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Matt Roper [Mon, 9 Mar 2015 18:06:02 +0000 (11:06 -0700)]
drm/i915: Don't assume primary & cursor are always on for wm calculation (v4)
Current ILK-style watermark code assumes the primary plane and cursor
plane are always enabled. This assumption, along with the combination
of two independent commits that got merged at the same time, results in
a NULL dereference. The offending commits are:
The first commit causes us to use the FB from plane->state->fb rather
than the legacy plane->fb, which is updated a bit later in the process.
The second commit includes a change that now triggers watermark
reprogramming on primary plane enable/disable where we didn't have one
before (which wasn't really correct, but we had been getting lucky
because we always calculated as if the primary plane was on).
Together, these two commits cause the watermark calculation to
(properly) see plane->state->fb = NULL when we're in the process of
disabling the primary plane. However the existing watermark code
assumes there's always a primary fb and tries to dereference it to find
out pixel format / bpp information.
The fix is to make ILK-style watermark calculation actually check the
true status of primary & cursor planes and adjust our watermark logic
accordingly.
v2: Update unchecked uses of state->fb for other platforms (pnv, skl,
etc.). Note that this is just a temporary fix. Ultimately the
useful information is going to be computed at check time and stored
right in the state structures so that we don't have to figure this
all out while we're supposed to be programming the watermarks.
(caught by Tvrtko)
v3: Fix a couple copy/paste mistakes in SKL code. (Tvrtko)
v4: Only add FB checks for ILK/SKL codepaths. Older platforms still use
intel_crtc_active() and will shortcircuit out of watermark
calculations before ever trying to dereference the primary plane's
framebuffer.
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reported-by: Michael Leuchtenburg <michael@slashhome.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89388 Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Chris Wilson [Mon, 16 Feb 2015 14:31:49 +0000 (14:31 +0000)]
drm/i915: Move drm_framebuffer_unreference out of struct_mutex for flips
intel_user_framebuffer_destroy() requires the struct_mutex for its
object bookkeeping, so this means that all calls to
drm_framebuffer_unreference must not hold that lock.
Ville Syrjälä [Thu, 5 Mar 2015 19:19:52 +0000 (21:19 +0200)]
drm/i915: Disable DDR DVFS on CHV
DDR DVFS introduces massive memory latencies which can't be handled by
the PND deadline stuff. Instead the watermarks will need to be
programmed to compensate for the latency and the deadlines will need to
be programmed to tight fixed values. That means DDR DVFS can only be
enabled if the display FIFOs are large enough, and that pretty much
means we have to manually repartition them to suit the needs of the
moment.
That's a lot of change, so in the meantime let's just disable DDR DVFS
to get the display(s) to be stable.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Ville Syrjälä [Thu, 5 Mar 2015 19:19:51 +0000 (21:19 +0200)]
drm/i915: Enable the maxfifo PM5 mode when appropriate on CHV
CHV has a new knob in Punit to select between some memory power savings
modes PM2 and PM5. We can allow the deeper PM5 when maxfifo mode is
enabled, so let's do so in the hopes for moar power savings.
v2: Put the thing into a separate function to avoid churn later
v3: Don't break VLV
Reviewed-by: Vijay Purushothaman <vijay.a.purushothaman@linux.intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Vidya Srinivas [Thu, 5 Mar 2015 19:19:50 +0000 (21:19 +0200)]
drm/i915: Program PFI credits for VLV
PFI credit programming is required when CD clock (related to data flow from
display pipeline to end display) is greater than CZ clock (related to data
flow from memory to display plane). This programming should be done when all
planes are OFF to avoid intermittent hangs while accessing memory even from
different Gfx units (not just display).
If cdclk/czclk >=1, PFI credits could be set as any number. To get better
performance, larger PFI credit can be assigned to PND. Otherwise if
cdclk/czclk<1, the default PFI credit of 8 should be set.
v2:
- Change log to lower log level instead of DRM_ERROR
- Change function name to valleyview_program_pfi_credits
- Move program PFI credits to modeset_init instead of intel_set_mode
- Change magic numbers to logical constants
[vsyrjala v3:
- only program in response to cdclk update
- program the credits also when cdclk<czclk
- add CHV bits
v4:
- Change CHV cdclk<czclk credits to 12 (Vijay)]
Ville Syrjälä [Thu, 5 Mar 2015 19:19:49 +0000 (21:19 +0200)]
drm/i915: Rewrite VLV/CHV watermark code
Assuming the PND deadline mechanism works reasonably we should do
memory requests as early as possible so that PND has schedule the
requests more intelligently. Currently we're still calculating
the watermarks as if VLV/CHV are identical to g4x, which isn't
the case.
The current code also seems to calculate insufficient watermarks
and hence we're seeing some underruns, especially on high resolution
displays.
To fix it just rip out the current code and replace is with something
that tries to utilize PND as efficiently as possible.
We now calculate the WM watermark to trigger when the FIFO still has
256us worth of data. 256us is the maximum deadline value supoorted by
PND, so issuing memory requests earlier would mean we probably couldn't
utilize the full FIFO as PND would attempt to return the data at
least in at least 256us. We also clamp the watermark to at least 8
cachelines as that's the magic watermark that enabling trickle feed
would also impose. I'm assuming it matches some burst size.
In theory we could just enable trickle feed and ignore the WM values,
except trickle feed doesn't work with max fifo mode anyway, so we'd
still need to calculate the SR watermarks. It seems cleaner to just
disable trickle feed and calculate all watermarks the same way. Also
trickle feed wouldn't account for the 256us max deadline value, thoguh
that may be a moot point in non-max fifo mode sicne the FIFOs are fairly
small.
On VLV max fifo mode can be used with either primary or sprite planes.
So the code now also checks all the planes (apart from the cursor)
when calculating the SR plane watermark.
We don't have to worry about the WM1 watermarks since we're using the
PND deadline scheme which means the hardware ignores WM1 values.
v2: Use plane->state->fb instead of plane->fb
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Rodrigo Vivi [Tue, 10 Mar 2015 00:57:07 +0000 (17:57 -0700)]
drm/i915: Make sure we invalidate frontbuffer on fbcon.
There are some cases like suspend/resume or dpms off/on sequences
that can flush frontbuffer bits. In these cases features that relies
on frontbuffer tracking can start working and user can stop getting
screen updates on fbcon having impression the system is frozen.
So, let's make sure we also invalidate frontbuffer on fbdev blank.
v2: Daniel was right, backtrace didn't show other path than this blank
one so let's make sure frontbuffer bits gets invalidate here instead of
on random write operations that doesn't garantee we track all frontbuffer
writes.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
[danvet: Exchange code comments for one that complains about the
locking, like in set_par.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
projects / linux-beck.git / log