Stephen Warren [Tue, 12 Feb 2013 17:26:45 +0000 (10:26 -0700)]
ARM: tegra: remove clock-frequency properties from serial nodes
Currently, the serial nodes define both a clock-frequency and a clocks
property. We should not provide both, since they might conflict.
In practice, this also causes problems since the of_serial driver uses
the clock-frequency property in preference to the clocks property, and
hence doesn't clk_prepare_enable() the clock, which may then leave it
with no known users, and hence the common clock framework will disable
it, thus breaking the port, which is usually the console.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
cclk_g_parents, cclk_lp_parents and sclk_parents are only accessed from within
clk-tegra30.c. Declare them static to avoid namespace polution.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
clk: tegra: Add missing spinlock for hclk and pclk
The hclk and pclk clocks are controlled by the same register. Hence a lock is
required to avoid corruption.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
Although tegra_clk_register_super_mux() has a lock parameter, the lock is not
actually used by the code. Fixed with this patch.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
Joseph Lo [Thu, 7 Feb 2013 05:07:11 +0000 (13:07 +0800)]
clk: tegra: fix wrong clock index between se to sata_cold
The index of se should be 127. And the previous clock index was 125. So
we need to set up the index for se to get the correct index between se
to sata_cold.
Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
Stephen Warren [Wed, 23 Jan 2013 16:43:49 +0000 (09:43 -0700)]
ARM: tegra: move serial clock-frequency attr into the Tegra30 dtsi
No Tegra30 Platform is running PLL_P at another rate than 408MHz, nor is
any using any other PLL as UART source clock. Move attribute into SoC
level dtsi file to slim down board DT files.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Lucas Stach [Tue, 22 Jan 2013 21:46:09 +0000 (22:46 +0100)]
ARM: tegra: Add Toradex Iris carrier board DT with T20 512MB COM
This adds the device tree for the Toradex Iris carrier board used
together with a Colibri T20 512MB COM.
The Iris has the following features, in brackets the current status:
- DVI and VGA output through DVI-I connector (DVI-D enabled and tested)
- LVDS output
- 1 USB host port (enabled and tested)
- 1 USB OTG port (enabled)
- 100 MBit Ethernet (enabled and tested)
- 5 UART ports (2 on 10way headers enabled and tested)
- 1 MicroSD Slot (enabled and tested)
- Audio connectors (enabled, only HP out and Line-in tested)
- i2c RTC
- GPIO connector (enabled, only sparsely tested)
- external i2c bus
- 4 PWM out
- analog in
Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Stephen Warren <swarren@nvidia.com>
Lucas Stach [Tue, 22 Jan 2013 21:46:08 +0000 (22:46 +0100)]
ARM: tegra: Add Colibri T20 512MB COM device tree
This adds the device tree include file for the Toradex Colibri T20
Computer on Module (COM). It's only valid for the 512MB RAM version of
the module, as the 256MB version needs different EMC tables and flash
configuration. To make this clear the suffix -512 was added to the board
compatible string.
The Colibri T20 uses a Tegra20 SoC and has onboard USB Ethernet and AC97
sound.
Still some things like onboard NAND support missing, but should be a
good base for further development.
Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Stephen Warren <swarren@nvidia.com>
Lucas Stach [Tue, 22 Jan 2013 21:46:07 +0000 (22:46 +0100)]
ARM: tegra: move serial clock-frequency attr into the Tegra20 dtsi
No Tegra20 Platform is running PLL_P at another rate than 216MHz, nor is
any using any other PLL as UART source clock. Move attribute into SoC
level dtsi file to slim down board DT files.
Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Stephen Warren <swarren@nvidia.com>
Laxman Dewangan [Fri, 18 Jan 2013 05:58:43 +0000 (11:28 +0530)]
ARM: tegra: whistler: enable keyboard in DT
Enable Tegra based keyboard controller and populate the key mapping
for Whistler.
With this patch, HOME, BACK, POWER and MENU keys will work.
Still other keys which are in ROW3 and ROW4 will not work as it
conflicts with KBC pins on SDIO2 pinmux.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
Laxman Dewangan [Wed, 16 Jan 2013 13:06:12 +0000 (18:36 +0530)]
ARM: tegra: cardhu: register UARTC
UARTC is used for the interfacing with bluetooth device.
Register this UART channel as high speed serial channel
so that it can use the APB DMA for data transfer.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
Laxman Dewangan [Tue, 15 Jan 2013 07:24:49 +0000 (12:54 +0530)]
ARM: tegra: seaboard: enable keyboard in DT
Enable Tegra based keyboard controller and populate the key matrix for
seaboard. The key matrix was originally on driver code which is removed
to have clean driver. The key mapping is now passed through dts file.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
Stephen Warren [Mon, 14 Jan 2013 17:09:16 +0000 (10:09 -0700)]
ARM: tegra: swap cache-/interrupt-ctrlr nodes in DT
This ensures nodes are sorted in order of reg address. This makes it
easier to compare against e.g. the U-Boot device trees, and is simply
consistent and clean.
While we're at it, remove the unit address from the cache-controller
node name, since it's unique without it.
Reported-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
Bryan Wu [Wed, 2 Jan 2013 23:53:51 +0000 (15:53 -0800)]
ARM: DT: tegra: Add Tegra30 Beaver board support
This patch adds support for Tegra30 Beaver board in upstream kernel.
Beaver board is a Tegra30 SoC based development board, it has
following features:
- T30 or T33 SoC (Qual core ARM Cortex A9)
- 2 GB DDR3L
- 16 GB EMMC
- 1 SD slot
- 1 USB Standart A port and 1 USB micro AB port
- PCI-E Gig Ethernet
- Audio input/output
- SATA port
- HDMI output
- UART and JTAG
Signed-off-by: Bryan Wu <pengw@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
The compatible properties of Tegra SoC based boards or machines need
to be documented. This patch adds these board levle compatible
properties into device tree binding document.
Signed-off-by: Bryan Wu <pengw@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
Laxman Dewangan [Wed, 19 Dec 2012 06:31:11 +0000 (12:01 +0530)]
ARM: tegra: dts: add aliases and DMA requestor for serial controller
Add APB DMA requestor and serial aliases for serial controller.
There will be two serial driver i.e. 8250 based simple serial driver
and APB DMA based serial driver for higher baudrate and performace.
The simple serial driver get enabled with compatible nvidia,tegra20-uart
and APB DMA based driver will get enabled with compatible
nvidia,tegra20-hsuart.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
Laxman Dewangan [Wed, 19 Dec 2012 14:57:12 +0000 (20:27 +0530)]
ARM: tegra30: tegra30 gpio is not compatible with tegra20 gpio
tegra30 gpio controller is not compatible with the tegra20 due to
their bank stride i.e. Tegra20 bank stride is 0x80 where Tegra30
bank stride is 0x100.
Joseph Lo [Wed, 16 Jan 2013 17:33:55 +0000 (17:33 +0000)]
ARM: tegra20: cpuidle: apply coupled cpuidle for powered-down mode
The "powered-down" cpuidle mode of Tegra20 needs the CPU0 be the last one
core to go into this mode before other core. The coupled cpuidle framework
can help to sync the MPCore to coupled state then go into "powered-down"
idle mode together. The driver can just assume the MPCore come into
"powered-down" mode at the same time. No need to take care if the CPU_0
goes into this mode along and only can put it into safe idle mode (WFI).
The powered-down state of Tegra20 requires power gating both CPU cores.
When the secondary CPU requests to enter powered-down state, it saves
its own contexts and then enters WFI for waiting CPU0 in the same state.
When the CPU0 requests powered-down state, it attempts to put the secondary
CPU into reset to prevent it from waking up. Then power down both CPUs
together and power off the cpu rail.
Be aware of that, you may see the legacy power state "LP2" in the code
which is exactly the same meaning of "CPU power down".
Based on the work by:
Colin Cross <ccross@android.com>
Gary King <gking@nvidia.com>
Signed-off-by: Joseph Lo <josephl@nvidia.com> Acked-by: Colin Cross <ccross@android.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
Joseph Lo [Tue, 15 Jan 2013 22:11:01 +0000 (22:11 +0000)]
ARM: tegra20: flowctrl: add support for cpu_suspend_enter/exit
The flow controller can help CPU to go into suspend mode (powered-down
state). When CPU go into powered-down state, it needs some careful
settings before getting into and after leaving. The enter and exit
functions do that by configuring appropriate mode for flow controller.
Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
Joseph Lo [Tue, 15 Jan 2013 22:10:38 +0000 (22:10 +0000)]
ARM: tegra20: cpuidle: add powered-down state for secondary CPU
The powered-down state of Tegra20 requires power gating both CPU cores.
When the secondary CPU requests to enter powered-down state, it saves
its own contexts and then enters WFI. The Tegra20 had a limition to
power down both CPU cores. The secondary CPU must waits for CPU0 in
powered-down state too. If the secondary CPU be woken up before CPU0
entering powered-down state, then it needs to restore its CPU states
and waits for next chance.
Be aware of that, you may see the legacy power state "LP2" in the code
which is exactly the same meaning of "CPU power down".
Based on the work by:
Colin Cross <ccross@android.com>
Gary King <gking@nvidia.com>
Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
Joseph Lo [Tue, 15 Jan 2013 22:10:26 +0000 (22:10 +0000)]
ARM: tegra: add pending SGI checking API
The "powered-down" CPU idle mode of Tegra cut off the vdd_cpu rail, it
include the power of GIC. That caused the SGI (Software Generated
Interrupt) been lost. Because the SGI can't wake up the CPU that in
the "powered-down" CPU idle mode. We need to check if there is any
pending SGI when go into "powered-down" CPU idle mode. This is important
especially when applying the coupled cpuidle framework into "power-down"
cpuidle dirver. Because the coupled cpuidle framework may have the
chance that misses IPI_SINGLE_FUNC handling sometimes.
For the PPI or SPI, something like the legacy peripheral interrupt. It
still can be maintained by Tegra legacy interrupt controller. If there
is any pending PPI or SPI when CPU in "powered-down" CPU idle mode. The
CPU can be woken up immediately. So we don't need to take care the same
situation for PPI or SPI.
Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
Venu Byravarasu [Thu, 17 Jan 2013 20:15:37 +0000 (20:15 +0000)]
usb: add APIs to access host registers from Tegra PHY
As Tegra PHY driver needs to access one of the host registers,
added few APIs.
Signed-off-by: Venu Byravarasu <vbyravarasu@nvidia.com> Acked-by: Alan Stern <stern@rowland.harvard.edu>
[swarren: moved assignment of phy->is_ulpi_phy to previous patch.] Signed-off-by: Stephen Warren <swarren@nvidia.com>
Venu Byravarasu [Wed, 16 Jan 2013 03:30:21 +0000 (03:30 +0000)]
USB: PHY: tegra: Get rid of instance number to differentiate PHY type
Tegra20 USB has 3 PHY instances:
Instance 1 and 3 are UTMI. Instance 2 is ULPI.
As instance number was used to differentiate ULPI from UTMI,
used DT param to get this info and processed accordingly.
Signed-off-by: Venu Byravarasu <vbyravarasu@nvidia.com> Acked-by: Felipe Balbi <balbi@ti.com>
[swarren: moved assignment of phy->is_ulpi_phy into this patch out
of next patch.] Signed-off-by: Stephen Warren <swarren@nvidia.com>
Stephen Warren [Wed, 23 Jan 2013 00:12:25 +0000 (17:12 -0700)]
ARM: tegra: add clocks properties to USB PHY nodes
The patch to add USB PHY nodes to device tree was written before Tegra
supported the clocks property in device tree. Now that it does, add the
required clocks properties to these nodes.
This will allow all clk_get_sys() calls in tegra_usb_phy.c to be replaced
by clk_get(phy->dev, clock_name), as part of converting the PHY driver to
a platform driver.
Acked-by: Venu Byravarasu <vbyravarasu@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
Venu Byravarasu [Wed, 16 Jan 2013 03:30:19 +0000 (03:30 +0000)]
ARM: tegra: add DT nodes for Tegra USB PHY
Add DT nodes for Tegra USB PHY along with related documentation.
Also added a phandle property to controller DT node, for referring
to connected PHY instance.
Signed-off-by: Venu Byravarasu <vbyravarasu@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
Venu Byravarasu [Thu, 13 Dec 2012 20:59:08 +0000 (20:59 +0000)]
usb: host: tegra: Resetting PORT0 based on information received via DT.
Tegra USB host driver is using port instance number,
to handle some of the hardware issues on SOC e.g. reset PORT0
twice etc. As instance number based handling looks ugly,
making use of information passed through DT for achieving this.
Venu Byravarasu [Mon, 17 Dec 2012 18:31:01 +0000 (18:31 +0000)]
ARM: tegra: remove USB address related macros from iomap.h
USB register base address and sizes defined in iomap.h
are not used in any files other than board-dt-tegra20.c.
Hence removed those defines from header file and using
the absolute values in board files.
Signed-off-by: Venu Byravarasu <vbyravarasu@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
Prashant Gaikwad [Fri, 11 Jan 2013 08:01:25 +0000 (13:31 +0530)]
ASoC: tegra: remove auxdata
Configlink clock information is added to device tree. Get the clocks
using device node. Remove AUXDATA.
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
Prashant Gaikwad [Fri, 11 Jan 2013 08:01:24 +0000 (13:31 +0530)]
staging: nvec: remove use of clk_get_sys
As clock information is added to device tree clock can be looked up
using clk_get. Remove use of clk_get_sys.
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Acked-by: Marc Dietrich <marvin24@gmx.de> Acked-by: Julian Andres Klode <jak@jak-linux.org>
[swarren: updated TODO file to remove entry that requested this change] Signed-off-by: Stephen Warren <swarren@nvidia.com>
Prashant Gaikwad [Fri, 11 Jan 2013 07:46:26 +0000 (13:16 +0530)]
ARM: tegra: migrate to new clock code
Migrate Tegra clock support to drivers/clk/tegra, this involves
moving:
1. definition of tegra_cpu_car_ops to clk.c
2. definition of reset functions to clk-peripheral.c
3. change parent of cpu clock.
4. Remove legacy clock initialization.
5. Initialize clocks using DT.
6. Remove all instance of mach/clk.h
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
[swarren: use to_clk_periph_gate().] Signed-off-by: Stephen Warren <swarren@nvidia.com>
Prashant Gaikwad [Fri, 11 Jan 2013 07:46:25 +0000 (13:16 +0530)]
clk: tegra: add clock support for Tegra30
Add Tegra30 clock support based on common clock framework.
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
[swarren: ensure all OF lookups return valid cookies i.e. an explicit
error pointer or valid pointer not NULL, adapt to renames in earlier
patches, fixed some checkpatch issues.] Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
Prashant Gaikwad [Fri, 11 Jan 2013 07:46:24 +0000 (13:16 +0530)]
clk: tegra: add clock support for Tegra20
Add Tegra20 clock support based on common clock framework.
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
[swarren: s/1GHz/100MHz/ in call to tegra_clk_plle() to fix PCIe,
implemented KBC clock, ensure all OF lookups return valid cookies i.e.
an explicit error pointer or valid pointer not NULL, adapt to renames
in earlier patches, fixed some checkpatch issues.] Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
Prashant Gaikwad [Fri, 11 Jan 2013 07:46:20 +0000 (13:16 +0530)]
clk: tegra: add Tegra specific clocks
Add Tegra specific clocks, pll, pll_out, peripheral, frac_divider, super.
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
[swarren: alloc sizeof(*foo) not sizeof(struct foo), add comments re:
storing pointers to stack variables, make a timeout loop more idiomatic,
use _clk_pll_disable() not clk_disable_pll() from _program_pll() to
avoid redundant lock operations, unified tegra_clk_periph() and
tegra_clk_periph_nodiv(), unified tegra_clk_pll{,e}, rename all clock
registration functions so they don't have the same name as the clock
structs, return -EINVAL from clk_plle_enable when matching table rate
not found, pass ops to _tegra_clk_register_pll rather than a bool.] Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
Stephen Warren [Fri, 11 Jan 2013 07:46:22 +0000 (13:16 +0530)]
ARM: tegra: define Tegra20 CAR binding
The Tegra20 CAR (Clock And Reset) Controller controls most aspects of
most clocks within Tegra20. The device tree binding models this as a
single monolithic clock provider, which exports many clocks. This reduces
the number of nodes needed in device tree to represent these clocks.
This binding is only useful for Tegra20; the set of clocks that exists on
Tegra30 is sufficiently different to merit its own binding.
Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
[pgaikwad: Added mux clk ids and sorted CAR node] Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
Joseph Lo [Fri, 25 Jan 2013 06:38:32 +0000 (14:38 +0800)]
ARM: tegra: fix compile error when disable CPU_IDLE
The "sleep.S" file has many functions that be shared by different module
currently. Not just for CPU idle driver. Make it build as default now.
Reported-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Joseph Lo <josephl@nvidia.com>
[swarren: add sleep.o to separate line so each line only contains 1 file] Signed-off-by: Stephen Warren <swarren@nvidia.com>
Joseph Lo [Fri, 4 Jan 2013 09:32:22 +0000 (17:32 +0800)]
ARM: tegra: make device can run on UP
The reset handler code is used for either UP or SMP. To make Tegra device
can compile for UP. It needs to be moved to another file that is not SMP
only. This is because the reset handler also be needed by CPU idle
"powered-down" mode. So we also need to put the reset handler init function
in non-SMP only and init them always.
And currently the implementation of the reset handler to know which CPU is
OK to bring up was identital with "cpu_present_mask". But the
"cpu_present_mask" did not initialize yet when the reset handler init
function was moved to init early function. We use the "cpu_possible_mask"
to replace "cpu_present_mask". Then it can work on both UP and SMP case.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
[swarren: dropped the move of v7_invalidate_l1() from one file to another,
to avoid conflicts with Pavel's cleanup of this function, adjust Makefile
so each line only contains 1 file.] Signed-off-by: Stephen Warren <swarren@nvidia.com>
Hiroshi Doyu [Tue, 15 Jan 2013 08:13:12 +0000 (10:13 +0200)]
ARM: tegra: Use DT /cpu node to detect number of CPU core
SCU based detection only works with Cortex-A9 MP and it doesn't
support ones with multiple clusters. The only way to detect number of
CPU core correctly is with DT /cpu node.
Tegra SoCs decided to use DT detection as the only way and to not use
SCU based detection at all. Even if DT /cpu node based detection
fails, it continues with a single core
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
Joseph Lo [Fri, 4 Jan 2013 09:32:21 +0000 (17:32 +0800)]
ARM: tegra: clean up the CPUINIT section
There are some redundant codes in the CPUINIT section that was caused by
some codes not be organized well in "headsmp.S". Currently all the codes
in "headsmp.S" were put into CPUINIT section. But actually it doesn't
need to be loacted in CPUINIT section. There is no fuction access them
in CPUINIT section and we will relocate them to IRAM.
These codes also caused some unnecessary functions that access these
codes been put into CPUINIT section too. This patch clean it up and put
them into normal text section.
Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
Joseph Lo [Thu, 3 Jan 2013 06:43:00 +0000 (14:43 +0800)]
ARM: tegra: moving the clock gating procedure to tegra_cpu_kill
The tegra_cpu_die was be executed by the CPU itslf. So the clock gating
procedure won't be executed after the CPU hardware shutdown code. Moving
the clock gating procedure to tegra_cpu_kill that will be run by another
CPU after the CPU died.
Signed-off-by: Joseph Lo <josephl@nvidia.com> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
Joseph Lo [Thu, 3 Jan 2013 06:42:59 +0000 (14:42 +0800)]
ARM: tegra: update the cache maintenance order for CPU shutdown
Updating the cache maintenance order before CPU shutdown when doing CPU
hotplug.
The old order:
* clean L1 by flush_cache_all
* exit SMP
* CPU shutdown
Adapt to:
* disable L1 data cache by clear C bit
* clean L1 by v7_flush_dcache_louis
* exit SMP
* CPU shutdown
For CPU hotplug case, it's no need to do "flush_cache_all". And we should
disable L1 data cache before clean L1 data cache. Then leaving the SMP
coherency.
Signed-off-by: Joseph Lo <josephl@nvidia.com> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
Joseph Lo [Thu, 3 Jan 2013 07:31:31 +0000 (15:31 +0800)]
ARM: tegra30: fix power up sequence for boot_secondary
The power up sequence is different on the cold boot CPU and the CPU
that resumed from the hotplug. For the cold boot CPU, it was been power
gated as default. To power up the cold boot CPU, the power should be
un-gated by un toggling the power gate register manually.
For the CPU that resumed from the hotplug, after un-halted the CPU. The
flow controller will un-gate the power of the CPU. No need to manually
control, just wait the power be resumed and continue the power up
sequence after the CPU power is ready.
Based on the work by:
Varun Wadekar <vwadekar@nvidia.com>
Signed-off-by: Joseph Lo <josephl@nvidia.com> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
Richard Zhao [Fri, 21 Dec 2012 00:09:55 +0000 (00:09 +0000)]
ARM: tegra: cpufreq: move clk_get/put out of function tegra_cpu_init/exit
tegra_cpu_init/exit will be called every time one cpu core is online or
offline. And all cpu cores share same clocks, redundant clk_get/put
wast time, so I move them out.
Signed-off-by: Richard Zhao <linuxzsc@gmail.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
Stephen Warren [Wed, 2 Jan 2013 21:34:15 +0000 (14:34 -0700)]
ARM: tegra: fix Kconfig warnings when !SMP
Fix:
warning: (ARCH_TEGRA_2x_SOC) selects ARM_ERRATA_754327 which has unmet direct dependencies (CPU_V7 && SMP)
warning: (ARCH_TEGRA_2x_SOC) selects ARM_ERRATA_742230 which has unmet direct dependencies (CPU_V7 && SMP)
by selecting options only if SMP.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Stephen Warren [Tue, 23 Oct 2012 17:52:53 +0000 (11:52 -0600)]
ARM: tegra: move timer.c to drivers/clocksource/
Move arch/arm/mach-tegra/timer.c to drivers/clocksource/tegra20_timer.c
so that the code is co-located with other clocksource drivers, and to
reduce the size of the mach-tegra directory.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Currently __hw_perf_event_init has an err variable that's ignored right
until the end, where it's initialised, conditionally set, and then used
as a boolean flag deciding whether to return another error code.
This patch removes the err variable and simplifies the associated error
handling logic.
Signed-off-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
Mark Rutland [Fri, 18 Jan 2013 13:42:59 +0000 (13:42 +0000)]
ARM: perf: remove unnecessary checks for idx < 0
We currently check for hwx->idx < 0 in armpmu_read and armpmu_del
unnecessarily. The only case where hwc->idx < 0 is when armpmu_add
fails, in which case the event's state is set to
PERF_EVENT_STATE_INACTIVE.
The perf core will not attempt to read from an event in
PERF_EVENT_STATE_INACTIVE, and so the check in armpmu_read is
unnecessary. Similarly, if perf core cannot add an event it will not
attempt to delete it, so the WARN_ON in armpmu_del is unnecessary.
This patch removes these two redundant checks.
Signed-off-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
Mark Rutland [Fri, 18 Jan 2013 13:42:58 +0000 (13:42 +0000)]
ARM: perf: handle armpmu_register failing
Currently perf_pmu_register may fail for several reasons (e.g. being
unable to allocate memory for the struct device it associates with each
PMU), and while any error is propagated by armpmu_register, it is
ignored by cpu_pmu_device_probe and not propagated to the caller. This
also results in a leak of a struct arm_pmu.
This patch adds cleanup if armpmu_register fails, and updates the info
messages to better differentiate this type of failure from a failure to
probe the PMU type from the hardware or dt.
Signed-off-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
Joachim Eastwood [Mon, 14 Jan 2013 17:42:22 +0000 (10:42 -0700)]
ARM: at91: fix board-rm9200-dt after sys_timer conversion
After "ARM: delete struct sys_timer" board-rm9200-dt
fails compilation with the following error:
CC arch/arm/mach-at91/board-rm9200-dt.o
arch/arm/mach-at91/board-rm9200-dt.c:50:2: error: unknown field 'timer' specified in initializer
arch/arm/mach-at91/board-rm9200-dt.c:50:13: error: 'at91rm9200_timer' undeclared here (not in a function)
make[1]: *** [arch/arm/mach-at91/board-rm9200-dt.o] Error 1
make: *** [arch/arm/mach-at91] Error 2
This is a fall out from the timer conversion. Fix it by
converting board-rm9200-dt to use new timer init
function as well.
Signed-off-by: Joachim Eastwood <manabian@gmail.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Olof Johansson <olof@lixom.net>
Christoffer Dall [Tue, 18 Dec 2012 04:06:38 +0000 (04:06 +0000)]
ARM: Use implementor and part defines from cputype.h
Instead of decoding implementor numbers, part numbers and Xscale
architecture masks inline in the pmu probing function, use defines
and accessor functions from cputype.h, which can also be shared by
other subsystems, such as KVM.
Signed-off-by: Christoffer Dall <c.dall@virtualopensystems.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
Christoffer Dall [Tue, 18 Dec 2012 04:06:37 +0000 (04:06 +0000)]
ARM: Define CPU part numbers and implementors
Define implementor IDs, part numbers and Xscale architecture versions in
cputype.h. Also create accessor functions for reading the implementor,
part number, and Xscale architecture versions from the CPUID regiser.
Signed-off-by: Christoffer Dall <c.dall@virtualopensystems.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
projects / karo-tx-linux.git / log