Dave Airlie [Fri, 25 Feb 2011 03:37:02 +0000 (13:37 +1000)]
Merge branch 'drm-nouveau-next' of git://anongit.freedesktop.org/git/nouveau/linux-2.6 into drm-next
* 'drm-nouveau-next' of git://anongit.freedesktop.org/git/nouveau/linux-2.6: (50 commits)
drm/nv50: flesh out ZCULL init and match nvidia on later chipsets
drm/nv50: support for compression
drm/nv50-nvc0: delay GART binding until move_notify time
drm/nouveau: rename nouveau_vram to nouveau_mem
drm/nvc0: allow creation of buffers with any non-compressed memtype
drm/nv50-nvc0: unmap buffers from the vm when they're evicted
drm/nv50-nvc0: move vm bind/unbind to move_notify hook
drm/nv50-nvc0: restrict memtype to those specified at creation time
drm/nouveau: pass domain rather than ttm flags to gem_new()
drm/nv50: simplify bo moves now that they're all through the vm
drm/nouveau: remove no_vm/mappable flags from nouveau_bo
drm/nouveau: Fix pageflip event
drm/nouveau/vbios: parse more gpio tag bits from connector table
drm/nouveau: decode PFIFO DMA_PUSHER error codes
drm/nv50: fix typos in CCACHE error reporting
drm/nvc0: support for sw methods + enable page flipping
drm/nv50: enable page flipping
drm/nv50-nvc0: activate/update ds channel's framebuffer on modesets
drm/nv50-nvc0: initialise display sync channels
drm/nv50-nvc0: precalculate some fb state when creating them
...
Ben Skeggs [Thu, 10 Feb 2011 02:59:51 +0000 (12:59 +1000)]
drm/nv50-nvc0: delay GART binding until move_notify time
The immediate benefit of doing this is that on NV50 and up, the GPU
virtual address of any buffer is now constant, regardless of what
memtype they're placed in.
Ben Skeggs [Sun, 13 Feb 2011 21:34:55 +0000 (07:34 +1000)]
drm/nvc0: allow creation of buffers with any non-compressed memtype
This adds a table of known nvc0 memtypes, and modifies the validity check
to allow any non-compressed type. Support for Z compression will come at
a later point.
Ben Skeggs [Thu, 10 Feb 2011 03:41:01 +0000 (13:41 +1000)]
drm/nv50-nvc0: restrict memtype to those specified at creation time
Upcoming patches are going to enable full support for buffers that keep
a constant GPU virtual address whenever they're validated for use by
the GPU.
In order for this to work properly while keeping support for large pages,
we need to know if it's ever going to be possible for a buffer to end
up in GART, and if so, disable large pages for the buffer's VMA.
This is a new restriction that's not present in earlier kernel's, but
should not break userspace as the current code never attempts to validate
buffers into a memtype other than it was created with.
Ben Skeggs [Mon, 7 Feb 2011 04:18:37 +0000 (14:18 +1000)]
drm/nv50-nvc0: activate/update ds channel's framebuffer on modesets
The hw doesn't really appear to be designed to be used the way we have to
use it due to DRI2's design. This leads us to having to keep the flipped
fb support active at all times.
Ben Skeggs [Thu, 3 Feb 2011 05:46:14 +0000 (15:46 +1000)]
drm/nv50-nvc0: request and wait on notification of modeset completion
This should prevent a number of races from occuring, the most obvious of
which will be exposed when we start making use of the "display sync" evo
channel for page flipping. The DS channel will reject any command stream
that doesn't completely agree with the current "master" state.
Ben Skeggs [Thu, 3 Feb 2011 10:06:14 +0000 (20:06 +1000)]
drm/nv50-nvc0: switch to tasklet for display isr bh
We need to be able to have the bh run while possibly spinning waiting for
the EVO notifier to signal. This apparently happens in some circumstances
with preempt disabled, so our workqueue was never being run.
Ben Skeggs [Thu, 3 Feb 2011 10:10:49 +0000 (20:10 +1000)]
drm/nouveau: make vbios parser runnable from an atomic context
The nv50 display isr bh needs to be converted to a tasklet, which means
we can't sleep anymore. The places we execute vbios init tables are
rare, and not in any way performance critical, so this isn't a huge
problem.
Tejun Heo [Wed, 26 Jan 2011 16:49:18 +0000 (17:49 +0100)]
drm/nouveau: use system_wq instead of dev_priv->wq
With cmwq, there's no reason for nouveau to use a dedicated workqueue.
Drop dev_priv->wq and use system_wq instead. Each work item is sync
flushed when the containing structure is unregistered/destroyed.
Note that this change also makes sure that nv50_gpio_handler is not
freed while the contained work item is still running.
Signed-off-by: Tejun Heo <tj@kernel.org> Cc: David Airlie <airlied@linux.ie> Cc: dri-devel@lists.freedesktop.org Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Ben Skeggs [Wed, 2 Feb 2011 04:57:05 +0000 (14:57 +1000)]
drm/nv50: drop explicit yields in favour of smaller PFIFO timeslice
This gives a small, but noticeable performance gain at lower performance
levels, and unchanged at the higher ones.
With this commit, we're now using the same timeslice size as the NVIDIA
binary driver currently does, and dropping an unknown bit that NVIDIA
no longer appear to set.
Ben Skeggs [Wed, 2 Feb 2011 03:21:57 +0000 (13:21 +1000)]
drm/nv84: use vm offsets for semaphores
We may well be making more use of semaphores in the future, having the
entire VM available makes requiring DMA objects for each and every
semaphore block unnecessary.
Dave Airlie [Wed, 23 Feb 2011 02:06:39 +0000 (12:06 +1000)]
Merge branch 'stable/ttm.pci-api.v5' of git://git.kernel.org/pub/scm/linux/kernel/git/konrad/xen into drm-next
* 'stable/ttm.pci-api.v5' of git://git.kernel.org/pub/scm/linux/kernel/git/konrad/xen:
ttm: Include the 'struct dev' when using the DMA API.
nouveau/ttm/PCIe: Use dma_addr if TTM has set it.
radeon/ttm/PCIe: Use dma_addr if TTM has set it.
ttm: Expand (*populate) to support an array of DMA addresses.
ttm: Utilize the DMA API for pages that have TTM_PAGE_FLAG_DMA32 set.
ttm: Introduce a placeholder for DMA (bus) addresses.
Chris Wilson [Wed, 12 Jan 2011 21:11:33 +0000 (21:11 +0000)]
drm: Trim the GEM mmap offset hashtab
Using an order 19 drm_ht for the mmap offsets is a little obscene. That
means that will a fully populated GTT with every single object mmaped at
least once in its lifetime, there will be exactly one object in each
bucket.
Typically systems only have at most a few thousand objects, though you
may see a KDE desktop hit 50000. And most of those should never be
mapped... On my systems, just using an order 10 ht would still have an
average occupancy less than 1, so apply a small safety factor and
use an order 12 ht, like the other mmap offset ht.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Dave Airlie <airlied@redhat.com>
Chris Wilson [Wed, 26 Jan 2011 09:49:47 +0000 (09:49 +0000)]
drm: Mark constant arrays of drm_display_mode const
... and fixup some methods to accept the constant argument.
Now that constant module arrays are loaded into read-only memory, using
const appropriately has some benefits beyond warning the programmer
about likely mistakes.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Dave Airlie <airlied@redhat.com>
Ben Skeggs [Wed, 2 Feb 2011 00:27:10 +0000 (00:27 +0000)]
drm/ttm: call driver move_notify() when doing system->tt bo moves
Nouveau doesn't have enough information at ttm_backend_func.bind() time
to implement things like tiled GART, or to keep a buffer at a constant
address in the GPU virtual address space no matter where in physical
memory it's placed.
To resolve this, nouveau will handle binding of all buffers to the GPU
itself from the move_notify() hook. This commit ensures it's called
for all buffer moves.
Talked to Dave about the impact on radeon, which uses move_notify, it
doesn't look like anything should break there.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Thomas Hellstrom <thomas@shipmail.org> Signed-off-by: Dave Airlie <airlied@redhat.com>
Daniel Vetter [Fri, 18 Feb 2011 16:59:21 +0000 (17:59 +0100)]
radeon: move blit functions to radeon_asic.h
Reviewed-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Dave Airlie <airlied@redhat.com>
Daniel Vetter [Fri, 18 Feb 2011 16:59:20 +0000 (17:59 +0100)]
radeon: kill decls for inline functions
Reviewed-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Dave Airlie <airlied@redhat.com>
Daniel Vetter [Fri, 18 Feb 2011 16:59:19 +0000 (17:59 +0100)]
radeon: consolidate asic-specific function decls for r600 & later
Now all the asic specific stuff ist mostly hid in radeon_asic.*
Reviewed-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Dave Airlie <airlied@redhat.com>
Daniel Vetter [Fri, 18 Feb 2011 16:59:15 +0000 (17:59 +0100)]
drm: mm: add helper to unwind scan state
With the switch to implicit free space accounting one pointer
got unused when scanning. Use it to create a single-linked list
to ensure correct unwinding of the scan state.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Dave Airlie <airlied@redhat.com>
Daniel Vetter [Fri, 18 Feb 2011 16:59:14 +0000 (17:59 +0100)]
drm: mm: add api for embedding struct drm_mm_node
The old api has a two-step process: First search for a suitable
free hole, then allocate from that specific hole. No user used
this to do anything clever. So drop it for the embeddable variant
of the drm_mm api (the old one retains this ability, for the time
being).
With struct drm_mm_node embedded, we cannot track allocations
anymore by checking for a NULL pointer. So keep track of this
and add a small helper drm_mm_node_allocated.
Also add a function to move allocations between different struct
drm_mm_node.
v2: Implement suggestions by Chris Wilson.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Dave Airlie <airlied@redhat.com>
Daniel Vetter [Fri, 18 Feb 2011 16:59:12 +0000 (17:59 +0100)]
drm: mm: track free areas implicitly
The idea is to track free holes implicitly by marking the allocation
immediatly preceeding a hole.
To avoid an ugly corner case add a dummy head_node to struct drm_mm
to track the hole that spans to complete allocation area when the
memory manager is empty.
To guarantee that there's always a preceeding/following node (that might
be marked as hole_follows == 1), move the mm->node_list list_head to the
head_node.
The main allocator and fair-lru scan code actually becomes simpler.
Only the debug code slightly suffers because free areas are no longer
explicit.
Also add drm_mm_for_each_node (which will be much more useful when
struct drm_mm_node is embeddable).
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Dave Airlie <airlied@redhat.com>
Daniel Vetter [Fri, 18 Feb 2011 16:59:11 +0000 (17:59 +0100)]
drm/nouveau: don't munge in drm_mm internals
Nouveau was checking drm_mm internals on teardown to see whether the
memory manager was initialized. Hide these internals in a small
inline helper function.
Acked-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Dave Airlie <airlied@redhat.com>
If the TTM layer has used the DMA API to setup pages that are
TTM_PAGE_FLAG_DMA32 (look at patch titled: "ttm: Utilize the
DMA API for pages that have TTM_PAGE_FLAG_DMA32 set"), lets
use it when programming the GART in the PCIe type cards.
This patch skips doing the pci_map_page (and pci_unmap_page) if
there is a DMA addresses passed in for that page. If the dma_address
is zero (or DMA_ERROR_CODE), then we continue on with our old
behaviour.
[v2: Added a review-by tag]
Reviewed-by: Thomas Hellstrom <thomas@shipmail.org> Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> Tested-by: Ian Campbell <ian.campbell@citrix.com>
If the TTM layer has used the DMA API to setup pages that are
TTM_PAGE_FLAG_DMA32 (look at patch titled: "ttm: Utilize the dma_addr_t
array for pages that are to in DMA32 pool."), lets use it
when programming the GART in the PCIe type cards.
This patch skips doing the pci_map_page (and pci_unmap_page) if
there is a DMA addresses passed in for that page. If the dma_address
is zero (or DMA_ERROR_CODE), then we continue on with our old
behaviour.
Ben Skeggs [Mon, 7 Feb 2011 00:49:39 +0000 (10:49 +1000)]
drm/nv40: fix tiling-related setup for a number of chipsets
Due to the default case handling the older chipsets, a bunch of the newer
ones ended up having the wrong tiling regs used. This commit switches the
default case to handle the newest chipsets.
This also makes nv4e touch the "extra" tiling regs. "nv" doesn't touch
them for C51 but traces of the NVIDIA binary driver show it being done
there.
I couldn't find NV41/NV45 traces to confirm the behaviour there, but an
educated guess was taken at each of them.
Francisco Jerez [Thu, 3 Feb 2011 00:53:18 +0000 (01:53 +0100)]
drm/nv04-nv40: Fix NULL dereference when we fail to find an LVDS native mode.
Reported-by: Alex Buell <alex.buell@munted.org.uk> Signed-off-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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