Bjorn Helgaas [Wed, 7 Nov 2012 22:53:33 +0000 (15:53 -0700)]
Merge branch 'pci/taku-prt-cleanup' into next
* pci/taku-prt-cleanup:
PCI/ACPI: Request _OSC control before scanning PCI root bus
PCI: Don't pass pci_dev to pci_ext_cfg_avail()
PCI/ACPI: Add _PRT interrupt routing info before enumerating devices
ACPI: Pass segment/bus to _PRT add/del so they don't depend on pci_bus
Bjorn Helgaas [Wed, 7 Nov 2012 22:53:29 +0000 (15:53 -0700)]
Merge branch 'pci/yinghai-for-pci-root-bus-hotplug' into next
* pci/yinghai-for-pci-root-bus-hotplug:
PCI/ACPI: Remove acpi_root_driver in reverse order
PCI/ACPI: Delete host bridge _PRT during hot remove path
PCI/ACPI: Make acpi_pci_root_remove() stop/remove pci root bus
PCI: Add pci_stop_and_remove_root_bus()
PCI/ACPI: Assign unassigned resource for hot-added root bus
PCI: Move out pci_enable_bridges out of assign_unsigned_bus_res
PCI: Move pci_rescan_bus() back to probe.c
PCI: Separate out pci_assign_unassigned_bus_resources()
Bjorn Helgaas [Wed, 7 Nov 2012 22:53:24 +0000 (15:53 -0700)]
Merge branch 'pci/misc' into next
* pci/misc:
x86/PCI: Allow x86 platforms to use translation offsets
PCI/PM: Add comments for PME poll support for PCIe
PCI: Add PLX PCI 9050 workaround for some Meilhaus DAQ cards
PCI: Add workaround for PLX PCI 9050 BAR alignment erratum
PCI: Convert dev_printk(KERN_<LEVEL> to dev_<level>(
x86/PCI: Ignore _SEG on HP xw9300
PCI: Don't touch card regs after runtime suspend D3
Mike Yoknis [Wed, 7 Nov 2012 22:52:20 +0000 (15:52 -0700)]
x86/PCI: Allow x86 platforms to use translation offsets
The memory range descriptors in the _CRS control method contain an address
translation offset for host bridges. This value is used to translate
addresses across the bridge. The support to use _TRA values is present for
other architectures but not for X86 platforms.
For existing X86 platforms the _TRA value is zero. Non-zero _TRA values
are expected on future X86 platforms. This change will register that value
with the resource.
Signed-off-by: Mike Yoknis <mike.yoknis@hp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Mike Yoknis [Tue, 6 Nov 2012 21:42:04 +0000 (15:42 -0600)]
x86/PCI: Allow x86 platforms to use translation offsets
The memory range descriptors in the _CRS control method contain an address
translation offset for host bridges. This value is used to translate
addresses across the bridge. The support to use _TRA values is present for
other architectures but not for X86 platforms.
For existing X86 platforms the _TRA value is zero. Non-zero _TRA values
are expected on future X86 platforms. This change will register that value
with the resource.
Signed-off-by: Mike Yoknis <mike.yoknis@hp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Huang Ying [Fri, 26 Oct 2012 05:07:51 +0000 (13:07 +0800)]
PCI/PM: Add comments for PME poll support for PCIe
There are comments on why PME poll support is necessary for PCI
devices, but not for PCIe devices. That may lead to misunderstanding
that PME poll is only necessary for PCI devices. So add comments
related to PCIe PME poll to make it more clear.
The content of comments comes from the changelog of commit:
Ian Abbott [Mon, 29 Oct 2012 14:40:18 +0000 (14:40 +0000)]
PCI: Add PLX PCI 9050 workaround for some Meilhaus DAQ cards
The Meilhaus ME-2000i and ME-2600i data acquisition cards supported by
the Comedi "me_daq" driver use the PLX PCI 9050 PCI Target bridge chip
affected by the bug that prevents the chip's local configuration
registers being read from BAR0 or BAR1 base addresses that are an odd
multiple of 128 bytes. Use the PLX PCI 9050 quirk handler for these
devices to re-allocate affected regions to a 256-byte boundary.
Signed-off-by: Ian Abbott <abbotti@mev.co.uk> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Ian Abbott [Tue, 30 Oct 2012 17:25:53 +0000 (17:25 +0000)]
PCI: Add workaround for PLX PCI 9050 BAR alignment erratum
The PLX PCI 9050 PCI Target bridge controller has a bug that prevents
its local configuration registers being read through BAR0 (memory) or
BAR1 (i/o) if the base address lies on an odd 128-byte boundary, i.e. if
bit 7 of the base address is non-zero. This bug is described in the PCI
9050 errata list, version 1.4, May 2005. It was fixed in the
pin-compatible PCI 9052, which can be distinguished from the PCI 9050 by
checking the revision in the PCI header, which is hard-coded for these
chips.
Workaround the problem by re-allocating the affected regions to a
256-byte boundary. Note that BAR0 and/or BAR1 may have been disabled
(size 0) during initialization of the PCI chip when its configuration is
read from a serial EEPROM.
Currently, the fix-up has only been used for devices with the default
vendor and device ID of the PLX PCI 9050. The PCI 9052 shares the same
default device ID as the PCI 9050 but they have different PCI revision
codes.
Signed-off-by: Ian Abbott <abbotti@mev.co.uk> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Bjorn Helgaas [Mon, 29 Oct 2012 23:26:54 +0000 (17:26 -0600)]
x86/PCI: Ignore _SEG on HP xw9300
The xw9300 BIOS supplies _SEG methods that are incorrect, which results
in some LSI SCSI devices not being discovered. This adds a quirk to
ignore _SEG on this machine and default to zero.
When the BIOS "ACPI Bus Segmentation" option is enabled (as it is by
default), the _SEG methods of the PCI1 and PCI2 bridges return 1 and 2,
respectively. However, the BIOS implementation appears to be incomplete,
and we can't enumerate devices in those domains.
But if we assume PCI1 and PCI2 really lead to buses in domain 0,
everything works fine. Windows XP and Vista also seem to ignore
these _SEG methods.
Reference: http://bugs.debian.org/cgi-bin/bugreport.cgi?bug=543308
Reference: https://bugzilla.kernel.org/show_bug.cgi?id=15362 Reported-and-Tested-by: Sean M. Pappalardo <pegasus@renegadetech.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Dave Airlie [Mon, 29 Oct 2012 23:26:54 +0000 (17:26 -0600)]
PCI: Don't touch card regs after runtime suspend D3
If the driver takes care of state saving, don't touch any registers on it.
Optimus (dual-gpu) laptops seem to have their own form of D3cold, but
unfortunately enter it on normal D3 transitions via the ACPI callback.
So when we use runtime PM to transition to D3, the card disappears off
the PCI bus, however we then try to access registers on it in the
runtime suspend finish, which really doesn't work.
This patch checks whether the pci state is saved and doesn't attempt to hit
any registers after that point if it is.
(Looks okay to Rafael)
Signed-off-by: Dave Airlie <airlied@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
projects / karo-tx-linux.git / log