ENGR00269945: ARM: dts: add max7310 support for imx6qdl-sabreauto
On imx6qdl-sabreauto board, there are three IO expanders implemented by
max7310, which are all controlled by I2C3. And GPIO5_4 is steering the
I2C3_SDA availability, while GPIO1_15 is used to reset max7310.
ENGR00269945: pinctrl: support pinctrl setting assertion via gpios
It's pretty common that on some reference design or validation boards,
one pin could be used by two devices on board, and the pin route is
controlled by a GPIO. So to assert the pin for given device, not only
the pinmux controller in SoC needs to be set up properly but also the
GPIO needs to be pulled up/down.
The patch adds support of a device tree property "pinctrl-assert-gpios"
under client device node. It plays pretty much like a board level pin
multiplexer, and steers the pin route by controlling the GPIOs. When
client device has the property represent in its node, pinctrl device
tree mapping function will firstly pull up/down the GPIOs to assert the
pins for the device at board level.
[shawn.guo: cherry-pick commit e5a718edab82 from imx_3.10.y] Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
The pca953x type of devices, e.g. max7310, may have a reset which needs
to be handled to get the device start working. Add a device_reset()
call for that, and defer the probe if the reset controller for that is
not ready yet.
ENGR00269945: select ARCH_HAS_RESET_CONTROLLER for IMX
Move ARCH_HAS_RESET_CONTROLLER from HAVE_IMX_SRC to ARCH_MXC to have it
selected for the whole IMX family instead of SRC (System Reset
Controller), since GPIO could be another reset controller in many cases.
ENGR00269945: reset: add dummy device_reset() for !CONFIG_RESET_CONTROLLER build
Add dummy device_reset() function for !CONFIG_RESET_CONTROLLER build,
so that we do not have to add #ifdef CONFIG_RESET_CONTROLLER in every
single client device drivers that call the function.
[shawn.guo: cherry-pick commit a9c086f35277 from imx_3.10.y] Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
ENGR00269945: reset: register gpio-reset driver in arch_initcall
It's a little bit late to register gpio-reset driver at module_init
time, because gpio-reset provides reset control via gpio for other
devices which are mostly probed at module_init time too. And it
becomes even worse, when the gpio comes from IO expander on I2C bus,
e.g. pca953x. In that case, gpio-reset needs to be ready before I2C
bus driver which is generally ready at subsys_initcall time. Let's
register gpio-reset driver in arch_initcall() to have it ready early
enough.
The defer probe mechanism is not used here, because a reset controller
driver should be reasonably registered early than other devices. More
importantly, defer probe doe not help in some nasty cases, e.g. the
gpio-pca953x device itself needs a reset from gpio-reset driver start
working.
[shawn.guo: cherry-pick commit 7153f05108ef from imx_3.10.y] Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Philipp Zabel [Thu, 30 May 2013 09:09:00 +0000 (11:09 +0200)]
reset: Add driver for gpio-controlled reset pins
This driver implements a reset controller device that toggle a gpio
connected to a reset pin of a peripheral IC. The delay between assertion
and de-assertion of the reset signal can be configured via device tree.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Pavel Machek <pavel@ucw.cz>
[shawn.guo: cherry-pick commit 27e3604c82cb from imx_3.10.y] Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Conflicts:
drivers/reset/Makefile
ENGR00240988: ARM: dts: add gpu nodes for imx6q and imx6dl
It adds gpu nodes for imx6q and imx6dl.
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
[shawn.guo: cherry-pick commit dfbafe2b0b33 from imx_3.10.y, use macro
for clock IDs and IRQ trigger type, and add power-domains]
ENGR00240988: ARM: imx6q: add dma_zone_size for GPU limit
GPU has a limit on physical address that it accesses, which must be
below 2GiB. Since i.MX6Q/DL maps system memory at 0x10000000 (offset
256MiB), we set dma_zone_size as (SZ_2G - SZ_256M) to ensure that.
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
[shawn.guo: cherry-pick commit f12c42130ab4 from imx_3.10.y]
Shawn Guo [Mon, 16 Jun 2014 06:48:01 +0000 (14:48 +0800)]
ENGR00317981: gpu-viv: use runtime pm for VDDPU management
On kernel 3.14, we use generic power domain for VDDPU management. In
that case, GPU driver does not need to call regulator API to manage
VDDPU anymore. Instead, it only needs to call runtime pm, which is
already being used by the driver.
Philipp Zabel [Thu, 6 Mar 2014 09:58:48 +0000 (10:58 +0100)]
ARM: dts: imx6qdl: Allow disabling the PU regulator, add a enable ramp delay
The PU regulator is enabled during boot, but not necessarily always-on.
It can be disabled by the generic pm domain framework when the PU power
domain is shut down. The ramp delay of 150 us might be a bit conservative,
the value is taken from the Freescale kernel.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
[shawn.guo: http://thread.gmane.org/gmane.linux.drivers.devicetree/64973] Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Philipp Zabel [Thu, 6 Mar 2014 09:58:47 +0000 (10:58 +0100)]
ARM: dts: imx6sl: Add power-domain information to gpc node
The PGC that is part of GPC controls isolation and power sequencing of the
power domains. The PU power domain will be handled by the generic pm domain
framework. It needs a phandle to the PU regulator to turn off power when
the domain is disabled and a list of clocks to be enabled during powerup
for reset propagation.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
[shawn.guo: http://thread.gmane.org/gmane.linux.drivers.devicetree/64973] Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Philipp Zabel [Thu, 6 Mar 2014 09:58:46 +0000 (10:58 +0100)]
ARM: dts: imx6qdl: Add power-domain information to gpc node
The PGC that is part of GPC controls isolation and power sequencing of the
power domains. The PU power domain will be handled by the generic pm domain
framework. It needs a phandle to the PU regulator to turn off power when
the domain is disabled, and a list of phandles to all clocks that must be
enabled during powerup for reset propagation.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
[shawn.guo: http://thread.gmane.org/gmane.linux.drivers.devicetree/64973]
[shawn.guo: use macro for clock IDs] Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Philipp Zabel [Thu, 6 Mar 2014 09:58:45 +0000 (10:58 +0100)]
ARM: imx6: gpc: Add PU power domain for GPU/VPU
When generic pm domain support is enabled, the PGC can be used
to completely gate power to the PU power domain containing GPU3D,
GPU2D, and VPU cores.
This code triggers the PGC powerdown sequence to disable the GPU/VPU
isolation cells and gate power and then disables the PU regulator.
To reenable, the reverse powerup sequence is triggered after the PU
regulator is enabled again.
The GPU and VPU devices in the PU power domain temporarily need
to be clocked during powerup, so that the reset machinery can work.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
[shawn.guo: http://thread.gmane.org/gmane.linux.drivers.devicetree/64973] Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Philipp Zabel [Thu, 6 Mar 2014 09:58:44 +0000 (10:58 +0100)]
Documentation: Add device tree bindings for Freescale i.MX GPC
The i.MX6 contains a power controller that controls power gating and
sequencing for the SoC's power domains.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
[shawn.guo: http://thread.gmane.org/gmane.linux.drivers.devicetree/64973]
[shawn.guo: update property name to be 'power-domains'] Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Tomasz Figa [Thu, 8 May 2014 12:49:14 +0000 (14:49 +0200)]
drivercore: Bind/unbind power domain on probe/remove
On a number of platforms, devices are part of controllable power
domains, which need to be enabled before such devices can be accessed
and may be powered down when the device is idle to save some power.
This means that on systems that support power domain control using
generic power domains subsystem, it is necessary to add device to its
power domain before binding a driver to it and remove it from its power
domain after its driver is unbound to make sure that an unused device
does not affect power domain state.
Since this is not limited to particular busses and specific
archs/platforms, it is more convenient to do the above directly in
driver core, just as done with pinctrl default configuration. This patch
adds necessary code to really_probe() and __device_release_driver() to
achieve this and maintain consistent stack-like ordering of operations
happening when binding and unbinding a driver.
Signed-off-by: Tomasz Figa <t.figa@samsung.com> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Reviewed-by: Philipp Zabel <philipp.zabel@gmail.com>
[on i.MX6 GK802] Tested-by: Philipp Zabel <philipp.zabel@gmail.com> Reviewed-by: Mark Brown <broonie@linaro.org> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
[shawn.guo: http://thread.gmane.org/gmane.linux.kernel.samsung-soc/31029] Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Tomasz Figa [Thu, 8 May 2014 12:49:13 +0000 (14:49 +0200)]
base: power: Add generic OF-based power domain look-up
This patch introduces generic code to perform power domain look-up using
device tree and automatically bind devices to their power domains.
Generic device tree binding is introduced to specify power domains of
devices in their device tree nodes.
Backwards compatibility with legacy Samsung-specific power domain
bindings is provided, but for now the new code is not compiled when
CONFIG_ARCH_EXYNOS is selected to avoid collision with legacy code. This
will change as soon as Exynos power domain code gets converted to use
the generic framework in further patch.
Signed-off-by: Tomasz Figa <t.figa@samsung.com> Reviewed-by: Mark Brown <broonie@linaro.org> Reviewed-by: Kevin Hilman <khilman@linaro.org> Reviewed-by: Philipp Zabel <philipp.zabel@gmail.com>
[on i.MX6 GK802] Tested-by: Philipp Zabel <philipp.zabel@gmail.com> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
[shawn.guo: http://thread.gmane.org/gmane.linux.kernel.samsung-soc/31029] Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Shawn Guo [Mon, 16 Jun 2014 06:11:51 +0000 (14:11 +0800)]
ENGR00317981: regulator: anatop: force vddpu to use same voltage level as vddsoc
The anatop on i.MX6 requires that vddpu use the same voltage level as
vddsoc. It's a quick hacking to force the check whenever vddpu is
about to be enabled.
Axel Lin [Sat, 22 Feb 2014 04:53:18 +0000 (12:53 +0800)]
regulator: anatop: Remove checking control_reg in [set|get]_voltage_sel
Remove checking control_reg in [set|get]_voltage_sel and then convert to use
regulator_[set|get]_voltage_sel_regmap for [set|get]_voltage_sel callbacks.
The anatop-reg-offset property is a required property rather than optional
property. So the question is what is the meaning of setting anatop-reg-offset
to 0? If 0 is a valid setting for anatop-reg-offset and it has special meaning,
we had better document it in the binding document. Otherwise, remove the testing
for control_reg in the driver.
No anatop voltage regulator node in the dts files set anatop-reg-offset to 0.
So I think it's safe to remove testing if control_reg is 0.
Signed-off-by: Axel Lin <axel.lin@ingics.com> Signed-off-by: Mark Brown <broonie@linaro.org>
[shawn.guo: cherry-pick commit 114c5748d540 from upstream] Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Philipp Zabel [Tue, 11 Feb 2014 13:43:45 +0000 (14:43 +0100)]
regulator: anatop: Add bypass support to digital LDOs
The ARM, PU, and SOC LDOs in the i.MX6 PMU can operate
in bypass mode. This allows to use external switching
regulators for cpu voltage scaling.
Since bypass and power gating modes are not configured
with their own bits, but via the voltage target bitfield,
store bypass state to be restored when reenabling the
regulator.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Mark Brown <broonie@linaro.org>
[shawn.guo: cherry-pick commit d38018f2019c from upstream] Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Philipp Zabel [Tue, 11 Feb 2014 13:43:44 +0000 (14:43 +0100)]
regulator: anatop: Add power gating support to digital LDOs
The ARM, PU, and SOC LDOs in the i.MX6 PMU can completely gate
their power output. Since power gating is configured by writing
zero to the voltage target bitfield,, store a copy of the
voltage selector to be restored when reenabling the regulator.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Mark Brown <broonie@linaro.org>
[shawn.guo: cherry-pick commit 605ebd35f059 from upstream] Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Liu Ying [Tue, 20 Aug 2013 06:37:47 +0000 (14:37 +0800)]
ENGR00274172-1 ARM: imx6q: refactor some ldb related clocks
The ldb_di[0|1]_ipu_div dividers may divide their parent clock
frequencies by either 3.5 or 7. The non-integral dividers cannot
be dealt with the common clock framework, so they cannot be
registered as common clock dividers. So this patch adds a fixed
factor clock of 1/7 and introduces ldb_di[0|1]_div_sel multiplexers
so that the fixed factor clocks of 1/3.5 and 1/7 can be set to be
the parents of ldb_di[0|1]_div_sel multiplexers. The ldb_di[0|1]_podf
dividers are no longer used then.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
[shawn.guo: cherry-pick commit aae58d71b525 from imx_3.10.y] Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Conflicts:
Documentation/devicetree/bindings/clock/imx6q-clock.txt
arch/arm/mach-imx/clk-imx6q.c
Shawn Guo [Sun, 15 Jun 2014 11:35:10 +0000 (19:35 +0800)]
ARM: imx6qdl: switch to use macro for clock ID
Instead of using enum for clock ID, let's switch imx6qdl clock driver to
use macro. In this case, device tree can reuse these macros to improve
readability.
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
[shawn.guo: cherry-pick from community IMX tree]
The esai_ahb clock is derived from ahb and used to provide ESAI the
capability of register accessing and FSYS clock source for I2S clocks
dividing. The gate bits of this esai_ahb clock are shared with the
esai clock -- the baud clock, so we need to call imx_clk_gate2_shared()
for these two clocks.
Shawn Guo [Fri, 13 Jun 2014 09:19:47 +0000 (17:19 +0800)]
ENGR00317981: media: mxc_pxp_v4l2: change __s32 to __u32
Commit f90580ca0133 ([media] videodev2: Set vb2_rect's width and height
as unsigned) changes v4l2_rect's width and height from __s32 to __u32,
and thus we see the build error below.
CC drivers/media/platform/mxc/output/mxc_pxp_v4l2.o
drivers/media/platform/mxc/output/mxc_pxp_v4l2.c: In function ‘pxp_try_fmt_output_overlay’:
drivers/media/platform/mxc/output/mxc_pxp_v4l2.c:605:16: warning: comparison of distinct pointer types lacks a cast [enabled by default]
drivers/media/platform/mxc/output/mxc_pxp_v4l2.c:607:17: warning: comparison of distinct pointer types lacks a cast [enabled by default]
Liu Ying [Tue, 25 Jun 2013 09:13:33 +0000 (17:13 +0800)]
ENGR00268508 backlight:Correct the setting for bd props.fb_blank
The patch of "ENGR00264855 backlight: Support backlight shared by
multiple fbs" doesn't consider that bd->props.fb_blank could be
shared by several framebuffers which use the same backlight device.
This causes the pwm backlight wrongly check the fb blank status.
This patch corrects the setting for the fb blank status by
considering all the framebuffers in question to fix the issue.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit 68b97d114629f22f64b3d8c14d0a0b7d07d6ebb2)
[shawn.guo: cherry-pick commit 8a03a96fba08 from imx_3.10.y] Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Liu Ying [Thu, 30 May 2013 05:56:17 +0000 (13:56 +0800)]
ENGR00264855 backlight: Support backlight shared by multiple fbs
One backlight device may shared by multiple framebuffers.
We don't hope blanking one of the framebuffers may turn the
backlight off for all the other framebuffers, since they are
likely active to show display content. This patch adds logic
to record each framebuffer's backlight usage to determine the
backlight device use count and whether the backlight should be
turned on or off.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit 37cbf741e4dff1f757f3ade6bb861d9a2af70693)
[shawn.guo: cherry-pick commit d62e7e8a788b from imx_3.10.y] Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Robby Cai [Thu, 22 Aug 2013 06:35:09 +0000 (14:35 +0800)]
ENGR00275031-1 mx6sl fb: support lcdif framebuffer on 3.10
re-use the upstreaming mxsfb.c code.
- add the lcdif axi clock for register and dram access
- set the lcdif pix's parent as pll5_video to get most accurate pix clock
- add binding doc for lcdif dts
Signed-off-by: Robby Cai <R63905@freescale.com>
[shawn.guo: cherry-pick commit 423273b4437f from imx_3.10.y] Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Conflicts:
drivers/video/mxsfb.c
Shawn Guo [Thu, 12 Jun 2014 07:43:56 +0000 (15:43 +0800)]
ENGR00317981: pxp: use DMA_COMPLETE for dma completion status
DMA_SUCCESS is removed by commit 7db5f7274a0b (dmaengine: remove unused
DMA_SUCCESS). Let's follow commit 409bff6a0f46 (dmaengine: imx-sdma: use
DMA_COMPLETE for dma completion status) to use DMA_COMPLETE instead.
This is to fix the following build error.
CC drivers/dma/pxp/pxp_dma_v2.o
drivers/dma/pxp/pxp_dma_v2.c: In function ‘pxp_tx_status’:
drivers/dma/pxp/pxp_dma_v2.c:1512:9: error: ‘DMA_SUCCESS’ undeclared (first use in this function)
Shawn Guo [Fri, 13 Jun 2014 03:37:29 +0000 (11:37 +0800)]
ENGR00317981: drm: vivante: drm_platform_exit is gone
The function drm_platform_exit() is removed by commit e2577d455adb (drm:
rip out drm_platform_exit). To fix the build error below, we need to
call drm_put_dev directly.
CC drivers/gpu/drm/vivante/vivante_drv.o
drivers/gpu/drm/vivante/vivante_drv.c: In function ‘vivante_exit’:
drivers/gpu/drm/vivante/vivante_drv.c:100:3: error: implicit declaration of function ‘drm_platform_exit’ [-Werror=implicit-function-declaration]
Note, this only works with commit "ENGR00317981: drm: set drm_device
pointer into drvdata".
Shawn Guo [Fri, 13 Jun 2014 08:02:58 +0000 (16:02 +0800)]
ENGR00317981: drm: set drm_device pointer into drvdata
If drvdata is not used by platform driver, let's set drm_device
pointer into it. We take this as the default usage of drvdata,
and platform driver is free to overwrite it later as needed.
Shawn Guo [Fri, 13 Jun 2014 02:45:39 +0000 (10:45 +0800)]
ENGR00317981: drm: vivante: flag DRIVER_USE_MTRR is gone
The flag DRIVER_USE_MTRR is removed by commit 281856477cda (drm: rip out
drm_core_has_MTRR checks). Drop it from vivante driver to fix the build
error below.
CC drivers/gpu/drm/vivante/vivante_drv.o
drivers/gpu/drm/vivante/vivante_drv.c:72:21: error: ‘DRIVER_USE_MTRR’ undeclared here (not in a function)
Shawn Guo [Thu, 12 Jun 2014 06:02:43 +0000 (14:02 +0800)]
ENGR00317981: gpu-viv: use reinit_completion instead of INIT_COMPLETION
INIT_COMPLETION was removed by commit 62026aedaace (sched: remove
INIT_COMPLETION), so we're seeing the following build error.
CC drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_os.o
drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_os.c: In function ‘gckOS_Signal’:
drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_os.c:7506:9: error: implicit declaration of function ‘INIT_COMPLETION’ [-Werror=implicit-function-declaration]
Follow commit 16735d022f72 (tree-wide: use reinit_completion instead of
INIT_COMPLETION) to fix the error.
Shawn Guo [Thu, 12 Jun 2014 02:13:32 +0000 (10:13 +0800)]
ENGR00317981: mxc: forward mxc drivers to 3.14 kernel
Forward imx_3.10.y mxc drivers to 3.14 kernel. This includes all
the imx_3.10.y drivers in drivers/mxc folder except ASRC. We will try
to use upstream ASRC driver on 3.14 kernel.
Anson Huang [Wed, 12 Feb 2014 10:06:35 +0000 (18:06 +0800)]
thermal: imx: update formula for thermal sensor
Thermal sensor used to need two calibration points which are
in fuse map to get a slope for converting thermal sensor's raw
data to real temperature in degree C. Due to the chip calibration
limitation, hardware team provides an universal formula to get
real temperature from internal thermal sensor raw data:
Anson Huang [Thu, 8 Aug 2013 17:20:40 +0000 (13:20 -0400)]
ENGR00274056-1 thermal: add device cooling for thermal driver
cpu cooling is not enough when temperature is
too hot, as some devices may contribute a lot of heat
to SOC, such as GPU, so we need to add device cooling
as well, when system is too hot, devices can also take
their actions to lower SOC temperature.
when temperature cross the passive trip, device cooling
driver will send out notification, those devices who
register this devfreq_cooling notification will take
actions to lower SOC temperature.
Shawn Guo [Thu, 12 Jun 2014 02:56:24 +0000 (10:56 +0800)]
ENGR00317981: busfreq: fix the use of MT_MEMORY_NONCACHED
Since commit 2e2c9de207be (ARM: add permission annotations to MT_MEMORY*
mapping types), MT_MEMORY_NONCACHED is not available any more. Thus, we
see following build error.
CC arch/arm/mach-imx/busfreq_ddr3.o
arch/arm/mach-imx/busfreq_ddr3.c: In function ‘init_mmdc_settings’:
arch/arm/mach-imx/busfreq_ddr3.c:464:7: error: ‘MT_MEMORY_NONCACHED’ undeclared (first use in this function)
Fix it by using the new enum MT_MEMORY_RWX_NONCACHED.
Peter Chen [Mon, 24 Feb 2014 02:21:04 +0000 (10:21 +0800)]
usb: phy: mxs: Add sync time after controller clear phcd
After clear portsc.phcd, PHY needs 200us stable time for switch
32K clock to AHB clock.
Signed-off-by: Peter Chen <peter.chen@freescale.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
[shawn.guo: cherry-pick commit 47d1845ffac0 from upstream]
Peter Chen [Mon, 24 Feb 2014 02:21:03 +0000 (10:21 +0800)]
usb: phy: mxs: Add system suspend/resume API
We need this to keep PHY's power on or off during the system
suspend mode. If we need to enable USB wakeup, then we
must keep PHY's power being on during the system suspend mode.
Otherwise, we need to keep PHY's power being off to save power.
Signed-off-by: Peter Chen <peter.chen@freescale.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
[shawn.guo: cherry-pick commit bf7834380086 from upstream]
Peter Chen [Mon, 24 Feb 2014 02:21:02 +0000 (10:21 +0800)]
usb: phy: mxs: Add implementation of set_wakeup
When we need the PHY can be waken up by external signals,
we can call this API. Besides, we call mxs_phy_disconnect_line
at this API to close the connection between USB PHY and
controller, after that, the line state from controller is SE0.
Once the PHY is out of power, without calling mxs_phy_disconnect_line,
there are unknown wakeups due to dp/dm floating at device mode.
Signed-off-by: Peter Chen <peter.chen@freescale.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
[shawn.guo: cherry-pick commit 3f1265056be0 from upstream]
Peter Chen [Mon, 24 Feb 2014 02:21:01 +0000 (10:21 +0800)]
usb: phy: Add set_wakeup API
This API is used to set wakeup enable at PHY registers, in that
case, the PHY can be waken up from suspend due to external events,
like vbus change, dp/dm change and id change.
Signed-off-by: Peter Chen <peter.chen@freescale.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
[shawn.guo: cherry-pick commit 57bf9b09a6ad from upstream]
Peter Chen [Mon, 24 Feb 2014 02:21:00 +0000 (10:21 +0800)]
usb: phy: mxs: add controller id
It is used to access un-regulator registers according to
different controllers.
Signed-off-by: Peter Chen <peter.chen@freescale.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
[shawn.guo: cherry-pick commit 83be181b6422 from upstream]
Peter Chen [Mon, 24 Feb 2014 02:20:59 +0000 (10:20 +0800)]
usb: phy: mxs: Enable IC fixes for related SoCs
Two PHY bugs are fixed by IC logic, but these bits are not
enabled by default, so we enable them at driver.
The two bugs are: MXS_PHY_ABNORMAL_IN_SUSPEND and MXS_PHY_SENDING_SOF_TOO_FAST
which are described at code.
Signed-off-by: Peter Chen <peter.chen@freescale.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
[shawn.guo: cherry-pick commit 22db05ecf2ba from upstream]
Peter Chen [Mon, 24 Feb 2014 02:20:58 +0000 (10:20 +0800)]
usb: phy: mxs: change description of usb device speed
Change "high speed" to "HS"
Change "non-high speed" to "FS/LS"
Implementation of notify_suspend and notify_resume will be different
according to mxs_phy_data->flags.
Signed-off-by: Peter Chen <peter.chen@freescale.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
[shawn.guo: cherry-pick commit f6a158243e56 from upstream]
Peter Chen [Mon, 24 Feb 2014 02:20:57 +0000 (10:20 +0800)]
usb: phy: mxs: Add anatop regmap
It is needed by imx6 SoC series, but not for imx23 and imx28.
Signed-off-by: Peter Chen <peter.chen@freescale.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
[shawn.guo: cherry-pick commit 0d896538d836 from upstream]
Peter Chen [Mon, 24 Feb 2014 02:20:56 +0000 (10:20 +0800)]
usb: doc: phy-mxs: update binding for adding anatop phandle
Add anatop phandle which is used to access anatop registers to
control PHY's power and other USB operations.
Signed-off-by: Peter Chen <peter.chen@freescale.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
[shawn.guo: cherry-pick commit d9c130328d2e from upstream]
Peter Chen [Mon, 24 Feb 2014 02:20:55 +0000 (10:20 +0800)]
usb: phy: mxs: Add auto clock and power setting
The auto setting is used to open related power and clocks
automatically after receiving wakeup signal.
With this feature, the PHY's clock and power can be recovered
correctly from low power mode, it is guaranteed by IC logic.
Signed-off-by: Peter Chen <peter.chen@freescale.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
[shawn.guo: cherry-pick commit 1364414411ac from upstream]
Peter Chen [Mon, 24 Feb 2014 02:20:54 +0000 (10:20 +0800)]
usb: phy: mxs: Add platform judgement code
The mxs-phy has several bugs and features at different
versions, the driver code can get it through of_device_id.data.
Signed-off-by: Peter Chen <peter.chen@freescale.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
[shawn.guo: cherry-pick commit 2400780ea18a from upstream]
Peter Chen [Mon, 24 Feb 2014 02:20:53 +0000 (10:20 +0800)]
usb: doc: phy-mxs: Add more compatible strings
Add "fsl,imx6q-usbphy" for imx6dq and imx6dl, add
"fsl,imx6sl-usbphy" for imx6sl, and "fsl,imx23-usbphy"
is still a fallback for other strings.
Signed-off-by: Peter Chen <peter.chen@freescale.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
[shawn.guo: cherry-pick commit 14de8c3a62b9 from upstream]
Peter Chen [Wed, 19 Feb 2014 05:41:41 +0000 (13:41 +0800)]
usb: chipidea: udc: refine ep operation at isr_tr_complete_handler
- delete the warning message at interrupt handler, and adds judgement at
ep_enable, if non-ep0 requests ctrl transfer, it will indicate an error.
- delete hw_test_and_clear_setup_status which is a broken code
- Tested with g_mass_storage, g_ncm, g_ether
Cc: matthieu.castet@parrot.com Reported-by: Michael Grzeschik <mgr@pengutronix.de> Acked-by: Michael Grzeschik <mgr@pengutronix.de> Tested-by: Michael Grzeschik <mgr@pengutronix.de> Signed-off-by: Peter Chen <peter.chen@freescale.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
[shawn.guo: cherry-pick commit 64fc06c40e01 from upstream]
Peter Chen [Wed, 19 Feb 2014 05:41:40 +0000 (13:41 +0800)]
usb: chipidea: refine PHY operation
- Delete global_phy due to we can get the phy from phy layer now
- using devm_usb_get_phy to instead of usb_get_phy
- delete the otg_set_peripheral, which should be handled by otg layer
Signed-off-by: Peter Chen <peter.chen@freescale.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
[shawn.guo: cherry-pick commit c859aa65a7ec from upstream]
Troy Kisky [Fri, 20 Dec 2013 18:47:10 +0000 (11:47 -0700)]
ARM: dts: imx6qdl: use interrupts-extended for fec
We need to be able to override interrupts in board file to
workaround a hardware bug for ethernet interrupts
waking the processor by using interrupts-extended.
So, use interrupts-extended here as well.
ERR006687 ENET: Only the ENET wake-up interrupt request can wake the
system from Wait mode.
The ENET block generates many interrupts. Only one of these interrupt lines
is connected to the General Power Controller (GPC) block, but a logical OR
of all of the ENET interrupts is connected to the General Interrupt Controller
(GIC). When the system enters Wait mode, a normal RX Done or TX Done does not
wake up the system because the GPC cannot see this interrupt. This impacts
performance of the ENET block because its interrupts are serviced only when
the chip exits Wait mode due to an interrupt from some other wake-up source.
Adding MX6QDL_PAD_GPIO_6__ENET_IRQ is the 1st step to
workaround this problem.
The input reg is set to 0x3c to set IOMUX_OBSRV_MUX1 to ENET_IRQ.
The mux reg value is 0x11, so that the observable mux is routed to
this pin and to the gpio controller(sion bit). These magic values
come from Ranjani Vaidyanathan's patch:
"ENGR00257847-1 MX6Q/DL-Fix Ethernet performance issue when WAIT mode is active"
Fabio Estevam [Thu, 19 Dec 2013 23:08:52 +0000 (21:08 -0200)]
ARM: dts: imx6: Use 'vddarm' as the regulator name
Instead of calling the regulator for the ARM core as 'cpu', let's rename it
as 'vddarm', so that we keep a better consistency with the other internal
regulators:
vdd1p1: 800 <--> 1375 mV at 1100 mV
vdd3p0: 2800 <--> 3150 mV at 3000 mV
vdd2p5: 2000 <--> 2750 mV at 2400 mV
vddarm: 725 <--> 1450 mV at 1150 mV
vddpu: 725 <--> 1450 mV at 1150 mV
vddsoc: 725 <--> 1450 mV at 1200 mV
Nicolin Chen [Sat, 8 Feb 2014 02:14:28 +0000 (10:14 +0800)]
ARM: dts: imx: specify the value of audmux pinctrl instead of 0x80000000
We must specify the value of audmux pinctrl if we want to use pinctrl_pm().
Thus change bypass value 0x80000000 to what we exactly need.
This patch also seperately unset PUE bit for TXD so that IOMUX won't pull
up/down the pin after turning into tristate. When we use SSI normal mode to
playback monaural audio via I2S signal, there'd be a pulled curve occur to
its signal at the second slot if setting PUE bit for TXD. And it will make
the second channel to play a constant noise. So by keeping the signal level
in the second slot, we can get a constant high level signal (-1) or a low
level one (0).
Shawn Guo [Fri, 7 Feb 2014 15:22:50 +0000 (23:22 +0800)]
ARM: dts: imx6: use generic node name for fixed regulator
The device tree specification recommends that generic name should be
used for nodes. So instead of naming those fixed regulator nodes
arbitrarily, let's use the generic name 'regulator@num' for those nodes.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
[shawn.guo: cherry-pick commit 56160e3361c6 from upstream]
Shawn Guo [Mon, 4 Nov 2013 02:49:04 +0000 (10:49 +0800)]
ARM: dts: imx6sl: make pinctrl nodes board specific
Currently, all pinctrl setting nodes are defined in <soc>.dtsi, so that
boards that share the same pinctrl setting do not have to define it time
and time again in <board>.dts. However, along with the devices and use
cases being added continuously, the pinctrl setting nodes under iomuxc
becomes more than expected. This bloats device tree blob for particular
board unnecessarily since only a small subset of those pinctrl setting
nodes will be used by the board. It impacts not only the DTB file size
but also the run-time device tree lookup efficiency.
The patch moves all the pinctrl data into individual boards as needed.
With the changes, the pinctrl setting nodes becomes local to particular
board, and it makes no sense to continue numbering the setting for
given peripheral. Thus, all the pinctrl phandler name gets updated to
have only peripheral name in there.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
[shawn.guo: cherry-pick from commit fffaa65dc463 upstream]
Shawn Guo [Wed, 23 Oct 2013 07:36:09 +0000 (15:36 +0800)]
ARM: dts: imx6qdl: make pinctrl nodes board specific
Currently, all pinctrl setting nodes are defined in <soc>.dtsi, so that
boards that share the same pinctrl setting do not have to define it time
and time again in <board>.dts. However, along with the devices and use
cases being added continuously, the pinctrl setting nodes under iomuxc
becomes more than expected. This bloats device tree blob for particular
board unnecessarily since only a small subset of those pinctrl setting
nodes will be used by the board. It impacts not only the DTB file size
but also the run-time device tree lookup efficiency.
The patch moves all the pinctrl data into individual boards as needed.
With the changes, the pinctrl setting nodes becomes local to particular
board, and it makes no sense to continue numbering the setting for
given peripheral. Thus, all the pinctrl phandler name gets updated to
have only peripheral name in there.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
[shawn.guo: cherry-pick commit 817c27a128e1 from upstream]
Anson Huang [Wed, 12 Feb 2014 09:57:02 +0000 (17:57 +0800)]
ARM: dts: imx6q: add 852MHz setpoint for CPU freq
According to datasheet, i.MX6Q has setpoint of 852MHz
which is exclusive with 996MHz, the fuse map of speed_grading
defines the max speed of ARM, here we add this 852MHz
setpoint opp info, kernel will check the speed_grading
fuse and remove all illegal setpoints.
Anson Huang [Thu, 19 Dec 2013 14:16:48 +0000 (09:16 -0500)]
ARM: dts: imx6q: add vddsoc/pu setpoint info
i.MX6Q needs to update vddarm, vddsoc/pu regulators when cpu freq
is changed, each setpoint has different voltage, so we need to
pass vddarm, vddsoc/pu's freq-voltage info from dts together.
Anson Huang [Mon, 16 Dec 2013 21:07:37 +0000 (16:07 -0500)]
ARM: dts: imx6q: update setting of VDDARM_CAP voltage
According to datasheet, VDD_CACHE_CAP must not exceed VDDARM_CAP
by more than 200mV, as all of i.MX6Q boards' VDD_CACHE_CAP currently
are connected to VDDSOC_CAP, so we need to follow this rule by
increasing VDDARM_CAP's voltage.
It's quite common on i.MX that one gate bit controls the gating of
multiple clocks, i.e. this is a shared gate. The patch adds the
function imx_clk_gate2_shared() for such case. The clocks controlled
by the same gate bits should call this function with a pointer to a
single share count variable, so that the gate bits will only be
operated on the first enabling and the last disabling of these shared
gate clocks.
Thanks to Gerhard Sittig <gsi@denx.de> for this idea.
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
[shawn.guo: cherry-pick commit f9f28cdf2167 from upstream]
The imx clk-gate2 driver implements an i.MX specific gate clock, which
has two bits controlling the gate states. While this is a completely
separate gate driver from the common clk-gate one, it reuses the common
clk_gate structure. Such reusing makes the extending of clk_gate2
clumsy. Let's define struct clk_gate2 on our own to make the driver
independent of the common clk-gate one, and ease the clk_gate2 extending
at a later time.
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
[shawn.guo: cherry-pick commit 54ee1471f820 from upstream]
Philipp Zabel [Mon, 14 Apr 2014 14:20:40 +0000 (16:20 +0200)]
ARM: i.MX6: ipu_di_sel clocks can set parent rates
To obtain exact pixel clocks, allow the DI clock selectors to influence
the PLLs that they are derived from.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Tested-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
[shawn.guo: cherry-pick commit 4591b13289b5 from upstream]
projects / karo-tx-linux.git / log