Danny Nold [Mon, 24 Oct 2011 16:11:17 +0000 (11:11 -0500)]
ENGR00160692 - MXC HDMI: Unbalanced clk disable
HDMI IAHB clock was capable of being disabled twice consecutively
due to a race condition between enabling the HDMI interrupts
and disabling the HDMI clock. A spinlock has been added to protect
against the race condition.
Another race condition was present due to the driver handling
HPD (hotplug detect) and RX Sense interrupts separately. Only HPD
interrupts handled now, simplifying enable/disable flow and
eliminating the race condition.
One final race condition fixed during HDMI driver initialization.
IRQ request moved to after place where IAHB is disabled, to ensure
balanced enable/disable of IAHB clock.
Signed-off-by: Danny Nold <dannynold@freescale.com>
ENGR00160397: Fix build break caused by DVFS-CORE driver
loops_per_jiffy is a global variable for non-smp platforms.
For SMP platforms, loops_per_jiffy is a per_cpu variable.
Fix dvfs_core to adjust loops_per_jiffy for both configurations.
- Ensure HDMI clocks are disabled when leaving HDMI core probe function.
- Create HDMI core api to allow HDMI sub-drivers to init, enable, and
disable the HDMI IRQ. Required to optimally manage HDMI clocks,
allow IAHB to be disabled, and still have video and audio sub-drivers
able to receive interrupts.
- Update code to adjust for decoupled ISFR and IAHB clocks.
- Disable IAHB clocks whenever HDMI not plugged in.
Signed-off-by: Danny Nold <dannynold@freescale.com>
Anson Huang [Tue, 11 Oct 2011 12:15:21 +0000 (20:15 +0800)]
ENGR00159796 [MX6]Cooling of cpufreq should consider governor type
We need to consider governor type of cpufreq, previous
method is to change the cpufreq to the lower point, but
it would not work if the cpufreq governor is not userspace,
now we set the scaling max freq instead of cpu current freq,
this will make sure working for all the governor.
Anson Huang [Tue, 11 Oct 2011 12:03:16 +0000 (20:03 +0800)]
ENGR00159737 [Mx6]Add clock check for periph clk
For lpddr2 board, current freq only support up to
400MHz, in this case, periph clk will set to 400M
in uboot, so in clock init, we need to check
whether the ddr clock is set to 400M, if yes, then
we should set periph clk parent to pll2_pfd_400M.
Anson Huang [Sun, 9 Oct 2011 01:47:20 +0000 (09:47 +0800)]
ENGR00156635 [MX6]Dormant random resume fail
1. sometimes system can not resume successfully from
dormant mode, there is still some defect with L2 cache
array alive during dromant mode, add clean operation
before dormant to make sure data alignment between L2
and DRAM, after doing it, dormant mode can resume fine.
2. local time no need to do store and restore during
suspend/resume.
Eric Miao [Mon, 26 Sep 2011 02:46:27 +0000 (10:46 +0800)]
SAUCE: set correct rates before registering SPDIF codec DAI
BugLink: http://bugs.launchpad.net/bugs/855281
Playback/capture rates should be configured before the SPDIF codec
DAI is registered, according to the parameters that passed in by
the platform data. And this caused pulseaudio not working with the
SPDIF sound card.
Add work around to the reboot issue of SMP, with
SMP, all the CPUs need to do _rcu_barrier, if we
enqueue an rcu callback, we need to make sure CPU
tick to stay alive until we take care of those by
completing the appropriate grace period.
This work around only work when the reboot command
issue, so it didn't impact normal kernel feature.
Danny Nold [Thu, 22 Sep 2011 21:43:24 +0000 (16:43 -0500)]
ENGR00157457 - MXC HDMI: Add support for non-CEA spec video modes
- Updated PHY configuration code to support ranges of clock frequencies,
rather than just a small set of supported clock frequencies corresponding
to CEA-861 video modes. This means that PC monitor modes are now
supported.
- Updated color handling code to ensure that a consistent set of
color mode defines are used.
- Fixed bug in how clock disable registers are configured
Signed-off-by: Danny Nold <dannynold@freescale.com>
Will Deacon [Wed, 20 Jul 2011 13:18:46 +0000 (14:18 +0100)]
ARM: twd: register clockevents device before enabling PPI
The smp_twd clockevents driver currently enables the local timer PPI
before the clockevents device is registered. This can lead to a kernel
panic if a spurious timer interrupt is generated before registration
has completed since the kernel will treat it as an IPI timer.
This patch moves the clockevents device registration before the IRQ
unmasking so that we can always handle timer interrupts once they can
occur.
Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
Danny Nold [Thu, 8 Sep 2011 20:38:25 +0000 (15:38 -0500)]
ENGR00156300 - EPDC fb: Move ISR code to work Q & replace spinlocks with mutexes
- Move the majority of code from the IRQ handler routine into a workqueue
routine. This should improve system interrupt latency.
- Change the spin_lock protecting EPDC queues into a mutex and change all
associated spin_lock calls into mutex calls.
Signed-off-by: Danny Nold <dannynold@freescale.com>
We can leave L2 cache alone during dormant,
just keep in mind don't access cache in dormant
process, then it should be OK without flushing
L2 cache, it will improve performance of suspend
and resume.
Jason Chen [Tue, 6 Sep 2011 06:06:09 +0000 (14:06 +0800)]
ENGR00155146 ipuv3: use mutex instead of spin lock
keep spin lock for irq function, but use mutex replace other
splin lock to provide better sync method.
Add _ipu_get/put function to check clock enable.
Jason Chen [Mon, 22 Aug 2011 02:46:22 +0000 (10:46 +0800)]
ENGR00155135-3 ipuv3 dev: add processing driver support
IPU's IC/IRT/VDI modules provide resizing/CSC/combination/de-interlacing
support, this patch make all these features into one processing driver.
A struct ipu_task is the interface between user and this driver, user
just need fill his task struct and queue it through ioctl, then wait
ipu hardware finish its job (now only support BLOCKING operation, not
support NO_BLOCK operation).
Pls refer to inlcude/linux/ipu.h for structure information and unit test
for usage.
Jason Chen [Mon, 22 Aug 2011 02:25:51 +0000 (10:25 +0800)]
ENGR00155135-2 ipuv3 dev: add processing driver support
IPU's IC/IRT/VDI modules provide resizing/CSC/combination/de-interlacing
support, this patch make all these features into one processing driver.
A struct ipu_task is the interface between user and this driver, user
just need fill his task struct and queue it through ioctl, then wait
ipu hardware finish its job (now only support BLOCKING operation, not
support NO_BLOCK operation).
Pls refer to inlcude/linux/ipu.h for structure information and unit test
for usage.
Jason Chen [Mon, 22 Aug 2011 02:24:49 +0000 (10:24 +0800)]
ENGR00155135-1 ipuv3 dev: add processing driver support
IPU's IC/IRT/VDI modules provide resizing/CSC/combination/de-interlacing
support, this patch make all these features into one processing driver.
A struct ipu_task is the interface between user and this driver, user
just need fill his task struct and queue it through ioctl, then wait
ipu hardware finish its job (now only support BLOCKING operation, not
support NO_BLOCK operation).
Pls refer to inlcude/linux/ipu.h for structure information and unit test
for usage.
ENGR00155880 USB device: Fix RNDIS Full Speed hang during initialization
When setup irq is received, the status phase of the transfer is primed
on ep0 before the data phase. The usb requests are added to the list
of transfer descriptors (maintained by driver) in reverse of their
expected completion order. Completion order is data followed by status,
however the list of tds contains status followed by data.
Upon completion of the data request, the irq handler proceeds to check
the 1st td in the list -- the status request. In full speed mode,
the status phase has not yet completed at this time, so the td's
ACTIVE bit is still set. This leads irq handler to ignore the completion
interrupt without checking the actual td for the data request that caused
the interrupt.
In high speed mode, this issue does not bear itself out because the status
request also completes by the time the irq handler goes to process the data
completion interrupt.
The simple fix for this issue is to prime the status request AFTER the data
request, so that the list of tds maintained by the driver contains the tds
in the order of expected completion.
Current thermal reading formula is not accurate,
and different board has different value, previous
setting of trip point setting is too low, and some
boards can reach hot and critical point easily, so
change the trip point as below:
critical : 50 -> 100 C
hot : 40 -> 90 C
active : 30 -> 80 C
these trip points value can also be changed via echo
an value into /sys/class/thermal/thermal_zone0/trip..
ENGR00155981: MX6: Fix crash caused by cpufreq during suspend/resume
Random crashes occur in CPUFREQ code when resuming from suspend.
The root cause is due to freeing and allocating of common data structure
(frequency table) shared among all the CPUs.
Fix the code by ensuring that the common data structure is only
created and deleted once.
Danny Nold [Fri, 2 Sep 2011 03:46:05 +0000 (22:46 -0500)]
ENGR00154436-2 - MXC HDMI: Support complete feature set
- Cleaned up video mode configuration in HDMI driver
- Add support for configurable ipu-to-hdmi mappings
- Add hotplug support.
- Adapt interrupt handling to account for sharing interrupt with HDMI audio
- Remove audio configuration
- Change code to only use CEA HDMI modes
- Add support for AVI InfoFrame
- Add aspect ratio to EDID mode data
- Add rounding support to IPU pix clk setup
- Add powerdown/powerup flow
- Support FB notifications
- Remove build warnings
Signed-off-by: Danny Nold <dannynold@freescale.com>
Danny Nold [Fri, 2 Sep 2011 21:45:14 +0000 (16:45 -0500)]
ENGR00154436-1 - MACH-MX6: MXC HDMI updates to support full feature set
- Corrected logic bug in how GPR registers are set
- Add support for configurable ipu-to-hdmi mappings
- Add aspect ratio to EDID mode data
- Expanded HDMI register field defines
- Removed HDMI platform data now handled by HDMI core in MFD
Signed-off-by: Danny Nold <dannynold@freescale.com>
1. We should enable mmdc_ch0 clock in init to make
its usecount > 0, or ipu's parent is mmdc_ch0,
when ipu enable/disable clock, mmdc_ch0 will be
also enable/disable, cause system hang when disable.
2. Remove build warning of unuse variable.
Tony Lin [Wed, 31 Aug 2011 05:28:37 +0000 (13:28 +0800)]
ENGR00155612-4 [mx6q]change the delay after clock frequence change to 1ms
100ms is too long delay, thus it impact other tasks scheduling.
for example, nfs reports timeout if two sd card is inserted because the
100ms delay occupies cpu too long.
1ms value is evaluated by IC engineer.
Tony Lin [Wed, 31 Aug 2011 05:28:37 +0000 (13:28 +0800)]
ENGR00155612-3 [mx6q]add delay after cmd6 for eMMC compatibility
sandisk eMMC4.4 cards need a 1ms delay after cmd6 (switch cmd)
which is confirm by sandisk errata.
add 1ms delay after cmd6 to provide more robustness and compatiblity
of our driver supporting eMMC4.4 cards.
projects / karo-tx-linux.git / log