dwc3 can do only max packet aligned transfers. So in case request length
is not max packet aligned and is bigger than DWC3_EP0_BOUNCE_SIZE
two chained TRBs is required to handle the transfer.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
In the linux kernel, non cacheable buffers are used. However in uboot
since there are no APIs to allocate non cacheable memory, all
the buffers should be flushed before using it.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
usb: dwc3: TI PHY: PHY driver for dwc3 in TI platforms
Added a single driver for both USB2 PHY programming and USB3 PHY
programming.
USB3 PHY is taken from drivers/phy/phy-ti-pipe3.c in linux kernel.
commit 56042e : phy: ti-pipe3: Fix suspend/resume and module reload.
USB2 PHY is taken from drivers/phy/phy-omap-usb2.c in linux kernel.
commit eb82a3 : phy: omap-usb2: Balance pm_runtime_enable() on probe
failure and remove.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
usb: dwc3: dwc3-omap: make dwc3-omap build in uboot
*) Changed the included header files to that used in u-boot.
*) Removed extcon_* APIs
*) Removed regulator_* APIs
*) Fixed other misc warnings
*) Added dwc3-omap.h to include the definitions of UTMI modes.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
include: dwc3-uboot: add a structure for populating platform data
Added a structure to populate dwc3 core platform data. The board file should
populate these platform data before invoking dwc3 driver.
This will be removed once we have dwc3 driver adapted to use the driver model.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
*) Changed the include header files to that used in u-boot.
*) Removed phy_* APIs
*) Removed jiffies and used a simple while loop
*) Used dma_alloc_coherent and dma_free_coherent APIs of u-boot
*) Fixed other misc warnings
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
include: usb: composite: add USB_GADGET_DELAYED_STATUS to avoid compilation error
Added USB_GADGET_DELAYED_STATUS to avoid the following compilation error.
error: ‘USB_GADGET_DELAYED_STATUS’ undeclared (first use in this function)
while compiling dwc3/ep0.c
While this is been added only to avoid compilation error, the complete fix
should be something like the one added in linux kernel. The complete fix
will be ported once we have the composite driver in u-boot look similar to
the one in linux kernel.
commit 1b9ba000177ee47bcc5b44c7c34e48e735f5f9b1
Author: Roger Quadros <roger.quadros@nokia.com>
Date: Mon May 9 13:08:06 2011 +0300
usb: gadget: composite: Allow function drivers to pause control transfers
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
Added resource_size_t type in order to get rid of the following
compilation error whiel building dwc3 gadget.
include/linux/ioport.h:19:2: error: unknown type name ‘resource_size_t’
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
usb: dwc3: gadget: make dwc3 gadget build in uboot
Did a bunch of things to get dwc3/gadget.c compile in u-boot without
build errors and warnings
*) Changed the included header files to that used in u-boot.
*) Used dma_alloc_coherent and dma_free_coherent APIs of u-boot
*) removed sg support
*) remove jiffies and used a simple while loop
*) removed irq support and added a function to call these interrupt handler.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
usb: dwc3: linux-compat: Add header for dwc3 linux compatibiltiy
Added a header file to include various linux specific APIs like
pr_debug, WARN_ WARN_ON_ONCE etc.. in order to avoid compilation
error while building dwc3 driver.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
arm: asm: dma-mapping: added dma_free_coherent API
Added dma_free_coherent corresponding to the dma_alloc_coherent in
dma-mapping.h in order to free memory allocated using dma_alloc_coherent.
This API is used in dwc3 driver.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
Changed the header files included in core.h and io.h to the u-boot header
files so that these files can be included in other dwc3 source files and
be compiled in uboot. Also added otg.h which has the defines for dr_mode.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
Removed most of the trace_* APIs from dwc3 driver since tracepoints are not
supported in u-boot. Replaced some of the trace_* API with dev_dbg/dev/vdbg.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Review-by: Lukasz Majewski <l.majewski@samsung.com>
usb: dwc3: Modify the file headers to u-boot format
Modified the file header to the format that is used in u-boot. Also
included in the header, the commit in linux kernel from which each of
these files are added.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
usb: gadget: udc: make udc-core compile in u-boot build
Make udc-core compile in u-boot by removing all linux specific
stuff and having only the bare minimal udc-core required for
usb gadget drivers. Also modified the file header to a format that is
generally being used in u-boot.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
usb: gadget: udc: add udc-core from linux kernel to u-boot
Added udc-core.c from linux kernel 3.19-rc1 (97bf6af1f9) to u-boot.
This will be adapted to work with u-boot in the
following patches.
Adding support for udc will help to seamlessly port dwc3 driver from
linux kernel to u-boot (since dwc3 uses udc-core) and it'll also help
to add support for multiple gadget controllers to be functional at the
same time.
All other gadget drivers can also be adapted to use udc-core.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
Stephen Warren [Sun, 12 Apr 2015 03:52:02 +0000 (21:52 -0600)]
usb: dwc2: retry NAK'd interrupt transfers
IIUC, interrupt transfers are NAK'd by devices until they wish to trigger
an interrupt, and e.g. EHCI controllers retry these in HW until they are
ACK'd. However, DWC2 doesn't seem to retry, so we need to do this in SW.
In practice, I've seen DWC2_HCINT_FRMOVRUN happen too. I'm not quite sure
what this error implies; perhaps it's related to how near the end of a
USB frame we're at when the interrupt transfer is initiated? Anyway,
retrying this temporary error seems to be necessary too.
With all these commits applied, both my USB keyboards (one LS Lenovo and
one FS Dell) work correctly when there is no USB hub between the SoC and
the keyboard; We still need split transactions to be implemented for hubs
to work.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Stephen Warren [Sat, 11 Apr 2015 03:05:22 +0000 (21:05 -0600)]
usb: dwc2: implement interrupt transfers
As best I can tell, there's no difference between bulk and interrupt
transfers in terms of how the HW should be programmed, at least given
that we're executing one transaction at a time rather than scheduling
them into frames for maximum throughput.
This patch ends up sharing the toggle bit state between bulk and
interrupt transfers on a particular EP. However I believe this is fine;
AFAIK a given EP either uses bulk or interrupt transfers and doesn't mix
them.
This patch doesn't do anything with the "interval" parameter for
interrupt transfers, but then most other USB controller drivers in U-Boot
don't either.
It turns out that one of my keyboards is happy to work using control
transfers but the other only gives non-zero "HID reports" via interrupt
transfers.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Stephen Warren [Sat, 11 Apr 2015 03:05:21 +0000 (21:05 -0600)]
usb: dwc2: correctly program hcchar for LS devices
A bit must be set in HCCHAR when communicating with low-speed devices.
I have no idea why there's no corresponding bit to distinguish between
full-speed and high-speed devices, but no matter; they all work now!
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Stephen Warren [Tue, 7 Apr 2015 02:28:39 +0000 (20:28 -0600)]
ARM: bcm2835: use phys_to_bus() for mbox
When we communicate with the VideoCore to perform property mailbox
transactions, that is a DMA operation as far as the property buffer
is concerned. Use phys_to_bus() on that buffer.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Stephen Warren [Wed, 25 Mar 2015 02:07:34 +0000 (20:07 -0600)]
ARM: bcm2835: implement phys_to_bus/bus_to_phys
The BCM283[56] contain both a L1 and L2 cache between the GPU (a/k/a
VideoCore CPU?) and DRAM. DMA-capable peripherals can also optionally
access DRAM via this same L2 cache (although they always bypass the L1
cache). Peripherals select whether to use or bypass the cache via the
top two bits of the bus address.
An IOMMU exists between the ARM CPU and the rest of the system. This
controls whether the ARM CPU's accesses use or bypass the L1 and/or L2
cache. This IOMMU is configured/controlled exclusively by the VideoCore
CPU.
In order for DRAM accesses made by the ARM core to be coherent with
accesses made by other DMA peripherals, we must program a bus address
into those peripherals that causes the peripheral's accesses to use the
same set of caches that the ARM core's accesses will use.
On the RPi1, the VideoCore firmware sets up the IOMMU to enable use of
the L2 cache. This corresponds to addresses based at 0x40000000.
On the RPi2, the VideoCore firmware sets up the IOMMU to disable use of
the L2 cache. This corresponds to addresses based at 0xc0000000.
This patch implements U-Boot's phys_to_bus/bus_to_phys APIs according
to those rules.
For full details of this setup, please see Dom Cobley's description at:
http://lists.denx.de/pipermail/u-boot/2015-March/208201.html
http://permalink.gmane.org/gmane.comp.boot-loaders.u-boot/215038
https://www.mail-archive.com/u-boot@lists.denx.de/msg166568.html
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Stephen Warren [Wed, 25 Mar 2015 02:07:33 +0000 (20:07 -0600)]
Create API to map between CPU physical and bus addresses
On some SoCs, DMA-capable peripherals see a different address space to
the CPU's physical address space. Create an API to allow platform-agnostic
drivers to convert between the two address spaces when programming DMA
operations.
This API will exist on all platforms, but will have a dummy implementation
when this feature is not required. Other platforms will enable
CONFIG_PHYS_TO_BUS and provide the required implementation.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Stephen Warren [Tue, 24 Mar 2015 05:01:01 +0000 (23:01 -0600)]
usb: dwc2: fix bulk transfers
When I created wait_for_chhltd(), I noticed that some instances of the
code it replaced expected the ACK bit to be set and others didn't. I
assumed this was an accidental inconsistency in the code, so wrote
wait_for_chhltd() to always expect ACK to be set. This code appeared to
work correctly for both enumeration of USB keyboards and operation of
USB Ethernet devices. However, this change broke USB Mass Storage (at
least my USB SD card reader). This change reverts to exactly the
original behaviour. I'm not sure why the ACK bit isn't always set
(perhaps a quirk in the USB HW or DWC2 controller), but the code works
this way!
Fixes: 5be4ca7d6ac8 ("usb: dwc2: unify waiting for transfer completion") Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Stephen Warren [Sun, 8 Mar 2015 17:08:14 +0000 (11:08 -0600)]
usb: dwc2: remove restriction on buffer length
Each USB transfer is split up into chunks that are held in an aligned
buffer. This imposes a limit on the size of each chunk, but no limit on
the total size of transferred data. Fix the logic in chunk_msg() not to
reject large transfers, but simply take the size of the aligned buffer
into account when calculating the chunk size.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Stephen Warren [Sun, 8 Mar 2015 17:08:13 +0000 (11:08 -0600)]
usb: dwc2: fix aligned buffer usage
The original aligned_buffer usage:
a) Uselessly copied data into the aligned buffer even for IN
transactions. Fix this my making the copy conditional.
b) Always programmed the HW to transfer to/from the start of the aligned
buffer. This worked fine for OUT transactions since the memcpy copied
the OUT data to this location too. However, for large IN transactions,
since the copy from the aligned buffer to the "client" buffer was
deferred until after all chunks were transferred. it resulted in each
chunk's transfer over-writing the data for the first transfer. Fix
this by copying IN data as soon as it's received.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Stephen Warren [Sun, 8 Mar 2015 05:48:54 +0000 (22:48 -0700)]
usb: dwc2: remove control_data_toggle[]
The control data toggle resets to DATA1 at the start of the data phase
of every setup transaction. We don't need a global variable to store
the value; we can just store it on the stack.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Stephen Warren [Sun, 8 Mar 2015 05:48:52 +0000 (22:48 -0700)]
usb: dwc2: refactor submit_bulk_msg to be common
Move the body of submit_bulk_msg() into new function chunk_msg(). This
can be shared with submit_control_msg() to reduce code duplication, and
allow control messages larger than maxpacket.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Stephen Warren [Thu, 9 Apr 2015 03:27:49 +0000 (21:27 -0600)]
usb: fix first descriptor fetch error handling
When fetching the first descriptor from a new device, only validate that
we received at least 8 bytes, not that we received the entire descriptor.
The reasoning is:
- The code only uses fields in the first 8 bytes, so that's all we need
to have fetched at this stage.
- The smallest maxpacket size is 8 bytes. Before we know the actual
maxpacket the device uses, the USB controller may only accept a single
packet (see the DWC2 note in the comment added in the commit).
Consequently we are only guaranteed to receive 1 packet (at least 8
bytes) even in a non-error case.
Fixes: 1a7758044b04 ("usb: Early failure when the first descriptor read
fails or is invalid") Cc: Paul Kocialkowski <contact@paulk.fr> Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
usb: Early failure when the first descriptor read fails or is invalid
This may happen when using an USB1 device on a controller that only supports
USB2 (e.g. EHCI). Reading the first descriptor will fail (read 0 byte), so we
can abort the process at this point instead of failing later and wasting time.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
This checks that a new USB device is correctly initialized and frees it if not.
In addition, this doesn't report that USB was started when no device was found.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
usb_storage:Fix USB storage capacity detection on 64 bit architectures
This patch fixes USB storage capacity detection breakage on 64-bit systems
which arises due to 'unsigned long' length difference. Old code assumes that
to be 32 bit and breaks because of inappropriate response buffer layout.
Also this fixes a number of build warnings and changes big-endian values
treatment style to be architecture-independent
This commit allows xHCI to use both 64 and 32 bit memory
physical addresses depending on architecture it's being built for.
Also it makes use of readq()/writeq() on 64-bit systems
Nishanth Menon [Mon, 9 Mar 2015 22:11:59 +0000 (17:11 -0500)]
ARM: Introduce erratum workaround for 798870
Add workaround for Cortex-A15 ARM erratum 798870 which says
"If back-to-back speculative cache line fills (fill A and fill B) are
issued from the L1 data cache of a CPU to the L2 cache, the second
request (fill B) is then cancelled, and the second request would have
detected a hazard against a recent write or eviction (write B) to the
same cache line as fill B then the L2 logic might deadlock."
Implementations for SoC families such as Exynos, OMAP5/DRA7 etc
will be widely different.
Every SoC has slightly different manner of setting up access to L2ACLR
and similar registers since the Secure Monitor handling of Secure
Monitor Call(smc) is diverse. Hence an weak function is introduced
which may be overriden to implement SoC specific accessor implementation.
Based on ARM errata Document revision 18.0 (22 Nov 2013)
Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Matt Porter <mporter@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Masahiro Yamada [Tue, 24 Feb 2015 13:26:20 +0000 (22:26 +0900)]
kconfig: switch to single .config configuration
When Kconfig for U-boot was examined, one of the biggest issues was
how to support multiple images (Normal, SPL, TPL). There were
actually two options, "single .config" and "multiple .config".
After some discussions and thought experiments, I chose the latter,
i.e. to create ".config", "spl/.config", "tpl/.config" for Normal,
SPL, TPL, respectively.
It is true that the "multiple .config" strategy provided us the
maximum flexibility and helped to avoid duplicating CONFIGs among
Normal, SPL, TPL, but I have noticed some fatal problems:
[1] It is impossible to share CONFIG options across the images.
If you change the configuration of Main image, you often have to
adjust some SPL configurations correspondingly. Currently, we
cannot handle the dependencies between them. It means one of the
biggest advantages of Kconfig is lost.
[2] It is too painful to change both ".config" and "spl/.config".
Sunxi guys started to work around this problem by creating a new
configuration target. Commit cbdd9a9737cc (sunxi: kconfig: Add
%_felconfig rule to enable FEL build of sunxi platforms.) added
"make *_felconfig" to enable CONFIG_SPL_FEL on both images.
Changing the configuration of multiple images in one command is a
generic demand. The current implementation cannot propose any
good solution about this.
[3] Kconfig files are getting ugly and difficult to understand.
Commit b724bd7d6349 (dm: Kconfig: Move CONFIG_SYS_MALLOC_F_LEN to
Kconfig) has sprinkled "if !SPL_BUILD" over the Kconfig files.
[4] The build system got more complicated than it should be.
To adjust Linux-originated Kconfig to U-Boot, the helper script
"scripts/multiconfig.sh" was introduced. Writing a complicated
text processor is a shell script sometimes caused problems.
Now I believe the "single .config" will serve us better. With it,
all the problems above would go away. Instead, we will have to add
some CONFIG_SPL_* (and CONFIG_TPL_*) options such as CONFIG_SPL_DM,
but we will not have much. Anyway, this is what we do now in
scripts/Makefile.spl.
I admit my mistake with my apology and this commit switches to the
single .config configuration.
It is not so difficult to do that:
- Remove unnecessary processings from scripts/multiconfig.sh
This file will remain for a while to support the current defconfig
format. It will be removed after more cleanups are done.
- Adjust some makefiles and Kconfigs
- Add some entries to include/config_uncmd_spl.h and the new file
scripts/Makefile.uncmd_spl. Some CONFIG options that are not
supported on SPL must be disabled because one .config is shared
between SPL and U-Boot proper going forward. I know this is not
a beautiful solution and I think we can do better, but let's see
how much we will have to describe them.
- update doc/README.kconfig
More cleaning up patches will follow this.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 24 Feb 2015 13:26:19 +0000 (22:26 +0900)]
kconfig: Adjust ordering so that defaults work as expected
At present defaults in arch-specific Kconfig files are ignored if the
top-level item comes ahead of it in include order. This means that it is
not possible to have a U-Boot default that architectures and boards can
override. This does not seem very useful.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Tested-by: Simon Glass <sjg@chromium.org> [ on nyan-big ] Cc: Stephen Warren <swarren@nvidia.com> Cc: Tom Warren <twarren@nvidia.com>
Peng Fan [Thu, 15 Jan 2015 06:22:32 +0000 (14:22 +0800)]
ARM: imx6: disable bandgap self-bias after boot
The self-bias circuit is used by the bandgap during startup.
Once the bandgap has stabilized, the self-bias circuit should
be disabled for best noise performance of analog blocks.
Also this bit should be disabled before the chip enters STOP mode or
when ever the regular bandgap is disabled.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
Peng Fan [Tue, 10 Feb 2015 06:46:34 +0000 (14:46 +0800)]
dm:gpio:mxc add DT support
This patch add DT support for mxc gpio driver.
There are one place using CONFIG_OF_CONTROL macro.
1. The U_BOOT_DEVICES and mxc_plat array are complied out. To DT,
platdata is alloced using calloc, so there is no need to use mxc_plat.
The following situations are tested, and all work fine:
1. with DM, without DT
2. with DM and DT
3. without DM
Since device tree has not been upstreamed, if want to test this patch.
The followings need to be done.
+ pieces of code does not gpio_request when using gpio_direction_xxx and
etc, need to request gpio.
+ move the gpio settings from board_early_init_f to board_init
+ define CONFIG_DM ,CONFIG_DM_GPIO and CONFIG_OF_CONTROL
+ Add device tree file and do related configuration in
`make ARCH=arm menuconfig`
These will be done in future patches by step.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Acked-by: Igor Grinberg <grinberg@compulab.co.il> Acked-by: Simon Glass <sjg@chromium.org>
Peng Fan [Tue, 10 Feb 2015 06:46:33 +0000 (14:46 +0800)]
dm:gpio:mxc add a bank_index entry in platdata
Add a new entry in platdata structure and intialize
bank_index in mxc_plat array.
This new entry can avoid using `plat - mxc_plat` by using
`plat->bank_index`.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Acked-by: Igor Grinberg <grinberg@compulab.co.il> Acked-by: Simon Glass <sjg@chromium.org>
Nikita Kiryanov [Tue, 3 Feb 2015 11:32:21 +0000 (13:32 +0200)]
lcd: split configuration_get_cmap
configuration_get_cmap() is multiple platform-specific functions stuffed into
one function. Split it into multiple versions, and move each version to the
appropriate driver to reduce the #ifdef complexity.
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Bo Shen <voice.shen@atmel.com> Tested-by: Josh Wu <josh.wu@atmel.com> Cc: Bo Shen <voice.shen@atmel.com> Cc: Simon Glass <sjg@chromium.org> Cc: Anatolij Gustschin <agust@denx.de>
Graeme Russ [Sun, 25 Jan 2015 01:07:51 +0000 (12:07 +1100)]
arm: mxs: Add debug outputs and comments to mxs SPL source files
It is difficult to track down fail to boot issues in the mxs SPL.
Implement the following to make it easier:
- Add debug outputs to allow tracing of SPL progress in order to track
where failure to boot occurs. DEUBUG and CONFIG_SPL_SERIAL_SUPPORT must
be defined to enable debug output in SPL
- Add TODO comments where it is not clear if the code is doing what it
is meant to be doing, even tough the board boots properly (these comments
refer to existing code, not to any code added by this patch)
Generate kernel video bootargs for sabresd, based on a list of needed video
interfaces ("video_interfaces" U-Boot env-var). The order of initialization
and video settings can be fully customized.
Signed-off-by: Nikolay Dimitrov <picmaster@mail.bg>
Tim Harvey [Mon, 18 May 2015 13:56:46 +0000 (06:56 -0700)]
imx: mx6: add display of CPU temperature grade in print_cpuinfo()
When CONFIG_IMX6_THERMAL is defined print the CPU temperature grade info
along with the current temperature.
Before:
CPU: Temperature 42 C
After:
CPU: Automotive temperature grade (-40C to 125C) at 42C
CPU: Industrial temperature grade (-40C to 105C) at 42C
CPU: Extended Commercial temperature grade (-20C to 105C) at 42C
Cc: Stefan Roese <sr@denx.de> Cc: Eric Nelson <eric.nelson@boundarydevices.com> Cc: Heiko Schocher <hs@denx.de> Cc: Nikita Kiryanov <nikita@compulab.co.il> Cc: Jon Nettleton <jon.nettleton@gmail.com> Cc: Jason Liu <r64343@freescale.com> Cc: Ye Li <b37916@freescale.com> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Christian Gmeiner <christian.gmeiner@gmail.com> Cc: Markus Niebel <Markus.Niebel@tq-group.com> Cc: Peng Fan <b51431@freescale.com> Tested-by: Nikolay Dimitrov <picmaster@mail.bg> Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Tim Harvey [Mon, 18 May 2015 13:56:45 +0000 (06:56 -0700)]
imx: mx6: add get_cpu_temp_grade to obtain cpu temperature grade from OTP
The MX6 has a temperature grade defined by OCOTP_MEM0[7:6] which is at 0x480
in the Fusemap Description Table in the reference manual. Return this value
as well as min/max temperature based on the value.
Note that the IMX6SDLRM and the IMX6SXRM do not indicate this in the
their Fusemap Description Table however Freescale has confirmed that these
eFUSE bits match the description within the IMX6DQRM and that they will
be added to the next revision of the respective reference manuals.
This has been tested with IMX6 Automative and Industrial parts.
Tim Harvey [Mon, 18 May 2015 14:02:25 +0000 (07:02 -0700)]
imx: mx6: display max cpu frequency in print_cpuinfo()
Display the max CPU frequency as well as the current running CPU frequency
if the max CPU frequency is available and differs from the current CPU
frequency.
Before:
CPU: Freescale i.MX6Q rev1.2 at 792 MHz
After - using an 800MHz IMX6DL (running at its max)
CPU: Freescale i.MX6DL rev1.1 at 792 MHz
After - using a 1GHz IMX6Q (not running at its max):
CPU: Freescale i.MX6Q rev1.2 996 MHz (running at 792 MHz)
Cc: Stefan Roese <sr@denx.de> Cc: Eric Nelson <eric.nelson@boundarydevices.com> Cc: Heiko Schocher <hs@denx.de> Cc: Nikita Kiryanov <nikita@compulab.co.il> Cc: Jon Nettleton <jon.nettleton@gmail.com> Cc: Jason Liu <r64343@freescale.com> Cc: Ye Li <b37916@freescale.com> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Christian Gmeiner <christian.gmeiner@gmail.com> Cc: Markus Niebel <Markus.Niebel@tq-group.com> Cc: Peng Fan <b51431@freescale.com> Tested-by: Nikolay Dimitrov <picmaster@mail.bg> Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Tim Harvey [Mon, 18 May 2015 14:02:24 +0000 (07:02 -0700)]
imx: mx6: add get_cpu_speed_grade_hz func to return MHz speed grade from OTP
The IMX6 has four different speed grades determined by eFUSE SPEED_GRADING
indicated by OCOTP_CFG3[17:16] which is at 0x440 in the Fusemap Description
Table. Return this frequency so that it can be used elsewhere.
Note that the IMX6SDLRM and the IMX6SXRM do not indicate this in the
their Fusemap Description Table however Freescale has confirmed that these
eFUSE bits match the description within the IMX6DQRM and that they will
be added to the next revision of the respective reference manuals.
These have been tested with IMX6 Quad/Solo/Dual-light 800Mhz and 1GHz grades.
Tim Harvey [Mon, 18 May 2015 14:07:02 +0000 (07:07 -0700)]
arm: mx6: ddr: set fast-exit on DDR3 if pd_fast_exit specified
Commit fa8b7d66f49f0c7bd41467fe78f6488d8af6976a introduced fast-exit support
to the MMDC however enabling it on the DDR3 got missed. Make sure we enable
it on the DDR3 as well.
Gateworks uses Micron memory as well as Winbond in MX6. We have found in
testing that we need to enable fast-exit for Winbond stability. Gateworks
boards are currently the only boards using the MX6 SPL and enabling
fast-exit mode.
projects / karo-tx-uboot.git / log