- Because mode_4 only use for handwriting mode, and
mode_3 use for power off mode, modify the waveform
mode for update requests.
- Use mode_2 for DU and A2, mode_1 for GU:
mode_A2 = mode_2, mode_du = mode_2;
mode_gu = mode_1;
Anson Huang [Fri, 25 May 2012 08:36:56 +0000 (16:36 +0800)]
ENGR00210547 [MX6]Enable I cache and branch prediction early
1. When resume, we can enable I cache and branch prediction
early to speed up the resume process;
2. L2 cache still need clean before suspend to make suspend/resume
modifiedre stable, add it back until we find the root cause.
Xinyu Chen [Fri, 25 May 2012 03:39:15 +0000 (11:39 +0800)]
ENGR00210850 mx6: boot failure with local timer and wait mode enabled
Previous patch only check the condition that GPT broadcast
event is ready or not before doing clock event switch.
It's not enough, as the clock switch from local timer to GPT
broadcast must be happen after GPT broadcast clock event setup
and current cpu's clock device switch to local timer clock event.
Otherwise, we will have chance that cpu exit the wait mode and
switch back clock event without local timer event setup correctly.
Rong Dian [Thu, 24 May 2012 08:05:31 +0000 (16:05 +0800)]
ENGR00210694 MX6 SABRESD:Enable IRQ for max11801
If miss to configure IRQ for max11801, the max11801 driver fails to
probe and returns error,sabresd battery driver also fails to sample
voltage by max11801 ADC.
Anson Huang [Wed, 23 May 2012 07:13:03 +0000 (15:13 +0800)]
ENGR00180495 [mx6]Fix suspend/resume issue caused by hotplug
When we kill a secondary cpu, we need to wait for it
die, then kill it from hardware setting. And to avoid
the cache unalign issue, we use hardware register to
send flag to inform main cpu to kill secondary cpu.
ARM: 7359/2: smp_twd: Only wait for reprogramming on active cpus
During booting of cpu1, there is a short window where cpu1
is online, but not active where cpu1 is occupied by waiting
to become active. If cpu0 then decides to schedule something
on cpu1 and wait for it to complete, before cpu0 has set
cpu1 active, we have a deadlock.
Typically it's this CPU frequency transition that happens at
this time, so let's just not wait for it to happen, it will
happen whenever the CPU eventually comes online instead.
Cc: Peter Zijlstra <peterz@infradead.org> Cc: stable@kernel.org Signed-off-by: Jonas Aaberg <jonas.aberg@stericsson.com> Reviewed-by: Rickard Andersson <rickard.andersson@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Will Deacon [Fri, 27 Apr 2012 11:56:24 +0000 (12:56 +0100)]
ARM: 7406/1: hotplug: copy the affinity mask when forcefully migrating IRQs
When a CPU is hotplugged off, we migrate any IRQs currently affine to it
away and onto another online CPU by calling the irq_set_affinity
function of the relevant interrupt controller chip. This function
returns either IRQ_SET_MASK_OK or IRQ_SET_MASK_OK_NOCOPY, to indicate
whether irq_data.affinity was updated.
If we are forcefully migrating an interrupt (because the affinity mask
no longer identifies any online CPUs) then we should update the IRQ
affinity mask to reflect the new CPU set. Failure to do so can
potentially leave /proc/irq/n/smp_affinity identifying only offline
CPUs, which may confuse userspace IRQ balancing daemons.
This patch updates migrate_one_irq to copy the affinity mask when
the interrupt chip returns IRQ_SET_MASK_OK after forcefully changing the
affinity of an interrupt.
Cc: stable@vger.kernel.org Reported-by: Leif Lindholm <leif.lindholm@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Thu, 21 Jul 2011 14:14:21 +0000 (15:14 +0100)]
ARM: CPU hotplug: ensure we migrate all IRQs off a downed CPU
Our selection of interrupts to consider for IRQ migration is sub-
standard. We were potentially including per-CPU interrupts in our
migration strategy, but omitting chained interrupts. This caused
some interrupts to remain on a downed CPU.
We were also trying to migrate interrupts which were not migratable,
resulting in an OOPS.
Instead, iterate over all interrupts, skipping per-CPU interrupts
or interrupts whose affinity does not include the downed CPU, and
attempt to set the affinity for every one else if their chip
implements irq_set_affinity().
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Thu, 21 Jul 2011 14:07:56 +0000 (15:07 +0100)]
ARM: CPU hotplug: pass in proper affinity mask on IRQ migration
Now that the GIC takes care of selecting a target interrupt from the
affinity mask, we don't need all this complexity in the core code
anymore. Just detect when we need to break affinity.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Thu, 21 Jul 2011 13:51:13 +0000 (14:51 +0100)]
ARM: CPU hotplug: fix abuse of irqdesc->node
irqdesc's node member is supposed to mark the numa node number for the
interrupt. Our use of it is non-standard. Remove this, replacing the
functionality with a test of the affinity mask.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
ARM: introduce handle_IRQ() not to dump exception stack
On Mon, Jul 11, 2011 at 3:52 PM, Russell King - ARM Linux
<linux@arm.linux.org.uk> wrote:
...
> The __exception annotation on a function causes this to happen:
>
> [<c002406c>] (asm_do_IRQ+0x6c/0x8c) from [<c0024b84>]
> (__irq_svc+0x44/0xcc)
> Exception stack(0xc3897c78 to 0xc3897cc0)
> 7c60: 4022d3204022e000
> 7c80: 0800007500001000c32273c0c03ce1c0c2b49b784022d000c2b420b400000001
> 7ca0: 00000000c3897cfc00000000c3897cc0c00afc54c002edd800000013ffffffff
>
> Where that stack dump represents the pt_regs for the exception which
> happened. Any function found in while unwinding will cause this to
> be printed.
>
> If you insert a C function between the IRQ assembly and asm_do_IRQ,
> the
> dump you get from asm_do_IRQ will be the stack for your function,
> not
> the pt_regs. That makes the feature useless.
>
When __irq_svc - or any of the other exception handling assembly code -
calls the C code, the stack pointer will be pointing at the pt_regs
structure.
All the entry points into C code from the exception handling code are
marked with __exception or __exception_irq_enter to indicate that they
are one of the functions which has pt_regs above them.
Normally, when you've entered asm_do_IRQ() you will have this stack
layout (higher address towards top):
pt_regs
asm_do_IRQ frame
If you insert a C function between the exception assembly code and
asm_do_IRQ, you end up with this stack layout instead:
pt_regs
your function frame
asm_do_IRQ frame
This means when we unwind, we'll get to asm_do_IRQ, and rather than
dumping out the pt_regs, we'll dump out your functions stack frame
instead, because that's what is above the asm_do_IRQ stack frame
rather than the expected pt_regs structure.
The fix is to introduce handle_IRQ() for no exception stack dump, so
it can be called with MULTI_IRQ_HANDLER is selected and a C function
is between the assembly code and the actual IRQ handling code.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
Russell King [Wed, 18 Jan 2012 15:59:45 +0000 (15:59 +0000)]
ARM: SMP: use a timing out completion for cpu hotplug
Rather than open-coding the jiffy-based wait, and polling for the
secondary CPU to come online, use a completion instead. This
removes the need to poll, instead we will be notified when the
secondary CPU has initialized.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Heiko Carstens [Tue, 23 Aug 2011 11:20:46 +0000 (13:20 +0200)]
nohz: Remove "Switched to NOHz mode" debugging messages
When performing cpu hotplug tests the kernel printk log buffer gets flooded
with pointless "Switched to NOHz mode..." messages. Especially when afterwards
analyzing a dump this might have removed more interesting stuff out of the
buffer.
Assuming that switching to NOHz mode simply works just remove the printk.
Sourcing AXI_CLK from PLL3_PFD_540M causes the system to
hang on resuming from STOP mode.
The main issue is that PFDs may sometimes hang/freeze
when their parent PLLs are powered on and then relocked
when exiting from STOP mode. To avoid this, PFDs must
be disabled before entering STOP and enabled after resume.
The fix is to move axi_clk to periph_clk before system
enters STOP and then restore it back to PLL3_PFD_540M
after resume.
Anson Huang [Wed, 23 May 2012 01:38:29 +0000 (09:38 +0800)]
ENGR00174974 [MX6]Fix CPU hotplug platform related issue
We need to turn of cache coherency of secondary core before
it is disable by core0, otherwise, the secondary core may be
waked by cache sync, and if it exit from wfi and access BUS,
meanwhile, core0 disable it from hardware, the whole SOC would
hang.
Robby Cai [Tue, 22 May 2012 08:55:18 +0000 (16:55 +0800)]
ENGR00210360 - EPDC: Fix regulator-related EPDC failure on MX6SL ARM2 CPU board
Its similar to ENGR00178581.
Remove call to regulator_has_full_constraints() from Max17135 EPD PMIC
initialization code, since leaving it enabled results in a failure of
system to load properly - key regulators are disabled when 'epdc' is added
to the kernel command line.
Fugang Duan [Sat, 19 May 2012 03:17:03 +0000 (11:17 +0800)]
ENGR00210075-3 - SPDC: Add Sipix driver
Add Sipix driver for electronic paper dispaly
- Support RGB565 & Y4 formats with 800x600 resolution
- Support synchronization update by waiting the last
request update completed.
- Support automated update using Linux deferred io mechanism
- Support for panning(y-direction)
- Support rotation with 90,180,and 270 degree.
- Initial integration with ePXP, output Y4 format
- Support specific waveform modes update.
- Support Snapshot, Queue and Queue Merge update sheeme.
- Support full and partial EPD screen updates.
mode_1 & mode_2: partial update
mode_0 & mode_3: full update
- Align waveform mode with EPDC as below:
mode_init = mode_0;
mode_gc4 = mode_2;
mode_A2 = mode_4, mode_du =mode_4;
mode_gc8 = mode_1, mode_gc16 = mode_1, mode_gc32 = mode_1;
Ryan QIAN [Mon, 21 May 2012 09:24:42 +0000 (17:24 +0800)]
ENGR00210160: [mx6]: mmc/sd illegal func call "clk_enable" in intr context
issue:
calling clk_enable in an interrupt context which will cause kernel bug.
- It is a temp workaround for calling 'clk_enable' in an interrupt context.
By redefine SDHCI_USE_LEDS_CLASS to SDHCI_USE_LEDS_CLASS_BROKEN to exclude
led ctrl support, it does not support mmc/sd LED ctrl with this patch.
- Per current driver structure, it's difficult to fix this issue in driver
layer. The fix for this issue needs adjustment to current driver structure
and using new clock management in kernel interface.
Wu Guoxing [Mon, 21 May 2012 01:24:29 +0000 (09:24 +0800)]
ENGR00209062-2: mx6dq and mx6dl dual camera support
dual camera support for mx6q and mx6dl:
1. let mipi and parallel camera working on different csi
2. the two camera can work independently and synchronously
3. the two camera will be registered and different video
device(/dev/video0, /dev/video1)
4. when both camera are working, the can not use the same
ipu channel, that is, when camera one using PRP_ENC_MEM
or PRP_VF_MEM channel, the other one can only use CSI_MEM
Wu Guoxing [Mon, 21 May 2012 01:21:12 +0000 (09:21 +0800)]
ENGR00209062-1: mx6dq and mx6dl dual camera support
dual camera support for mx6q and mx6dl:
1. let mipi and parallel camera working on different csi
2. the two camera can work independently and synchronously
3. the two camera will be registered and different video
device(/dev/video0, /dev/video1)
4. when both camera are working, the can not use the same
ipu channel, that is, when camera one using PRP_ENC_MEM
or PRP_VF_MEM channel, the other one can only use CSI_MEM
DLL ON/OFF code randomly hangs waiting for the CON_ACK bit
to be set when a CON_REQ is asserted.
Fix this by adding a delay after the MMDC automatic power savings
mode is disabled.
To avoid the ARM from accepting an interrupt in the dangerous
window, reduce the ARM core freq just before the sytem is
about to enter WAIT state.
Reduce the ARM freq so as to maintain 12:5 ARM_CLK to IPG
ratio. Use the ARM_PODF to drop the frequency.
In a multicore case the frequency is dropped only when all the
4 cores are going to be in WFI.
In case of single core environment, its easy to drop the ARM core
freq just before WFI since there is no need to identify the state of
the other cores.
Some other points to note:
1. If "mem_clk_on" is added to the command line, the memory clocks will
not be gated in WAIT mode. This will increase the system IDLE power.
This mode is valid only on MX6sl, MX6DQ TO1.2 and MX6DL TO1.1.
2. In case the IPG clk is too low (for ex 50MHz) and ARM is at 1GHz,
we cannot match the 12:5 ratio using ARM_PODF only. In this case,
donot clock gate the memories in WAIT mode (available on MX6SL,
MXDQ TO1.2 and MXDL TO1.1). For MXDQ TO1.1 and MX6DL TO1.0, disable
system wide WAIT entry in this case.
In STOP mode, always ensure that the memory clocks are gated, else
power impact will be significant.
Danny Nold [Thu, 17 May 2012 20:17:37 +0000 (15:17 -0500)]
ENGR00209883-1 - EPDC fb: Add support for MX 6SoloLite ARM2 board
- Add EPDC and Max17135 structures and initialization calls to
the MX6SL ARM2 board file
- Add IOMUX configuration defines and GPIO defines for EPDC/Max17135
- Remove prints/debug from EPDC-related clocks.
Signed-off-by: Danny Nold <dannynold@freescale.com>
B38613 [Fri, 18 May 2012 10:15:56 +0000 (18:15 +0800)]
ENGR00209686-2:sdio:suspend/resume issue
1.add MMC_PM_WAKE_SDIO_IRQ capability, it should be
used together with MMC_PM_KEEP_POWER although not support
SDIO wakeup in function.
2.add MMC_CAP_NONREMOVABLE to describe imx6's three sdhc
devices's removable feature.Now emmc is permanent,sdio and
sd is removable instead of all default were permanent before.
According to this feature, detimine whether reinit card
or not in resume.
B38613 [Fri, 18 May 2012 10:14:56 +0000 (18:14 +0800)]
ENGR00209686-1:sdio:suspend/resume issue
1.add MMC_PM_WAKE_SDIO_IRQ capability, it should be
used together with MMC_PM_KEEP_POWER although not support
SDIO wakeup in function.
2.add MMC_CAP_NONREMOVABLE to describe imx6's three sdhc
devices's removable feature.Now emmc is permanent,sdio and
sd is removable instead of all default were permanent before.
According to this feature, detimine whether reinit card
or not in resume.
Sandor Yu [Thu, 17 May 2012 07:28:54 +0000 (15:28 +0800)]
ENGR00182769 HDMI: No sound when playing audio in 480p mode
It is cause by HDMI audio driver can't get right pixel clock
from IPU driver if pixel clock source from HSP clock not from
DI clock.
HDMI driver get pixel clock by call clk_get_rate() function,
but the function return actually clock, in some videomode the
actually pixel clock is not right equal the pixel clock in CEA spec.
Get pixel clock from video mode struct instead of CCM register.
480P HDMI audio can work.
Adrian Alonso [Wed, 16 May 2012 22:34:24 +0000 (17:34 -0500)]
ENGR00209384-4 mxc_spdif: disable sym_err isr
* Disable symbol error interrupt when rx dpll is unlocked
This means that no spdif Rx data had been identified and
driver will keep issuing sym_err interrupt request.
* Add check to only execute capture_start/stop
functions if rx_active is set.
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Robin Gong [Thu, 17 May 2012 06:19:01 +0000 (14:19 +0800)]
ENGR00209633-2 I2C mx6sl pfuze: add pfuze board support for mx6sl arm2
1.add pmic board support file
2.add i2c support on board-mx6sl_arm2.c
3.update IOMUX setting for I2C pin for mx6sl arm2 board Signed-off-by: Robin Gong <B38343@freescale.com>
ENGR00209620 MX6-Disable PU Brown out detection in low power mode.
Ensure that the brown out detection of the PU regulator is
disabled before the regulator itself is disabled.
Keeping the detection enabled will generate an interrupt that
is not currently being handled in the BSP when the regulator is
disabled since its voltage is dropped to 0V. This will prevent
the system from entering complete WAIT state thus increasing the
power in the low power idle/audio usecase.
Adrian Alonso [Mon, 14 May 2012 23:50:53 +0000 (18:50 -0500)]
ENGR00209384-2 mxc_spdif: capture playback start function
* Add start capture/playback function
Start sequence for capturing/playing audio data.
* Remove caprure/playback prepere function hwd initialization
handled by trigger function when user/app starts capture/play
process.
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Adrian Alonso [Mon, 14 May 2012 23:43:37 +0000 (18:43 -0500)]
SAUCE remove unnecessary suspend/resume functions
BugLink: http://bugs.launchpad.net/bugs/882723
Disabling/re-enabling clocks is not necessary as it's done in *_startup()
and *_shutdown() functions, and shall be performed during suspend/resume.
This is causing warnings of un-matched clk_enable()/clk_disable()
Rework patch for imx_3.0.15 code base
Signed-off-by: Eric Miao <eric.miao@linaro.org> Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Fugang Duan [Wed, 16 May 2012 09:57:53 +0000 (17:57 +0800)]
ENGR00209520-03 - FEC : Add support for MX6SL MSL.
- Modify the the platform macro define like as cpu_is_xxx()
for supporting Mergrez chip.
- Config MIIGSK for FEC IP to enable RMII mode. MX25,MX53,
and MX6Sololite use FEC IP, which need to config the MIIGSK
registers memory map for RMII and MII.
- Correct device id_table entry name for differnt IP.
- Rewrite FEC MAC address by net_device address when reset FEC,
which can avoid invalid MAC address to result in FEC cannot
work.
Fugang Duan [Wed, 16 May 2012 10:27:09 +0000 (18:27 +0800)]
ENGR00209520-01 - MX6SL MSL : Add FEC support
Add FEC support for mx6-sololite:
- Add FEC pad iomux setting.
- Power on phy and init fec.
- Add devname to distinguish different IP.
- Use ANATOP as FEC clock source in default, remove redundant
config "FEC_CLOCK_FROM_ANATOP".
Wayne Zou [Wed, 16 May 2012 07:43:12 +0000 (15:43 +0800)]
ENGR00169375 IPU: Remove the warning message when doing 8:1 downsize
Remove Overflow message on resize coeff when resize from 1280*720 to 160*120
The IPU IC can not do exactly 8:1 downsize, but can be very close to 8:1
downsize.
Xinyu Chen [Tue, 15 May 2012 09:16:33 +0000 (17:16 +0800)]
ENGR00182786 mx6q sabresd: Add power/reset function for 3G modem
Add PCIE 3V3 power up/down routing if we do not have
pcie driver selected. And power up 3V3 in board init.
As the reset function of the hw board cannot reset the
modem power. So on kernel boot up, we must make sure
the 3g modem is reset correctly by gpio reset.
Jason Liu [Mon, 14 May 2012 13:41:05 +0000 (21:41 +0800)]
ENGR00182324-4 - MX6SL MSL: Enable L2 cache as OCRAM functionality
L2 cache can be configured to serve as OCRAM. This patch adds
code to check this configuration, and reset it to L2 cache function
before enabling the L2 cache.
Jason Liu [Mon, 14 May 2012 13:15:57 +0000 (21:15 +0800)]
ENGR00182324-3 - MX6SL MSL: Add clock support for i.MX 6SoloLite
Add clock support for i.MX 6SoloLite. A new clock file has been created
to reflect the substantial set of changes in the clocks used between
6SoloLite and other 6 series SoCs.
Signed-off-by: Jason Liu <r64343@freescale.com> Signed-off-by: Robby Cai <r63905@freescale.com>
Adrian Alonso [Mon, 14 May 2012 23:02:35 +0000 (18:02 -0500)]
ENGR00178459 mxc_spdif: fix read access for debug info
* Fix read register access for debug info
* Read from spdif registers with a disabled
spdif core clock leads to kernel hang.
* Avoid it by enabling/diabling core clk.
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Adrian Alonso [Fri, 11 May 2012 17:17:44 +0000 (12:17 -0500)]
ENGR00178459 mxc_spdif: clk_enable return checks
* Add clk_enable return checks, if clocks aren't enabled
writting/reading from spdif register will cause
system to become unresponsive.
* Remove spdif_audio_clk enable/disable calls
this clock is not assigned and is reposible for making
the system unresposive.
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Zhang Jiejing [Mon, 14 May 2012 06:22:11 +0000 (14:22 +0800)]
ENGR00209059-1 MX6: reboot: add reboot to special function
add reboot to special function like mfg download mode,
android fastboot, recovery mode.
It use ASRC register to enter mfgtool download mode and other function.
For android fastboot, recovery function it use ASRC_GPR10 bit 7-8 bit,
it will checked in uboot and clear after read.
Add this feature to improve recovery function, to avoid infinit looping
enter recovery mode if some thing goes wrong in fastboot mode.
Also add convient function for developer.
Xinyu Chen [Wed, 7 Mar 2012 02:17:21 +0000 (10:17 +0800)]
ENGR00176278 mx6: make local timer work with WAIT mode
As mx6q soc use one clock to provide for cpu and local timer,
the local timers will be stopped when enter wait mode.
This causes system hang when enter wait mode with local timer
enabled. So we should switch the clock event to GPT
broadcast clock event before entering wait mode, and disable
local timers. Todo this, following changes made:
* In arch_idle(), we check if the GPT broadcast clock
event is switched to one shot mode. If the kernel clocksource
is switched from jiffies one to GPT, then we can use GPT
as broadcast event. And switch from local timer to GPT broadcast
event before entering mx6q_wait. Otherwise, kernel will hange
if the SW jiffies clock source is used.
We call clockevents_notify to switch clock source.
* Remove the enable_wait_mode check in local timer setup.
* Always return 0 in GPT v2 timer's set_next_event routing.
All the GPTs are running in free run mode as what driver did.
So we should allow the GPT CNT register roll over to 0 when it
reaches 0xFFFFFFFF. And the next event written to compare register
can less than the current value in CNT.
If we refused to do roll over settings, the kernel will continues
to set_next_event to GPT when the next event is far away and
we return negative value. This is happend when one CPU is in idle
and no timewheel is being expired in short time.
Loren Huang [Fri, 11 May 2012 02:20:56 +0000 (10:20 +0800)]
ENGR00209022 Update gpu clock management code
-This patch from vivante.They need to bypass the
reference count in clock management code as they
may touch clock while they just want to change
power state.
projects / karo-tx-linux.git / log