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11 years agoENGR00182743-4 V4L2 output: Add non-interleaved YUV444 pixel format support
Wayne Zou [Tue, 3 Jul 2012 09:18:08 +0000 (17:18 +0800)]
ENGR00182743-4 V4L2 output: Add non-interleaved YUV444 pixel format support

Add non-interleaved YUV444 pixel format IPU_PIX_FMT_YUV444P support

Signed-off-by: Wayne Zou <b36644@freescale.com>
11 years agoENGR00182743-3 FB MXC: Add non-interleaved YUV444 pixel format support
Wayne Zou [Tue, 3 Jul 2012 09:16:37 +0000 (17:16 +0800)]
ENGR00182743-3 FB MXC: Add non-interleaved YUV444 pixel format support

Add non-interleaved YUV444 pixel format IPU_PIX_FMT_YUV444P support

Signed-off-by: Wayne Zou <b36644@freescale.com>
11 years agoENGR00182743-2 IPU: Add non-interleaved YUV444 pixel format support
Wayne Zou [Tue, 3 Jul 2012 09:15:54 +0000 (17:15 +0800)]
ENGR00182743-2 IPU: Add non-interleaved YUV444 pixel format support

Add non-interleaved YUV444 pixel format IPU_PIX_FMT_YUV444P support

Signed-off-by: Wayne Zou <b36644@freescale.com>
11 years agoENGR00182743-1 IPU: Add non-interleaved YUV444 pixel format support
Wayne Zou [Tue, 3 Jul 2012 08:59:52 +0000 (16:59 +0800)]
ENGR00182743-1 IPU: Add non-interleaved YUV444 pixel format support

Define IPU_PIX_FMT_YUV444P macro for non-interleaved YUV444 pixel format

Signed-off-by: Wayne Zou <b36644@freescale.com>
11 years agoENGR00218466 WM8962: remove unused variable
Gary Zhang [Thu, 26 Jul 2012 08:24:24 +0000 (16:24 +0800)]
ENGR00218466 WM8962: remove unused variable

remove unused variable

Signed-off-by: Gary Zhang <b13634@freescale.com>
11 years agoENGR00218579-2 Update dynamically change GPU clock implementation
Loren Huang [Fri, 27 Jul 2012 05:12:18 +0000 (13:12 +0800)]
ENGR00218579-2 Update dynamically change GPU clock implementation

It fixed the issue which causes gpu driver can't enter suspend and idle mode.
Signed-off-by: Loren Huang <b02279@freescale.com>
Acked-by: Lily Zhang
11 years agoENGR00218579-1 Update dynamically change GPU clock implementation
Loren Huang [Fri, 27 Jul 2012 05:11:28 +0000 (13:11 +0800)]
ENGR00218579-1 Update dynamically change GPU clock implementation

This patch from vivante.
It fixed the stress test failure issue by disabling all internal clock
before clock updating.

Signed-off-by: Loren Huang <b02279@freescale.com>
Acked-by: Lily Zhang
11 years agoENGR00214565 MX6x, IPUv3: Display lack last horizontal pixel
Sandor Yu [Thu, 26 Jul 2012 07:48:40 +0000 (15:48 +0800)]
ENGR00214565 MX6x, IPUv3: Display lack last horizontal pixel

Update IPU micro code to show the last horizontal line pixel.

Signed-off-by: Sandor Yu <R01008@freescale.com>
11 years agoENGR00218412-2 OV5642:Power down after checking dev id
Liu Ying [Thu, 26 Jul 2012 01:54:13 +0000 (09:54 +0800)]
ENGR00218412-2 OV5642:Power down after checking dev id

This patch powers down camera after checking camera device
id to save power.

Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit eb280a7182cd8c71d698b57a720447f9d9b1174a)

11 years agoENGR00218412-1 OV5640 mipi:Power down after checking dev id
Liu Ying [Thu, 26 Jul 2012 01:52:45 +0000 (09:52 +0800)]
ENGR00218412-1 OV5640 mipi:Power down after checking dev id

This patch powers down camera after checking camera device
id to save power.

Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit a73b70b3d425825b4f4ba99c4c38c23bde227a9a)

11 years agoENGR00172083 SPI-NOR mx6: fix failed erase uboot ENV on SPI-NOR by MFG tool
Robin Gong [Thu, 26 Jul 2012 09:00:48 +0000 (17:00 +0800)]
ENGR00172083 SPI-NOR mx6: fix failed erase uboot ENV on SPI-NOR by MFG tool

In MFG tool will use "flash_eraseall /dev/mtd0" command to erase whole mtd0
partition, but u-boot environment params are stored  in offset 0xc0000 which
exceed the u-boot patition 0x40000, it means the "flash_eraseall" command only
erase u-boot partition, but not environment area. So we need increase the size
of u-boot partition  to 0x100000 as what we remain 1MB for u-boot.
Signed-off-by: Robin Gong <B38343@freescale.com>
11 years agoENGR00215520-04 Mx6:USB host: USB Host1 modulization
make shi [Wed, 25 Jul 2012 02:12:45 +0000 (10:12 +0800)]
ENGR00215520-04 Mx6:USB host: USB Host1 modulization

Disable the host wakeup and put phy to low power mode When the
module be removed, and the requested pre irq should be free.

Signed-off-by: make shi <b15407@freescale.com>
11 years agoENGR00215520-03 Mx6:USB host: USB Host1 modulization
make shi [Wed, 25 Jul 2012 02:10:45 +0000 (10:10 +0800)]
ENGR00215520-03 Mx6:USB host: USB Host1 modulization

- remove mx6_usb_h1_init() in board specific initialization files
- Add module_init(mx6_usb_h1_init) and module_exit(mx6_usb_h1_exit) in usb_h1.c
  to support the usb_h1 modulization
- Export necessary function which is used in usb_h1.c

Signed-off-by: make shi <b15407@freescale.com>
11 years agoENGR00215520-02 Mx6:USB host:USB Host1 modulization
make shi [Wed, 25 Jul 2012 00:59:48 +0000 (08:59 +0800)]
ENGR00215520-02 Mx6:USB host:USB Host1 modulization

MSL headfile part change

-Add and remove some function define in usb.h

Signed-off-by: make shi <b15407@freescale.com>
11 years agoENGR00215520-01 Mx6:USB host: USB Host1 modulization
make shi [Fri, 20 Jul 2012 02:43:09 +0000 (10:43 +0800)]
ENGR00215520-01 Mx6:USB host: USB Host1 modulization

- Add USB_EHCI_ARC_H1 configuration to imx6_defconfig and imx6s_defconfig,
   the default configuration is selected as "y"
- add related USB_EHCI_ARC_H1 configuration to Makefile
- add related USB_EHCI_ARC_H1 configuration to Kconfig

Signed-off-by: make shi <b15407@freescale.com>
11 years agoENGR00217633 Add force contiguous memory pool in gpu driver
Richard Liu [Thu, 26 Jul 2012 02:59:12 +0000 (10:59 +0800)]
ENGR00217633 Add force contiguous memory pool in gpu driver

Add force contiguous memory pool in gpu driver

Signed-off-by: Richard Liu <r66033@freescale.com>
Acked-by: Lily Zhang
11 years agoENGR00215346: mmc: esdhc: change to use sdma instead of adma due to ic limit.
Ryan QIAN [Wed, 25 Jul 2012 05:58:46 +0000 (13:58 +0800)]
ENGR00215346: mmc: esdhc: change to use sdma instead of adma due to ic limit.

Due to ic issue, adma2 failed to work when ahb freq is slow (<50Mhz),
while SDMA does not have issue.

workaround:
- use SDMA instead.

performance comparison between SDMA & ADMA:

| | SDMA | ADMA |
---------------------------------------------------------------------
| wifi downlink* | ~38Mbps | ~38Mbps |
| memory card** | ~20MBps(r)/~4MBps(w) | ~20MBps(r)/~9MBps(w) |

* wifi downlink throughput is tested by iperf in open air.
** writing performance for SDMA is much slower than ADMA, it might
be an issue which needs further investigation.

Signed-off-by: Ryan QIAN <b32804@freescale.com>
11 years agoENGR00216848 MX6 DL dual display failed on HDMI and LVDS
Sandor Yu [Wed, 18 Jul 2012 09:43:39 +0000 (17:43 +0800)]
ENGR00216848 MX6 DL dual display failed on HDMI and LVDS

HDMI output video mode is 1080p, LVDS output is XGA.
The IPU bandwidth is not enough to support the two display output
when IPU HSP clock setting to 200MHz,
increase the IPU HSP clock to 270MHz and dual display can work.

Signed-off-by: Sandor Yu <R01008@freescale.com>
11 years agoENGR00218274 CPUFREQ: fix conservative governor bug
Lin Fuzhen [Wed, 25 Jul 2012 07:09:07 +0000 (15:09 +0800)]
ENGR00218274 CPUFREQ: fix conservative governor bug

When system not boot up all cores, such as adding max_cpus=n,
n<NR_CPUS, then the conservative governor will increase the cpu
frequncy to the highest freq and never get to down.

Signed-off-by: Lin Fuzhen <fuzhen.lin@freescale.com>
11 years agoENGR00182061-4 MXC v4l2 capture:Remove inappropriate msleep code
Liu Ying [Tue, 24 Jul 2012 10:10:23 +0000 (18:10 +0800)]
ENGR00182061-4 MXC v4l2 capture:Remove inappropriate msleep code

msleep() after camera power down should not be called in mxc
v4l2 capture core code. Instead, this should be handled by
camera power down function.

Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
11 years agoENGR00182061-3 MX6 SabreSD:Correct camera pwdn function
Liu Ying [Tue, 24 Jul 2012 10:01:35 +0000 (18:01 +0800)]
ENGR00182061-3 MX6 SabreSD:Correct camera pwdn function

This patch adds 2ms sleep after camera power down signal
is set to high or to low to ensure power down or up
is successful. OV5640/OV5642 camera specs say that they
require this condtion to be true - for PWDN to go low,
power must first become stable(DVDD to PWDN>=1ms), so
this patch simply use 2ms which should be enough.

Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
11 years agoENGR00182061-2 OV5640 mipi camera:Check dev id before register
Liu Ying [Tue, 24 Jul 2012 10:00:08 +0000 (18:00 +0800)]
ENGR00182061-2 OV5640 mipi camera:Check dev id before register

This patch checks camera device id via i2c bus before register
v4l2 internal device.

Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
11 years agoENGR00182061-1 OV5642 camera:Check dev id before register
Liu Ying [Tue, 24 Jul 2012 09:58:03 +0000 (17:58 +0800)]
ENGR00182061-1 OV5642 camera:Check dev id before register

This patch checks camera device id via i2c bus before register
v4l2 internal device.

Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
11 years agoENGR00218070 imx6 battery: fix charger led first wrong indication status
Rong Dian [Tue, 24 Jul 2012 02:34:15 +0000 (10:34 +0800)]
ENGR00218070 imx6 battery: fix charger led first wrong indication status

because boot time gap between led framwork and battery driver init,when system
boots with charger attatched, charger led framwork loses the first charger
online event,add once extra power_supply_changed can fix this issure

Signed-off-by: Rong Dian <b38775@freescale.com>
11 years agoENGR00217936-02 mmc: esdhc: fix unknown controller version for usdhc
Ryan QIAN [Tue, 24 Jul 2012 04:33:40 +0000 (12:33 +0800)]
ENGR00217936-02 mmc: esdhc: fix unknown controller version for usdhc

- Add cpu_is_mx6dq, cpu_is_mx6dl to strengthen the condition.

Note: mx6sl has no such issue because it's fixed by IC, in other word,
mx6sl aligns with sdhc specification.

Signed-off-by: Ryan QIAN <b32804@freescale.com>
11 years agoENGR00217936-01 mmc: esdhc: fix unknown controller version for usdhc
Ryan QIAN [Mon, 23 Jul 2012 07:57:52 +0000 (15:57 +0800)]
ENGR00217936-01 mmc: esdhc: fix unknown controller version for usdhc

SVN value (0x3) defined in fsl host controller on mx6dq/mx6dl differs from
the one (0x2) defined in sdhc specification.

- original 0x11 is an incorrect value, it should be 0x3

Note: mx6sl has no such issue because it's fixed by IC, in other word,
mx6sl aligns with sdhc specification.

Signed-off-by: Ryan QIAN <b32804@freescale.com>
11 years agoENGR00218067 mx6sl LDO_BYPASS: enable LDO BYPASS in mx6sl by default
Robin Gong [Tue, 24 Jul 2012 01:56:28 +0000 (09:56 +0800)]
ENGR00218067 mx6sl LDO_BYPASS: enable LDO BYPASS in mx6sl by default

To validate LDO bypass function fully, enable CONFIG_MX6_INTER_LDO_BYPASS
on u-boot and kernel, only for mx6sl.
Signed-off-by: Robin Gong <b38343@freescale.com>
11 years agoENGR00182271-3 V4L2 OVERLAY: Add IPU2 overaly support for fore ground
Yuxi Sun [Tue, 17 Jul 2012 09:24:51 +0000 (17:24 +0800)]
ENGR00182271-3 V4L2 OVERLAY: Add IPU2 overaly support for fore ground

When vf_rotation > IPU_ROTATE_VERT_FLIP, canncel the MEM_ROT_VF_MEM
- MEM_FG_SYNC channel link and using IPU_IRQ_PRP_VF_ROT_OUT_EOF irq
to trigger double buffer switch.

When vf_rotation <= IPU_ROTATE_VERT_FLIP,cannel the CSI_PRP_VF_MEM
- MEM_FG_SYNC channel link, and using IPU_IRQ_PRP_VF_OUT_EOF to
trigger double buffer switch.

Signed-off-by: Yuxi Sun <b36102@freescale.com>
11 years agoENGR00182271-2 V4L2 OVERLAY: Add IPU2 overlay support of back ground
Yuxi Sun [Tue, 17 Jul 2012 08:35:16 +0000 (16:35 +0800)]
ENGR00182271-2 V4L2 OVERLAY: Add IPU2 overlay support of back ground

Get the ipu device which the display frame buffer is on before start
preview, then request the correspondding display channel irq.

Signed-off-by: Yuxi Sun <b36102@freescale.com>
11 years agoENGR00182271-1 V4L2 capture: Add IPU2 overlay support
Yuxi Sun [Tue, 17 Jul 2012 08:03:00 +0000 (16:03 +0800)]
ENGR00182271-1 V4L2 capture: Add IPU2 overlay support

Add 3 overlay output item for IPU2: DISP4 BG, DISP4 BG - DI1,
DISP4 FG.

Signed-off-by: Yuxi Sun <b36102@freescale.com>
11 years agoENGR00217857: Changed iomux ID pin
Alejandro Sierra [Fri, 20 Jul 2012 18:51:41 +0000 (13:51 -0500)]
ENGR00217857: Changed iomux ID pin

Changed iomux MX6Q ID pin to MX6Q_PAD_ENET_RX_ER__ANATOP_USBOTG_ID
This fix was already implemented on CR ENGR00180424. Somehow this
was not included on newer releases.

Signed-off-by: Alejandro Sierra <b18039@freescale.com>
11 years agoENGR00214404-1 Merge vivante 4.6.9_p4 kernel part code
Loren Huang [Wed, 20 Jun 2012 09:46:43 +0000 (17:46 +0800)]
ENGR00214404-1 Merge vivante 4.6.9_p4 kernel part code

Merge vivante 4.6.9 kernel part code
Updated clock management code
Updated gpu reset code

Signed-off-by: Loren Huang <b02279@freescale.com>
Acked-by: Lily Zhang
11 years agoENGR00217721-5 usb gadget random transfer fail
Tony LIU [Fri, 20 Jul 2012 09:54:35 +0000 (17:54 +0800)]
ENGR00217721-5 usb gadget random transfer fail

usb driver part

- After USB driver prime a bulk transfer(whatever IN or OUT, take
  OUT for example) on ep1, only one dTD is primed, an USB Interrupt
  (bit 0 of USBSTS) will be issued, and find that endptcomplete
  register is 0x2 which means an OUT transfer on ep1 is completed,
  at this time the ep1 out queue head status is 0x1e18000, and next
  dtd pointer is 0x1 which means transfer is done and everything is
  OK, while the dTD token status is 0x2008080 which means this dTD
  is still active, not completed yet.
- Audio SDMA and Ethernet have the similar issue
- root cause is not found yet
- work around:
  change the non-cacheable bufferable memory to non-cacheable
  non-bufferable memory to make this issue disappear.

Signed-off-by: Tony LIU <junjie.liu@freescale.com>
11 years agoENGR00217721-4 implement dma_pool_alloc_nonbufferable interface
Tony LIU [Fri, 20 Jul 2012 09:53:55 +0000 (17:53 +0800)]
ENGR00217721-4 implement dma_pool_alloc_nonbufferable interface

mm core part

- After USB driver prime a bulk transfer(whatever IN or OUT, take
  OUT for example) on ep1, only one dTD is primed, an USB Interrupt
  (bit 0 of USBSTS) will be issued, and find that endptcomplete
  register is 0x2 which means an OUT transfer on ep1 is completed,
  at this time the ep1 out queue head status is 0x1e18000, and next
  dtd pointer is 0x1 which means transfer is done and everything is
  OK, while the dTD token status is 0x2008080 which means this dTD
  is still active, not completed yet.
- Audio SDMA and Ethernet have the similar issue
- root cause is not found yet
- work around:
  change the non-cacheable bufferable memory to non-cacheable
  non-bufferable memory to make this issue disappear.

Signed-off-by: Tony LIU <junjie.liu@freescale.com>
11 years agoENGR00217721-3 implement dma_alloc_noncacheable interface
Tony LIU [Fri, 20 Jul 2012 09:53:05 +0000 (17:53 +0800)]
ENGR00217721-3 implement dma_alloc_noncacheable interface

arch/arm/mm part

- After USB driver prime a bulk transfer(whatever IN or OUT, take
  OUT for example) on ep1, only one dTD is primed, an USB Interrupt
  (bit 0 of USBSTS) will be issued, and find that endptcomplete
  register is 0x2 which means an OUT transfer on ep1 is completed,
  at this time the ep1 out queue head status is 0x1e18000, and next
  dtd pointer is 0x1 which means transfer is done and everything is
  OK, while the dTD token status is 0x2008080 which means this dTD
  is still active, not completed yet.
- Audio SDMA and Ethernet have the similar issue
- root cause is not found yet
- work around:
  change the non-cacheable bufferable memory to non-cacheable
  non-bufferable memory to make this issue disappear.

Signed-off-by: Tony LIU <junjie.liu@freescale.com>
11 years agoENGR00217721-2 add dma_pool_alloc_nonbufferable interface
Tony LIU [Fri, 20 Jul 2012 09:51:22 +0000 (17:51 +0800)]
ENGR00217721-2 add dma_pool_alloc_nonbufferable interface

include/linux head file part

- After USB driver prime a bulk transfer(whatever IN or OUT, take
  OUT for example) on ep1, only one dTD is primed, an USB Interrupt
  (bit 0 of USBSTS) will be issued, and find that endptcomplete
  register is 0x2 which means an OUT transfer on ep1 is completed,
  at this time the ep1 out queue head status is 0x1e18000, and next
  dtd pointer is 0x1 which means transfer is done and everything is
  OK, while the dTD token status is 0x2008080 which means this dTD
  is still active, not completed yet.
- Audio SDMA and Ethernet have the similar issue
- root cause is not found yet
- work around:
  change the non-cacheable bufferable memory to non-cacheable
  non-bufferable memory to make this issue disappear.

Signed-off-by: Tony LIU <junjie.liu@freescale.com>
11 years agoENGR00217721-1 add dma_alloc_noncacheable interface
Tony LIU [Fri, 20 Jul 2012 09:49:47 +0000 (17:49 +0800)]
ENGR00217721-1 add dma_alloc_noncacheable interface

arch/arm/include part

- After USB driver prime a bulk transfer(whatever IN or OUT, take
  OUT for example) on ep1, only one dTD is primed, an USB Interrupt
  (bit 0 of USBSTS) will be issued, and find that endptcomplete
  register is 0x2 which means an OUT transfer on ep1 is completed,
  at this time the ep1 out queue head status is 0x1e18000, and next
  dtd pointer is 0x1 which means transfer is done and everything is
  OK, while the dTD token status is 0x2008080 which means this dTD
  is still active, not completed yet.
- Audio SDMA and Ethernet have the similar issue
- root cause is not found yet
- work around:
  change the non-cacheable bufferable memory to non-cacheable
  non-bufferable memory to make this issue disappear.

Signed-off-by: Tony LIU <junjie.liu@freescale.com>
11 years agoENGR00217128 MX6: support for binding and unbinding console driver
Wayne Zou [Thu, 19 Jul 2012 07:14:39 +0000 (15:14 +0800)]
ENGR00217128 MX6: support for binding and unbinding console driver

Enable CONFIG_VT_HW_CONSOLE_BINDING to support for binding
and unbinding console driver

Signed-off-by: Wayne Zou <b36644@freescale.com>
11 years agoENGR00217717 mfgtool firmware will crash during mfgtool running
Tony LIU [Fri, 20 Jul 2012 02:11:06 +0000 (10:11 +0800)]
ENGR00217717 mfgtool firmware will crash during mfgtool running

- the root cause of this issue is there is no protection for
  the resource which will be accessed by multiple thread

Signed-off-by: Tony LIU <junjie.liu@freescale.com>
11 years agoENGR00217719 usb gadget msc may enumeration fail if msc storage response slow
Tony LIU [Fri, 20 Jul 2012 01:51:17 +0000 (09:51 +0800)]
ENGR00217719 usb gadget msc may enumeration fail if msc storage response slow

- communication between the usb driver and msc class driver is using
  raise_exception/handle_excpetion, such mechaism can only have two
  events(exceptions) at most, one is on processing and another is store to be
  executed after the current one completed.
  If the first one processing is very slow, and the third one occur, then the
  second one will be overwriten by the third one and then the second event is
  lost and then enumeration failed
- since it is the linux community code, it is hard to change the whole frame
  work, currently only a work around is provided
- because this issue is brought in when the first reset event, when this
  event occur, a lun sync will happen and it will cost much time, but in fact
  this lun sync is not necessary for the first reset event, the work around
  is to skip this lun sync.

Signed-off-by: Tony LIU <junjie.liu@freescale.com>
11 years agoENGR00217716 mfgtool host frequently reset bus during transfer
Tony LIU [Fri, 20 Jul 2012 01:28:27 +0000 (09:28 +0800)]
ENGR00217716 mfgtool host frequently reset bus during transfer

- the response in csw to request sense will be 1 due to UTP change
  some storage information
- host will reset the bus if response to request sense is 1
- change the response to 0 if CONFIG_FSL_UTP is defined

Signed-off-by: Tony LIU <junjie.liu@freescale.com>
11 years agoENGR00217732-2: Add dummy clock for DCP/RNGB.
Terry Lv [Fri, 20 Jul 2012 05:55:58 +0000 (13:55 +0800)]
ENGR00217732-2: Add dummy clock for DCP/RNGB.

Add dummy clock for DCP/RNGB.

Signed-off-by: Terry Lv <r65388@freescale.com>
11 years agoENGR00217732-1: revert back rngc code
Terry Lv [Fri, 20 Jul 2012 03:01:29 +0000 (11:01 +0800)]
ENGR00217732-1: revert back rngc code

Revert to rngc code before as we will add dummy clock for it.

Signed-off-by: Terry Lv <r65388@freescale.com>
11 years agoENGR00217643 mx6 sabresd battery:add POWER_SUPPLY_PROP_CAPACITY_LEVEL property
Rong Dian [Fri, 20 Jul 2012 05:37:09 +0000 (13:37 +0800)]
ENGR00217643 mx6 sabresd battery:add POWER_SUPPLY_PROP_CAPACITY_LEVEL property

this battery property provides battery capacity low/normal/full status

Signed-off-by: Rong Dian <b38775@freescale.com>
11 years agoENGR00217598 SSI: improvement for ssi driver
Gary Zhang [Thu, 19 Jul 2012 05:48:51 +0000 (13:48 +0800)]
ENGR00217598 SSI: improvement for ssi driver

SSI driver improvement:
1. add parameter check in imx_ssi_set_dai_clkdiv(),
2. add TX/RX FIFO1 watermark settings,
3. remove the hardcode for watermark setting.

Signed-off-by: Gary Zhang <b13634@freescale.com>
11 years agomm: Hold a file reference in madvise_remove
Andy Lutomirski [Thu, 5 Jul 2012 23:00:11 +0000 (16:00 -0700)]
mm: Hold a file reference in madvise_remove

commit 9ab4233dd08036fe34a89c7dc6f47a8bf2eb29eb upstream.

Otherwise the code races with munmap (causing a use-after-free
of the vma) or with close (causing a use-after-free of the struct
file).

The bug was introduced by commit 90ed52ebe481 ("[PATCH] holepunch: fix
mmap_sem i_mutex deadlock")

[bwh: Backported to 3.2:
 - Adjust context
 - madvise_remove() calls vmtruncate_range(), not do_fallocate()]
[luto: Backported to 3.0: Adjust context]

Cc: Hugh Dickins <hugh@veritas.com>
Cc: Miklos Szeredi <mszeredi@suse.cz>
Cc: Badari Pulavarty <pbadari@us.ibm.com>
Cc: Nick Piggin <npiggin@suse.de>
Signed-off-by: Ben Hutchings <ben@decadent.org.uk>
Signed-off-by: Andy Lutomirski <luto@amacapital.net>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
11 years agonet: l2tp_eth: fix kernel panic on rmmod l2tp_eth
Eric Dumazet [Thu, 7 Jun 2012 00:07:20 +0000 (00:07 +0000)]
net: l2tp_eth: fix kernel panic on rmmod l2tp_eth

[ Upstream commit a06998b88b1651c5f71c0e35f528bf2057188ead ]

We must prevent module unloading if some devices are still attached to
l2tp_eth driver.

Signed-off-by: Eric Dumazet <edumazet@google.com>
Reported-by: Denys Fedoryshchenko <denys@visp.net.lb>
Tested-by: Denys Fedoryshchenko <denys@visp.net.lb>
Cc: James Chapman <jchapman@katalix.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
11 years agonet: sock: validate data_len before allocating skb in sock_alloc_send_pskb()
Jason Wang [Wed, 30 May 2012 21:18:10 +0000 (21:18 +0000)]
net: sock: validate data_len before allocating skb in sock_alloc_send_pskb()

[ Upstream commit cc9b17ad29ecaa20bfe426a8d4dbfb94b13ff1cc ]

We need to validate the number of pages consumed by data_len, otherwise frags
array could be overflowed by userspace. So this patch validate data_len and
return -EMSGSIZE when data_len may occupies more frags than MAX_SKB_FRAGS.

Signed-off-by: Jason Wang <jasowang@redhat.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
11 years agoARM: fix rcu stalls on SMP platforms
Russell King [Thu, 19 Jan 2012 15:20:58 +0000 (15:20 +0000)]
ARM: fix rcu stalls on SMP platforms

commit 7deabca0acfe02b8e18f59a4c95676012f49a304 upstream.

We can stall RCU processing on SMP platforms if a CPU sits in its idle
loop for a long time.  This happens because we don't call irq_enter()
and irq_exit() around generic_smp_call_function_interrupt() and
friends.  Add the necessary calls, and remove the one from within
ipi_timer(), so that they're all in a common place.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
[add irq_enter()/irq_exit() in do_local_timer]
Signed-off-by: UCHINO Satoshi <satoshi.uchino@toshiba.co.jp>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
11 years agoARM i.MX imx21ads: Fix overlapping static i/o mappings
Jaccon Bastiaansen [Mon, 30 Apr 2012 09:53:43 +0000 (11:53 +0200)]
ARM i.MX imx21ads: Fix overlapping static i/o mappings

commit 350ab15bb2ffe7103bc6bf6c634f3c5b286eaf2a upstream.

The statically defined I/O memory regions for the i.MX21 on chip
peripherals and the on board I/O peripherals of the i.MX21ADS board
overlap. This results in a kernel crash during startup. This is fixed
by reducing the memory range for the on board I/O peripherals to the
actually required range.

Signed-off-by: Jaccon Bastiaansen <jaccon.bastiaansen@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
11 years agoENGR00215945-3: caam: Improve error recovery on failed RNG4 kickstart
Steve Cornelius [Wed, 11 Jul 2012 21:48:09 +0000 (14:48 -0700)]
ENGR00215945-3: caam: Improve error recovery on failed RNG4 kickstart

RNG4 requires a kickstart process to transition into running mode.
In the case that this kickstart process errors, the driver is shut
back down (under the assumption that internal random padding of keys
or data cannot occur).

In an isolated case, the kickstart failed to start the RNG, an error
was returned, and the driver attempted to de-register an RNG function
that never completed, causing a crash. (This is difficult to test for
without manual intervention).

Therefore, amended the driver shutdown process to only de-register
the hardware RNG when an instance kickstarted without error.

This does NOT correct the kickstart problem, only the consequences.

Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
Signed-off-by: Terry Lv <r65388@freescale.com>
11 years agoENGR00215945-2: Fix directions in cache coherence functions
Steve Cornelius [Sat, 7 Jul 2012 00:35:55 +0000 (17:35 -0700)]
ENGR00215945-2: Fix directions in cache coherence functions

During a bug search, a review turned up two places where the wrong
direction was used in dma_sync function calls. In practice. these
compiled away to be inconsequential on the platform in question, but
this may not be true on all platforms.

Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
Signed-off-by: Terry Lv <r65388@freescale.com>
11 years agoENGR00215945-1: Rework scatterlist handling for bi-endian platforms
Steve Cornelius [Thu, 5 Jul 2012 23:41:29 +0000 (16:41 -0700)]
ENGR00215945-1: Rework scatterlist handling for bi-endian platforms

Former versions of this (ARM) branch of this driver reworked the hardware-
readable scatter/gather list to operate as a set of 32-bit integers,
rather than a packed structure of smaller sizes, which cannot burst-read
correctly on a little-endian platform.

Integration of caamhash.c revealed subtle ways in which the ordering of
items written to a hardware s/g list could create bugs, such as the
"final" bit being written to an entry that would later be updated with
a size, inadvertently erasing the bit (e.g. such as sg_to_sec4_sg_last()
before sg_to_sec4_sg()).

Since fields must be ORed in to operate correctly using any order of
operations, changed allocations of the combination of extended descriptor
structs + hardware scatterlists to use kzalloc() instead of kmalloc(), so
as to ensure that residue data would not be ORed in with the correct data.

Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
Signed-off-by: Terry Lv <r65388@freescale.com>
11 years agoENGR00217621-02 - SPDC : fix build error enable both SPDC and EPDC
Fugang Duan [Thu, 19 Jul 2012 08:09:46 +0000 (16:09 +0800)]
ENGR00217621-02 - SPDC : fix build error enable both SPDC and EPDC

- Add early param to select SPDC module, which can enable SPDC and
  EPDC modules build in kernel. Fix the build error because they both
  modules use the same gobal varaible.

Signed-off-by: Fugang Duan <B38611@freescale.com>
11 years agoENGR00217621-01 - MSL : Add early param to select SPDC
Fugang Duan [Thu, 19 Jul 2012 08:02:18 +0000 (16:02 +0800)]
ENGR00217621-01 - MSL : Add early param to select SPDC

- Add "spdc" in uboot command line to select SPDC module for
  AUO panel display. By default, EPDC is enabled and SPDC is
  disabled, which are mutually exclusive because they share
  the same data line.

Signed-off-by: Fugang Duan <B38611@freescale.com>
11 years agoENGR00217616 - FEC : fix the typo to avoid build warning
Fugang Duan [Thu, 19 Jul 2012 07:29:52 +0000 (15:29 +0800)]
ENGR00217616 - FEC : fix the typo to avoid build warning

- Fix the typo to avoid kernel build warning.

Signed-off-by: Fugang Duan <B38611@freescale.com>
11 years agoENGR00217590: i.mx6: Add IMX_CHIP_REVISION_1_2 support
Jason Liu [Thu, 19 Jul 2012 03:12:45 +0000 (11:12 +0800)]
ENGR00217590: i.mx6: Add IMX_CHIP_REVISION_1_2 support

Add IMX_CHIP_REVISION_1_2 support for i.mx6q TO1.2

Signed-off-by: Jason Liu <r64343@freescale.com>
11 years agoENGR00215202 - MSL : Ethernet phy LAN8720 cable link issue
Fugang Duan [Thu, 28 Jun 2012 07:29:43 +0000 (15:29 +0800)]
ENGR00215202 - MSL : Ethernet phy LAN8720 cable link issue

- Phy LAN8720 link status is un-stable when disable clock from clock
  enabled status. The phy register_1[link status] bit is pulsatile,
  so driver will print:
   PHY: 1:00 - Link is Up - 100/Full
PHY: 1:00 - Link is Down
PHY: 1:00 - Link is Up - 100/Full
PHY: 1:00 - Link is Down
...

- Because phy clock source is from FEC internel clock, if disbale clock
  from enabled status, some LAN8720 phys status machine is in disorder
  and cannot display link status correctly. So, it need to do phy hw
  reset before clock enable.

Signed-off-by: Fugang Duan <B38611@freescale.com>
11 years agoENGR00217509 ASRC:Use ideal ratio mode for p2p playback
Chen Liangjun [Wed, 18 Jul 2012 03:11:39 +0000 (11:11 +0800)]
ENGR00217509 ASRC:Use ideal ratio mode for p2p playback

When use ESAI p2p playback, ASRC is configured no ratio mode.
Due to an IC bug(TKT117009), user may hear noise sometimes.

In this patch, use ideal ratio mode for ESAI p2p playback to avoid
 noise.

Signed-off-by: Chen Liangjun <b36089@freescale.com>
11 years agoENGR00216270-2 MXC EDID, Update MXC EDID to parse HDMI VDSB
Sandor Yu [Tue, 10 Jul 2012 08:27:13 +0000 (16:27 +0800)]
ENGR00216270-2 MXC EDID, Update MXC EDID to parse HDMI VDSB

Added HDMI vendor specific data block parse to MXC EDID code.

Signed-off-by: Sandor Yu <R01008@freescale.com>
11 years agoENGR00216270-1 MXC EDID add HDMI VSDB variable
Sandor Yu [Tue, 10 Jul 2012 08:24:34 +0000 (16:24 +0800)]
ENGR00216270-1 MXC EDID add HDMI VSDB variable

Define more variable in struct mxc_edid_cfg for HDMI VSDB.

Signed-off-by: Sandor Yu <R01008@freescale.com>
11 years agoENGR00215722 HDMI HCT: Pass TestID:7-33 interoperability with DVI
Sandor Yu [Wed, 4 Jul 2012 10:29:11 +0000 (18:29 +0800)]
ENGR00215722 HDMI HCT: Pass TestID:7-33 interoperability with DVI

Check HDMI VSDB block, only enable HDMI output when EDID with HDMI
VSDB block, enable DVI output when EDID with no HDMI VSDB.

Signed-off-by: Sandor Yu <R01008@freescale.com>
11 years agoENGR00215636 HDMI: Pass HCT TestID 7-19: Packet Types
Sandor Yu [Tue, 3 Jul 2012 09:37:27 +0000 (17:37 +0800)]
ENGR00215636 HDMI: Pass HCT TestID 7-19: Packet Types

HDMI not support deep color output, setting register
VP_PR_CD bits color_depth to 0.(24 bits per pixel video)

Signed-off-by: Sandor Yu <R01008@freescale.com>
11 years agoENGR00215621 HDMI: Pass HCT TestID 7-32: Audio Sample Packet Layout
Sandor Yu [Tue, 3 Jul 2012 08:06:45 +0000 (16:06 +0800)]
ENGR00215621 HDMI: Pass HCT TestID 7-32: Audio Sample Packet Layout

CA index table should followed CEA-861-D table 20.

Signed-off-by: Sandor Yu <R01008@freescale.com>
11 years agoENGR00217306-2: Add DCP/RNGB arch support
Terry Lv [Mon, 16 Jul 2012 07:58:06 +0000 (15:58 +0800)]
ENGR00217306-2: Add DCP/RNGB arch support

This patch will add arch support of DCP/RNGB.

Signed-off-by: Terry Lv <r65388@freescale.com>
11 years agoENGR00217306-1: Add DCP/RNGB driver support
Terry Lv [Mon, 16 Jul 2012 07:48:11 +0000 (15:48 +0800)]
ENGR00217306-1: Add DCP/RNGB driver support

This patch will add driver menu support.
And also, for rng don't need to enable clock, we add operation when no
clock is specified for rng.

Signed-off-by: Terry Lv <r65388@freescale.com>
11 years agoENGR00217388: imx6sl_arm2: Add software poweroff support via SNVS
Robby Cai [Tue, 17 Jul 2012 06:14:35 +0000 (14:14 +0800)]
ENGR00217388: imx6sl_arm2: Add software poweroff support via SNVS

Add s/w poweroff support via SNVS setting.
Use `poweroff' command to power down ARM2 board.

Signed-off-by: Robby Cai <R63905@freescale.com>
11 years agoENGR00216013-4 vpu: add phy address check ioctl.
Zhang Jiejing [Mon, 16 Jul 2012 05:53:26 +0000 (13:53 +0800)]
ENGR00216013-4 vpu: add phy address check ioctl.

this patch is adding a ioctl for vpu to check the phy addr before vpu
start using this addr, this use case is common in some Direct Render case,
the VPU 's framebuffer phy memory is allocate by GPU, if the address given
by GPU have some wrong, like pass a virtual address, vpu will hang the system.

Add this IOCTL to be the goalkeeper, this IOCTL can check whether the phy
address was virtual memory or the address is within phy memory of your DDR.

The phy memory valild check is now doing best effort:
1. check whether is was allocated by vmalloc(), which must be a phy un-continus
2. check whether is was beyound DDR's top address, usually the other driver
   pass a virtual address as a phy address.

Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
11 years agoENGR00216013-3 vpu: add VPU_IOC_PHYMEM_CHECK ioctl.
Zhang Jiejing [Mon, 9 Jul 2012 04:58:16 +0000 (12:58 +0800)]
ENGR00216013-3 vpu: add VPU_IOC_PHYMEM_CHECK ioctl.

Add VPU_IOC_PHYMEM_CHECK ioctl in header file.
This IOCTL will check the phy memory address is valid or not.

Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
11 years agoENGR00216013-2 mx6: not call memblock_free after reserve memory.
Zhang Jiejing [Mon, 16 Jul 2012 05:51:30 +0000 (13:51 +0800)]
ENGR00216013-2 mx6: not call memblock_free after reserve memory.

Remove call memblock_free after reserve memory with memblock_allocate().
The function of memblock_free is to remove the memory block from reserve list
of memblock, it will totally lost the info about how much phy memory
we have.

Skipping call this can make the reserved memory be accountable in
memblock With no side-effect.

After doing this, we can know how much our phy memory is, then can add check
in our driver like(vpu) to check the phy memory valid or not before vpu start
use the address.

Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
11 years agoENGR00216013-1 memblock: add memblock_end_of_DRAM_with_reserved() function.
Zhang Jiejing [Mon, 9 Jul 2012 04:38:05 +0000 (12:38 +0800)]
ENGR00216013-1 memblock: add memblock_end_of_DRAM_with_reserved() function.

add a function to check the end address including reserved memory,
this API can provide the top address of phy memory,
it can be used to check if the phy memory is valild in some driver
like VPU.

Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
11 years agoENGR00217120 mmc: esdhc: implement std tuning for fsl sdhc ip
Ryan QIAN [Mon, 25 Jun 2012 23:39:36 +0000 (07:39 +0800)]
ENGR00217120 mmc: esdhc: implement std tuning for fsl sdhc ip

1. in mx6sl, it adds sd3.0 uhs mode capability indicator bits.
2. in mx6sl, exe_tune and smp_clk_sel bits for standard tuning procedure
have been put in ACMD12_ERR reg

Signed-off-by: Ryan QIAN <b32804@freescale.com>
11 years agoENGR00217122 mmc: esdhc: move sd3.0 tuning routine into pltfm
Ryan QIAN [Fri, 13 Jul 2012 07:11:31 +0000 (15:11 +0800)]
ENGR00217122 mmc: esdhc: move sd3.0 tuning routine into pltfm

in mx6q/dl, move fsl tuning procedure into platform driver code from common
code hacking.

Signed-off-by: Ryan QIAN <b32804@freescale.com>
11 years agoENGR00217371: imx6sl_arm2: Add WDOG_B pad configuration
Robby Cai [Tue, 17 Jul 2012 02:54:11 +0000 (10:54 +0800)]
ENGR00217371: imx6sl_arm2: Add WDOG_B pad configuration

Add missing WDOG_B pad configuration. Default setting is GPIO function
which is not appropriate for WDOG_B generation.

Signed-off-by: Robby Cai <R63905@freescale.com>
11 years agoENGR00217242 [MX6SL]: VDDSOC_CAP voltage to 1.1V in idle mode
Nancy Chen [Tue, 17 Jul 2012 03:52:58 +0000 (22:52 -0500)]
ENGR00217242 [MX6SL]: VDDSOC_CAP voltage to 1.1V in idle mode

Drop VDDSOC_CAP voltage from 1.2V to 1.1V in idle mode.

Signed-off-by: Nancy Chen <Nancy.Chen@freescale.com>
11 years agoENGR00217258 mxc_vpu: return error when ioctl was not supported.
Zhang Jiejing [Mon, 16 Jul 2012 01:51:47 +0000 (09:51 +0800)]
ENGR00217258 mxc_vpu: return error when ioctl was not supported.

MXC_VPU will return 0 if IOCTL don't support, for user space, it think
this IOCTL success, but it's needs actually return a failed return
value.

Signed-off-by Zhang Jiejing <jiejing.zhang@freescale.com>

11 years agoENGR00216961: MMC/SDIO: gate off sdio clk when MMC_POWER_OFF is set
Ryan QIAN [Wed, 11 Jul 2012 00:50:12 +0000 (08:50 +0800)]
ENGR00216961: MMC/SDIO: gate off sdio clk when MMC_POWER_OFF is set

1. For sdio card, only when MMC_POWER_OFF is set,
sdhci_disable_clk will be called for sdio. otherwise sdio clk
will not be gated.
2. Set MMC_CAP_POWER_OFF_CARD caps in esdhc, so that
sdio_bus power off and clock gate off card through
to pm_runtime interface.

Signed-off-by: Ryan QIAN <b32804@freescale.com>
11 years agoENGR00217123 VPU kernel driver: enable/disable PU LDO
Hongzhang Yang [Fri, 13 Jul 2012 10:20:01 +0000 (18:20 +0800)]
ENGR00217123 VPU kernel driver: enable/disable PU LDO

VPU driver will enable/disable PU LDO by calling regulator API

Enable PU LDO in vpu_open
Disable PU LDO in vpu_release

Signed-off-by: Hongzhang Yang <Hongzhang.Yang@freescale.com>
11 years agoENGR00216293 V4L2 output: Check input params for progressive tiled format
Wayne Zou [Fri, 13 Jul 2012 07:01:59 +0000 (15:01 +0800)]
ENGR00216293 V4L2 output: Check input params for progressive tiled format

Check input params for progressive tiled format to remind the application
input wrong params and make driver more robust.

Signed-off-by: Wayne Zou <b36644@freescale.com>
11 years agoENGR00216109 MX6Q/DL clock: VDOA needs OCRAM clock and DDR clock enabled
Wayne Zou [Thu, 5 Jul 2012 05:14:46 +0000 (13:14 +0800)]
ENGR00216109 MX6Q/DL clock: VDOA needs OCRAM clock and DDR clock enabled

VDOA needs OCRAM clock and DDR clock enabled when video playback,
and set bus clock high to finish work quickly.

Signed-off-by: Wayne Zou <b36644@freescale.com>
11 years agoENGR00216976 ESAI: add support for 4,6channel p2p
Chen Liangjun [Fri, 13 Jul 2012 06:11:19 +0000 (14:11 +0800)]
ENGR00216976 ESAI: add support for 4,6channel p2p

Add support for 4, 6 channels p2p playback in ESAI.

Signed-off-by: Chen Liangjun <b36089@freescale.com>
11 years agoENGR00216998: battery: add usb charger voltage offset sysfs interface
Rong Dian [Fri, 13 Jul 2012 05:07:38 +0000 (13:07 +0800)]
ENGR00216998: battery: add usb charger voltage offset sysfs interface

add usb charger voltage offset sysfs interface

Signed-off-by: Rong Dian <b38775@freescale.com>
11 years agoENGR00209905 WM8962: support for continuously playback diff sample bit streams
Gary Zhang [Wed, 11 Jul 2012 02:15:42 +0000 (10:15 +0800)]
ENGR00209905 WM8962: support for continuously playback diff sample bit streams

support for continuously playback different sample bit audio
streams with -Dplughw:0,0 option
such as the command: 'aplay -Dplughw:0,0 16bit.wav 24bit.wav'
before prohibit reenter hw_params, now remove this limitation
to support this feature.

Signed-off-by: Gary Zhang <b13634@freescale.com>
11 years agoENGR00217018 [Mx6 ]Need to set 1.1V as PU default voltage
Anson Huang [Thu, 12 Jul 2012 09:58:11 +0000 (17:58 +0800)]
ENGR00217018 [Mx6 ]Need to set 1.1V as PU default voltage

1. Need to set 1.1V as default PU value, as when first time VPU
or GPU try to enable PU regulator, it will use this default
value as PU voltage setting.
2. For DL, as its default setpoint is set to middle point,
we need to add a usecount for 400M PFD, because when system
enter 24M, it will disable 400M PFD if its previous setpoint
is middle, if not add this usecount when we init the bus freq
setpoint, then the usecount will be wrong when first time system
enter 24M bus mode.

Signed-off-by: Anson Huang <b20788@freescale.com>
11 years agoENGR00216955 MX6 General : Fix a typo when defining OCOTP fuse name
Eric Sun [Thu, 12 Jul 2012 05:28:58 +0000 (13:28 +0800)]
ENGR00216955 MX6 General : Fix a typo when defining OCOTP fuse name

The name in BANK2, "SOTPMK1" should be "OTPMK1"

Signed-off-by: Eric Sun <jian.sun@freescale.com>
11 years agoENGR00216946: battery: increase update period to 2 minutes
Rong Dian [Thu, 12 Jul 2012 03:20:17 +0000 (11:20 +0800)]
ENGR00216946: battery: increase update period to 2 minutes

increase update period to 2 minutes. Due to improper hardware design,
when enable HDCP function, the I2C2 bus pins function is change to DDC
function,the CPU loading is high when I2C failed transfer data via I2C
bus,so decrease battery update voltage frequency.

Signed-off-by: Rong Dian <b38775@freescale.com>
11 years agoENGR00172077 [MX6Q_ARD]TVIN: Kernel dump and Error Messages
Israel Perez [Mon, 9 Jul 2012 16:59:23 +0000 (11:59 -0500)]
ENGR00172077 [MX6Q_ARD]TVIN: Kernel dump and Error Messages

adv7180.c code was not working properly in this new release because some
changes done in mxc_v4l_capture.c driver.
Also mostly of the error messages and kernel dump problem which were related
to csi_enc are already fixed on this release.
In order to fix on previous releases csi and ipuv3 fixes
should be applied or back ported.

Signed-off-by: Israel Perez <B37753@freescale.com>
11 years agoENGR00216031 [MX6]Need to force bus freq to highest point when suspend
Anson Huang [Fri, 6 Jul 2012 11:10:06 +0000 (19:10 +0800)]
ENGR00216031 [MX6]Need to force bus freq to highest point when suspend

1. When bus freq is at 400M setpoint, currently bus freq will not
set to high setpoint when suspend, but some drivers which need
high bus freq enable clock before bus freq resume, so the request
of high bus freq will be ignore until next high bus freq device is
enabled,it will result in some devices need high bus freq but bus freq
dirver stay at med setpoint. So we need to force bus freq to
highest setpoint before suspend to avoid such scenario.

2. Clean up PU LDO turn on/off, move to regulator driver and maintain by
VPU and GPU driver.

Signed-off-by: Anson Huang <b20788@freescale.com>
11 years agoENGR00216282 [MX6 SABREAUTO(ARD)] No mxs-perfmon.0 directory
Eric Sun [Wed, 11 Jul 2012 03:21:17 +0000 (11:21 +0800)]
ENGR00216282 [MX6 SABREAUTO(ARD)] No mxs-perfmon.0 directory

The problem is caused because "mx6_board_init" don't add the
corresponding device node. Problem resolved after add them.

Signed-off-by: Eric Sun <jian.sun@freescale.com>
11 years agoENGR00211653 [MX6Q ARD] IMX UART add support for loopback mode.
Israel Perez [Wed, 30 May 2012 21:00:06 +0000 (16:00 -0500)]
ENGR00211653 [MX6Q ARD] IMX UART add support for loopback mode.

ttymxc serial uart driver add  support loopback mode.
returns TIOCM_LOOP set when reading the status.

Signed-off-by: Israel Perez <B37753@freescale.com>
11 years agoENGR00216327: battery: fail to update battery voltage with usb charger attached
Rong Dian [Tue, 10 Jul 2012 11:23:50 +0000 (19:23 +0800)]
ENGR00216327: battery: fail to update battery voltage with usb charger attached

when usb charger is online, driver also updates battery voltage

Signed-off-by: Rong Dian <b38775@freescale.com>
11 years agoENGR00216254 mx6 sabresd battery:change battery status update strategy
Lin Fuzhen [Tue, 10 Jul 2012 01:57:53 +0000 (09:57 +0800)]
ENGR00216254 mx6 sabresd battery:change battery status update strategy

update the  battery info just when the value is changed.

Signed-off-by: Lin Fuzhen <fuzhen.lin@freescale.com>
11 years agoENGR00215810-2 AHCI: sata drops to 1.5Gbps after suspend/resume several times
Richard Zhu [Tue, 10 Jul 2012 05:14:02 +0000 (13:14 +0800)]
ENGR00215810-2 AHCI: sata drops to 1.5Gbps after suspend/resume several times

Add the AHCI platform suspend/resume function callback to
fix this issue.

Signed-off-by: Richard Zhu <r65037@freescale.com>
11 years agoENGR00215810-1 AHCI: sata drops to 1.5Gbps after suspend/resume several times
Richard Zhu [Tue, 10 Jul 2012 02:31:06 +0000 (10:31 +0800)]
ENGR00215810-1 AHCI: sata drops to 1.5Gbps after suspend/resume several times

Add the AHCI platform suspend/resume function callback to
fix this issue.

Signed-off-by: Richard Zhu <Hong-Xing.Zhu@freescale.com>
11 years agoENGR00216268 Ov5642 camera:Fix green line issue for 2 modes
Liu Ying [Tue, 10 Jul 2012 04:00:17 +0000 (12:00 +0800)]
ENGR00216268 Ov5642 camera:Fix green line issue for 2 modes

This patch fix green line issue on captured frames for
720x480p@30 and 720x576p@30 modes by changing register
0x302c's bit[6:5] to 0'11 to enhance output driving
capability to 4x.

Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
11 years agoENGR00215792 USB:fix gadget issue when boot kernel with USB connected
make shi [Thu, 5 Jul 2012 05:57:59 +0000 (13:57 +0800)]
ENGR00215792 USB:fix gadget issue when boot kernel with USB connected

- USB gadget disconnected when system boot kernel with USB connected. Commit
68b1c60f7f6c436340206679a18d61d9 induce the issue, call dr_discharge_line(1)
to ensure no abnormal usb wakeup interrupt happen after plug out the cable.
There are two cases cause dr_discharge_line(1) of fsl_otg_event() be called.
One case is switch the otg mode form Host mode to Device mode. Another case is
boot kernel with USB connected. The host_first_call is true when system boot
kernel with USB connected, otherwise it is false. So dr_discharge_line(true)
should not be called in fsl_otg_event() if host_first_call is true.

- USBOH3 clock is still on after plug out the cable when boot kernel with USB
connected, If the suspended bit is 0x1 and stopped is 0x0,the case is regarded
as suspend connected to usb charger. USB clock will be turn on, otherwise the
second suspend is processed without USB clock and it causes system hang. But
system boot kernel with cable connected, suspended is 0x1 and stopped is 0x0.
USB clock will be on by mistake. And stopped is cleared in dr_controller_run()
when system boot kernel with USB connected. We should check the suspended and
stopped bit before call dr_controller_run() to fix the issue.

Signed-off-by: make shi <b15407@freescale.com>
11 years agoENGR00215999 Export API for update gpu active clock dynamically
Loren Huang [Fri, 6 Jul 2012 10:59:08 +0000 (18:59 +0800)]
ENGR00215999 Export API for update gpu active clock dynamically

The patch is from vivante.

Signed-off-by: Loren Huang <b02279@freescale.com>
Acked-by: Lily Zhang
11 years agoENGR00216008 ov5642: Add exposure calculation when set mode
Yuxi Sun [Fri, 6 Jul 2012 09:29:03 +0000 (17:29 +0800)]
ENGR00216008 ov5642: Add exposure calculation when set mode

Originally only QSXGA mode use exposure calculation, now we enable
this function on every mode to fix image dark problem.

Signed-off-by: Yuxi Sun <b36102@freescale.com>
11 years agoENGR00216010-3: spdc: Make clock enable/disable paired for PIX and AXI
Robby Cai [Mon, 9 Jul 2012 06:05:59 +0000 (14:05 +0800)]
ENGR00216010-3: spdc: Make clock enable/disable paired for PIX and AXI

Really disable pix/axi clock when SPDC is idle.

Signed-off-by: Robby Cai <R63905@freescale.com>
11 years agoENGR00216010-2: [e|s]pdc: re-initialize the controller after resume
Robby Cai [Fri, 6 Jul 2012 10:07:24 +0000 (18:07 +0800)]
ENGR00216010-2: [e|s]pdc: re-initialize the controller after resume

Because we have DISPLAY power down/up request when do suspend/resume,
EPDC/SPDC has been powered off and powered on again, thus re-initialization
is needed.

Signed-off-by: Robby Cai <R63905@freescale.com>